JPS6331643A - Operation device for x-ray ct apparatus - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention performs preprocessing and reconstruction processing to create an image from collected data regarding a subject, and further performs image processing on the created image. The present invention relates to an arithmetic device for an X-ray CT device.

(Prior art) In an X-ray CT device, an x'fjA detector detects the absorption coefficient of each part of the X-rays irradiated to the target object.
Image reproduction is performed based on this collected data. To do this, the first step is to perform preprocessing and reconstruction processing to create an image from the collected data, and the second step is to perform further image processing such as filtering on the created image. .

In this case, in the first stage preprocessing and reconstruction processing,
Since the data to be processed is input in chronological order, these data are processed in chronological order by Processing Uniso 1-(7'Lossessing Unisoto) 1,2゜3 as shown in Figure 7. The so-called vibe line processing (serial processing) is performed. The data processed in this way is stored in the storage device 4 in sequence.

On the other hand, in the second stage of image processing, the data to be processed is multiple data (2D or 3D data) that has already been obtained, so multiple data are simultaneously imported and processed as shown in Figure 8. Units 5, 6, and 7 perform simultaneous processing, resulting in parallel processing.

Therefore, the conventional arithmetic unit for an X-ray CT apparatus requires two types of hardware configurations corresponding to the two processing methods.

For example, a hardware configuration compatible with a pipeline processing method is fixed to functions suitable for pipeline processing, and it is impossible to apply this to parallel processing.

(Problem to be solved by the invention) In this way, the conventional X'! Since the arithmetic unit for the aCT apparatus requires two types of hardware configurations corresponding to two data processing methods, there is a problem in that the price/performance ratio of the apparatus decreases.

The present invention was made in response to such problems.
It is an object of the present invention to provide an arithmetic unit for an X-ray CT apparatus that has a hardware configuration that can be commonly applied to two different data processing methods.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention connects a plurality of arithmetic units in series and parallel to process data in a desired manner,
A memory unit having an address mapping function is connected to each arithmetic unit, and a controller controls address mapping of each memory unit and data transfer between each memory unit.

(Function) When performing pipeline processing, data processing is performed using the paths of the arithmetic units connected in series, while when performing parallel processing, the data processing is performed using the paths of the arithmetic units connected in parallel. Data processing is performed. In either data processing method, the processed data is stored in a memory unit.

(Embodiment) FIG. 1 is a block diagram showing an arithmetic unit for an X-ray CT apparatus according to an embodiment of the present invention. connected in series and also bus 'I + 12 + 12
are connected in parallel by Each calculation unit 11.
12.13 are connected to memory units 14, 15.16, and each memory unit 14, 15.16 is connected to a world controller 18 via a world brain 17.
(hereinafter referred to as a controller) is connected.

The arithmetic units 11, 12, and 13 are composed of a microprocessor and memory, each consisting of one chip or multiple chips, and have arithmetic functions such as addition, subtraction, and multiplication, shifts, and logical operations. Connected. The paths of buses L+, Lz, and ls constitute a pipeline processing path, and the paths of buses 11, 12, and (1) constitute a parallel processing path.
is programmed into memory unit 14.15.16
is configured so that data stored in it can be transferred.

The memory units 14, 15, and 16 have an address mapping function that allows the address viewed from the controller 18 to be changed by a program under the control of the controller 18, and are configured to allow data transfer between them. .

The controller 18 controls the address mapping function of the memory units 14, 15, 16, and
, 15 and 16. Furthermore, this controller 18 has a broadcast capability to simultaneously transfer data read from one memory unit to one or more memory units 14, 15, 16, thereby providing not only pipeline processing capabilities but also parallel It enables the realization of processing functions.

Next, the operation of this embodiment will be explained.

First, in pipeline processing that performs preprocessing and reconfiguration processing, collected data is dynamically input in a time-series manner to a pipeline processing path consisting of buses L1゜L, , l, as shown in FIG. .12.13 are processed sequentially and in chronological order. In this embodiment, as a typical example of correction processing, reference correction, log correction, and water correction are performed by arithmetic units 1-11, 12, and 13, respectively, and the corresponding equations are listed below.

The collected data d(i) is first input manually to the calculation unit 11, and the data R(i) set in the calculation unit 11 in advance is
i) to perform reference correction. The processed data is transferred to the next stage arithmetic unit 12 via bus L1.
is input and log correction is performed. Similarly, the processed data is manually input to the next stage arithmetic unit 13 via the bus Lx, and water correction is performed. The data processed in this way is stored in the memory unit 16 via bus j23.

In the above, if the multiplication process of the arithmetic unit 11 requires more time than the processing in the other arithmetic units 12 and 13, the arithmetic unit 11 is divided into three units lla and flb as shown in FIG.

It can be changed by a program to divide into 11C and perform partial multiplication in each stage.

At this time, the multiplicand and multiplier are lla and llb for each unit.

It is a requirement that the same data be sent for both 11C,
This can be easily achieved by using the broadcast function of the controller 18 as described above. As mentioned above, the memory units 14, 15, and 16 have an address mapping function that allows the address to be changed to any position when viewed from the controller 1st, so the memory units 14, 15, and 16 can be divided into three
To easily operate a broadcast function by setting the addresses of the three units lla, llb, and llc to be the same as part of the memory addresses of three memory units (not shown) connected to each unit. Can be done.

Next, parallel processing for image processing will be explained. First, by the broadcast function of the controller 18, data 1' and 2' at addresses "1" and "2" of one memory unit 14, for example, are transferred to memory units 15 and 16, respectively, as shown in FIG. The controller 18 previously addresses each address unit 14, 15 .
16, the partial memory of each unit is arranged so as to have a linear address when viewed from the controller 18, and then the data to be processed, such as the above-mentioned "1" and "2", is transferred.

At this time, the data in each memory unit 15, 16 is controlled so that it has the same address when viewed from the corresponding arithmetic unit 12, 13.

As a result, the arithmetic units 12.13 simultaneously process the above data "1" via the parallel processing path 7!2.7!3.
, "2'" processing is performed. This provides processing data.

Subsequently, the controller 18 again controls the address mapping function of the address unit, and the same process is repeated to obtain the desired calculation result.

In the embodiment in this text, an example is shown in which the calculation units 11, 12, 13 are connected to each other one-dimensionally,
The same application can be made to the case of connecting two-dimensionally or three-dimensionally as shown in FIGS. 5 and 6.

〔Effect of the invention〕

As described above, according to the present invention, the hardware configuration that can be commonly applied to different data processing methods such as pipeline processing and parallel processing is provided, so that the price/performance ratio of the device can be improved. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an arithmetic device for an X-ray CT device according to an embodiment of the present invention, FIGS.
and FIG. 6 are block diagrams showing other embodiments of the present invention,
FIGS. 7 and 8 are block diagrams showing conventional examples. 11.12.13... Arithmetic unit, 14.15.1
6...Memory unit, 18...Controller, Ll, L2...Bus (for series), ! ,,A2,1 u... Lotus (for parallel).

Claims (1)

[Claims] In the arithmetic unit for the X-ray CT device, which performs preprocessing and reconstruction processing to create an image from collected data related to the subject, and further processes the created image, there are a plurality of arithmetic units, a plurality of memory units connected to each arithmetic unit and having an address mapping function, and a controller that controls the address mapping function of each memory unit and data transfer between each memory unit. An arithmetic device for an X-ray CT device, characterized in that: