JPS63316126A - Pattern detection circuit - Google Patents

Abstract

PURPOSE:To easily respond to the expansion of the pattern length of a specific pattern or that of the number of allowable errors at the time of detecting correlation, by writing a storage content corresponding to a selected address signal on a storage means. CONSTITUTION:In a detection mode, reception data is converted to parallel data at a serial/parallel conversion part 1, and after being selected at a selection part 2, is supplied to a storage part 3, and the storage part 3 outputs a detecting signal only to an address corresponding to the specific pattern. Also, in a write mode, storage data such as to issue the detecting signal only to the address corresponding to a required specific pattern is written from a write control part 4 to the storage part 3. At this time, address data representing a write address not parallel reception data for the address input of the storage part 3 is selected at the selection part 2. Consequently, since it is possible to change the storage data of the storage part 3 arbitrarily easily, a purpose can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern detection circuit, and more particularly to a pattern detection method for detecting a specific pattern from digital signals transmitted in a digital signal transmission system by exact match detection or correlation detection.

In conventional digital signal transmission systems, a synchronization signal is inserted as a specific pattern different from other data in order to use it as a time reference to distinguish which data is what, for example when multiplexing and transmitting. has been done. On the receiving side, by detecting this synchronization signal, it is used as a time reference for reception timing, and based on this, the received data is separated and demodulated, and the beginning of the received data and its presence or absence are detected. , reproducing the original digital signal. In such a method, detection of a synchronization signal is essential.

To detect the synchronization signal, a reference pattern of the synchronization signal having a predetermined unique pattern is successively compared with the data pattern in the received data series, and a mismatch or coincidence is determined for each corresponding bit. The synchronization signal is detected by In this case, depending on each method, there is a case of perfect match detection in which the synchronization signal is detected as a complete match, and a case of correlation detection in which the synchronization signal is detected by allowing a certain amount of bit error. This number of bit errors allowed to a certain extent is called the allowable number of errors.

Conventionally, as this type of technology, there is a pattern detection method configured using a ROM (read only memory) that is pre-stored so as to output a detection signal only to an address corresponding to a specific pattern (for example, a specific pattern detection method). Publication No. 57-2230). Such a conventional example is shown in FIG. In the detection method shown in FIG. 2, the received data is serially input to the shift register 5, and the output converted to 8-bit parallel data is directly input to the address of the programmed read-only memory (PROM) 6. Supplied to terminals AO to A7.

Now, if the specific pattern ° is, for example, "11100101", in the case of complete match detection, the stored data D is stored only at the address corresponding to this specific pattern.
``1'' is stored in advance for o, and 0'' is stored in other addresses.Also, when detecting a correlation by allowing, for example, a 1-bit error, the address corresponding to this specific pattern and , Furthermore, if there is a transmission error in any one of these specific patterns, 1" is stored as storage data DO in the addresses for the 8 types of patterns, and '0" is stored in the remaining addresses. I'll keep it.

In the detection circuit configured as described above, the received digital data is sequentially input to the shift register 5 in series and shifted by the clock, and the instantaneous 8-bit parallel output is sent to the address input terminals AO to A7 of the PROM 6.
When the specific pattern itself or a pattern in which a transmission error occurs in any one bit of the specific pattern is applied to the address input terminal, the specific pattern detection signal "1" is output from the data output terminal DO of the PROM6. Ru.

By the way, in digital signal transmission systems, different specific patterns are selected among various systems. For example, it is possible to select the optimal pattern for each method, between various teletext systems, between various time division multiplex systems, between various time division multiple access systems, and even among these systems. Because of the necessity, different specific patterns are usually selected for each.

Therefore, it would be very convenient if the detection patterns could be easily changed in accordance with each selected specific pattern, since one pattern detection circuit could be used in common.

However, in the conventional pattern detection method shown in FIG. 2 described above, the contents of the PROM 6 must be rewritten in order to change the specific pattern to be detected. That is, there is a drawback that it is not possible to respond to changes in a specific pattern without making significant changes in software and hardware.

In addition, in conventional methods, for example, in correlation detection that can handle up to a 1-bit error, when searching for the PROM address when a 1-bit error occurs in any bit in an 8-bit pattern, the address is directly determined from a specific pattern. Output data of 0'' is stored as detection data at that address. However,
If the specific pattern is increased in bit length or allowable error number by various methods, for example, from 8 bits to 30 bits, or from 1 bit to 2 bits, It is necessary to find a pattern in which the number of permissible errors is 2 or less from a 30-bit pattern, and 30CO+30C1+30C2=466 patterns must be found one by one.

Therefore, a very complicated operation is required to obtain the stored data to be stored in the PROM, and in such a case, it is not easy to obtain the stored data.

OBJECTS OF THE INVENTION An object of the present invention is to provide a pattern detection circuit that can easily cope with expansion of the pattern length of a specific pattern and expansion of the number of allowable errors during correlation detection.

Structure of the Invention According to the present invention, input serial digital data is converted into parallel digital data, and the parallel digital data matches a predetermined data pattern with a correlation of less than or equal to the allowable error number. A pattern detection circuit that sometimes generates a coincidence detection signal,
storage means that can be read and written; write control means that generates an address signal of the storage means and storage contents corresponding to the address signal; selection means for inputting an address of the storage means, and when the address signal is selected by the selection means, the storage content corresponding to the address signal is written to the corresponding address of the storage means. A pattern detection circuit having the following characteristics is obtained.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a pattern detection circuit according to an embodiment of the present invention. In the figure, 1 is a serial-to-parallel conversion section, 2 is a selection section, 3 is a writable/readable storage section, and 4 is a write control section. Further, 41 is address data for specifying the J:inclusive address of the storage unit 3, 42 is a selection signal for the selection unit 2 to select between parallel data that is the output of the serial-parallel conversion unit 1 or address data 41, and 43 is a selection signal for specifying the address data 41. The storage data 44 is written into the storage section 3, and is a write signal for writing the storage data 43 into the storage section 3.

The received digital data is serially input to the column-parallel converter 1, shifted bit by bit by a clock, and converted into N-bit (N is a natural number) bit parallel data at each moment, and then sent to the selector 2. Supplied.

The write control section 4 controls a write mode for writing the storage data 43 necessary at that time into the storage section 3, or controls a detection mode for detecting a specific pattern.

First, in the write mode, the write control unit 4 generates N-bit parallel address data 4 indicating the address necessary for write-in.
1, and the selection unit 2 outputs this address data 41.
A selection signal 42 is output that selects and supplies it to the storage section 3. In this way, the address data 41 necessary for writing is selected by the selection section 2 and supplied to the storage section 3.

Further, when the write address is determined, the storage data 43 corresponding to the address and the write signal 44 necessary for writing this storage data /13 into the storage section 3 are outputted from the output control section 4. As a result, the storage data corresponding to that address will be written into the storage section 3.

In this way, all the storage data corresponding to each address can be written into the storage section 3. The stored data 43 to be written has the following contents. That is,
For each input address of the storage unit 3, the total number of mismatches for each corresponding bit between that address and a predetermined specific pattern is less than or equal to the allowable number of errors (an integer greater than or equal to 0). The content is such that the stored data is set to 1'' only at certain times, for example, when the address is 2 or less, and is set to O'' at other addresses.

By doing this, when the received parallel data is supplied to the address that is the input of the storage unit 3, a detection signal of 1'' is output as a detection signal indicating that the specific pattern has been detected only if it matches the specific pattern or if the error is 2 bits or less. That's what happens.

Next, in the detection mode, the Yoshikomi control unit 4 uses the selection signal 42
is output to the selection section 2, the received data converted into parallel data is selected, and this parallel data is supplied to the storage section 3. Further, the output of the output signal 44 is stopped so that the storage section 3 is placed in the read mode. This bundled and inputted serial data is converted into parallel data by a serial/parallel converter 1, selected by a selector 2, and then supplied to a storage unit 3.

The storage unit 3 stores storage data that outputs a detection signal when the total of non-political religion for each bit is less than or equal to the allowable number of errors between the supplied parallel data and a preset specific pattern. was written in the previous write mode, so the specific pattern can be detected from the received data by correlation detection. Note that it is clear that if the number of allowable errors is set to 0, complete match detection will be achieved.

Note that in this embodiment, the selection section 2 is shown as if a circuit exists as a hardware, but the actual hardware does not have a selection circuit in particular and is connected to the serial/parallel conversion section 1 and the writing υ.
1 @ section 4 address data 41 output as a high impedance output and directly connect the outputs, that is, by controlling each output as a wire A art OR,
Of course, it is also possible to provide a selection function.

In addition, in the explanation of this embodiment, when the total value of the number of mismatches of each bit is less than or equal to the allowable number of errors, the output is ``1''.

Although I have given an example where the output is "O11" instead of "1", it is clear that the number of mismatches of each bit can be conversely used as the number of matches.In this case, , since the total number of matches for each bit can be treated as more than a certain number of bits, it is easy to do Class 1.

Furthermore, in the storage unit 3, an example is shown in which the input of the storage data 43 and the output of the detection signal are output from separate terminals, but even if these are the same terminal, they are different in each write/detection mode. It is only necessary that the above-mentioned functions cannot be performed separately, and it is clear that it can be applied immediately in that case as well.

In this manner, when the present pattern detection circuit is in the detection mode, the received data is converted into parallel data by the serial/parallel converter 1, selected by the selector 2, and then supplied to the storage unit 3.
The storage unit 3 outputs a detection signal only to an address corresponding to a specific pattern. Further, in the case of the write mode, the write control section 4 writes storage data to the storage section 3 such that a detection signal is output only to an address corresponding to a necessary specific pattern. At this time, as the address input of the storage section 3, the selection section 2 selects address data indicating a write address instead of the parallel received data.

Therefore, it is possible to easily change the stored data in the storage unit 3 at will, so no matter how the specific pattern to be detected changes or even if it changes dynamically over time, the hardware and software will remain the same. There is no need to change the circuit at all, and it can be easily adapted.

In addition, the method of obtaining stored data does not use the conventional method of directly searching for addresses corresponding to a specific pattern one by one, but instead compares each address with a specific pattern bit by bit. If the allowable number of errors is 2 or less, an extremely simple method of storing output data, for example 1", is sufficient in all addresses where the total number of mismatches for each bit is 2 or less. Therefore, it is easy to store. Data can be requested, and since it is simple, there is almost no risk of creating memory data by mistake.

Effects of the Invention As described above, according to the present invention, it is possible to extremely easily cope with expansion of the pattern length of a specific pattern and expansion of the number of allowable errors in correlation detection.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a conventional pattern detection circuit. Explanation of symbols of main parts 1...Serial/parallel conversion section 2...Selection section 3...Storage section 4...Write control section

Claims (1)

[Claims] It converts input serial digital data into parallel digital data, and generates a match detection signal when this parallel digital data matches a predetermined data pattern with a correlation less than the allowable number of error bits. A pattern detection circuit comprising: a storage means that can be read and written; a write control means that generates an address signal of the storage means and storage contents corresponding to the address signal; selection means for alternatively deriving the address signal as an address input of the storage means, and when the address signal is selected by the selection means, the storage content corresponding to this address signal is input to the storage means. A pattern detection circuit characterized in that it writes to the address.