SU1640741A1 - Read-only memory with data correction - Google Patents

Abstract

The invention relates to computing and digital automation, in particular to storage devices. The purpose of the invention is to simplify the device. The goal is achieved by the fact that the device contains an element AND, an element OR b, an element 4 UNBALANCING with corresponding links. When appearing at the address inputs of the information block 1 of the address memory of the faulty cell, in both blocks 3 of the address memory the same address appears at the outputs. As a result, the signal from the output of the element 4 through the element 6 and the inverter 7 selects the corrective memory block 2, in which the address stored in the blocks 3 contains good information. 1 il.

Description

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About 1

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The invention relates to computer technology and digital automation, namely, to memory devices.

The purpose of the invention is to simplify the device.

The drawing shows a functional diagram of the storage device.

. The device comprises an information block 1 of memory, a correction block 2 of memory, two blocks 3 of the address memory, element 4 Non-equivalence, AND 5, element OR 6, inverter 7.

Unit 1 is designed to store information (microinstructions, reference data, etc.).

Block 2 is intended for storing corrective information, i.e. information that, in one way or another, should replace the information of unit 1. These reasons may include defects in the manufacture of unit 1, changes in information due to technological defects during operation of the device, as well as the need to replace the microcommand, etc. It is advisable that block 2 be available for additional programming during operation.

Blocks 3 are designed to issue the address of the corrected number to block 2 with a certain address code at their input. It is advisable that the control units 3, like block 2, are available for additional programming during operation.

Element 4 is designed to isolate cases of information discrepancy at the outputs of the first and second blocks 3, address codes, one of which is fed to the address input of block 2. Therefore, the number of bits of the outputs of blocks 3 and element 4 is equal to the number of address inputs of block 2.

The device works as follows.

The presence of a specific address code at the inputs of the device leads to the appearance at the outputs of blocks 3 of information that determines the need or absence of the need for correction.

When the information on the outputs of the first and second blocks 3 is not equal, the output of the element 4 appears

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0 5 Q

five

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block 1 enable signal. This signal passes through the OR 6 and Р element and includes 1 block. Due to the presence of inverter 7, block 2 is turned off - - If the information on the outputs of the first and second blocks 3 is identical, the output signal of the 4 block of the block 1 is absent. If the inclusion signal of block 1 at the output of element 5 is also not present, block T is turned off, and block 2 is turned on, and the corrected information is output to the device outputs.

At the output of element 5, the turn on signal of block 1 takes place when all the outputs of the first block 3 are in the initial state, i. Thus, block 1 is turned on both when the information on the outputs of blocks 3 is unequal and when the initial state is present on the outputs of the first block 3, i.e. if the input information of the block 2 contains the initial information of the blocks 3, it is turned off, which leads to the exclusion of the same number from the capacity of the block 2.

The information at the outputs of the second block 3 determines the address of the block 2 by which the corrected word is issued.

It is possible that non-adjustable words have the same combination of levels at the inputs of one of blocks 3. For correct correction, it is necessary that these corrected words correspond to different states of the levels at the outputs of blocks 3 and the address inputs of block 2. To resolve this situation, it is advisable that blocks 3 have a backup bit. Then by connecting this backup input of block 3 to that address bus of another group of address inputs that separates these corrected words can be obtained at the outputs Lokov 3 different addresses of block 2. Formula.

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A permanent storage device with information correction containing a memory information block, two groups of address inputs and outputs of which are address inputs and outputs of the device, respectively, two address memory blocks whose inputs are connected to the address inputs of the first and second groups of the information block

e1640741

memory, respectively, corrective and second memory blocks of the address, corresponding to the memory block, the outputs of which are connected indirectly, the inputs of the I and I element to the outputs of the information block, the address inputs of the corrective memory, the inverter whose output is connected to the memory block accordingly, the outputs are dinene with the input of the selection of the corrective element AND and the element of the Unequal memory block, the difference being connected to the first and second e c. which, for the sake of simplicity, by the inputs of the OR element, respectively, it contains the AND element, the OR element,. the output of which is connected to the input of the VALUE UNIFORM, the inputs of the JQ of the information storage unit and the latter are connected to the outputs of the first input of the inverter.

Claims (1)

Permanent memory correction information containing 50 G with an information memory block, two groups of address inputs and outputs of which are address inputs and outputs of the device ⁵⁵ , respectively, two address memory blocks whose inputs are connected to the address inputs of the first and second groups of the information memory block, respectively, a correcting memory block, the outputs of which connected to the outputs of the memory information block, an inverter, the output of which is connected to the sample input of the correction memory block, which can be used in that, for the sake of simplicity, it contains the AND element, the OR element , the element DISEQUALITY, the inputs of which are connected to the outputs of the first and second memory blocks of the address, respectively, and the ^ inputs of the element And and the address inputs of the correcting g memory block, respectively, the outputs of the element And the element of Inequality are connected to the first and second inputs of the OR element, respectively, the output of which is connected with the input of the high side of the memory information block and the inverter input.