KR0128055Y1 - Error correction apparatus - Google Patents

Abstract

A system for correcting an error occurring in D2 MAC packet type audio data by using a size factor extracted from the acoustic data, wherein the acoustic data is stored in units of code blocks that are error correction standards and correspond to the acoustic data of a predetermined code block. The configuration of an error correction device which delays the sound data of the code block until the extraction of the magnitude factor is completed, has the effect of simplifying the circuit configuration of the control means for controlling the input and output of data.

Description

Acoustic Data Error Correction Device in D2 MAC Packet System

1 is a 15-bit long acoustic signal sample.

2 is a conceptual diagram showing a correlation between a code range CR of a linear code, a protection range PR, and a magnitude factor SF.

3 is a conceptual block diagram illustrating a conventional error correction apparatus for extracting magnitude and correcting an error in a D2 MAC packet type acoustic signal.

Figure 4 is a circuit diagram showing an acoustic data error correction apparatus according to an embodiment of the present invention.

5 is a timing diagram of a memory controller.

* Explanation of symbols for main parts of the drawings

41: size factor extraction unit 42, 43: RAM

44: micom 45: address generator

46: register 47: logic sum circuit

48: logical multiplication circuit 49: error control unit

The present invention relates to a sound data error correcting apparatus in a D2 MAC packet system, and more particularly, a process of extracting a scale factor from sound data at a receiver and correcting an error of the sound data using the extracted size factor. The present invention relates to an acoustic data error correcting apparatus having a function of synchronizing a magnitude factor with an acoustic data.

In the D2 MAC packet system using satellite communication for television broadcasting, digitally divided audio signals are time-division multiplexed and transmitted in the form of packets. Divided. However, in the following description, only the linear code first protection level mode of 15 bits per sample including 14 bits of acoustic data and 1 bit of parity check bits is used.

FIG. 1 shows a 15-bit long audio signal sample, in which a parity bit Pi of a linear coded first-level audio data is loaded in a bit region up to X ₀ , the most significant bit (LSB). One configured audio signal sample is shown.

In the following description, the parity coverage area is set to 11 bits from X ₁₃ to X ₃ in FIG. 1, and the error checking method is an even parity check method, that is, parity so that the number of data having the bit value '1' in the parity application area is even. A parity check method is used to determine bit values.

FIG. 2 is a conceptual diagram illustrating a correlation between a coding range (CR), a protection range (PR), and a scale factor (SF) of a linear code. Here, the bit area indicated by 'X' is a bit area in which both bit values '1' and '0' are possible, and R ₂ , R ₁ , and R ₀ are used to distinguish the components of the size factor. The size factor SF determines the number of bits having the same bit value from the maximum significant bit MSB.

In case of transmitting stereo sound signal, D2 MAC packet system forms one 'sign block' with 64 sound signal samples, and the remaining 32 samples in the right channel of stereo among the sound signal samples in the code block. Assign. When the transmitter determines the size factors for each of the two channels and inserts them into the audio signal samples, the receiver extracts the size factors from the transmitted sound signal samples and then corrects the error in the sound signal using the extracted size factors. The method of inserting the magnitude factor into the stereo sound signal in the D2 MAC packet system will be described in detail as follows.

In the stereo method, the size factor is determined for each of the left and right channels, so the size factor of the left channel is S _L = (S _2L , S _1L , S _0L ), and the size factor of the right channel is S = (S _2R , S _1R , S _0R ). When the code range CR and the protection range PR are determined by a predetermined method, as shown in FIG. 2, the magnitude factor S _L or S _R placed in the same row as the determined protection range PR is determined. Determined by the size factor of the sample or channel. For example, when the coding range CR is '2' and the protection range PR is also '2', the magnitude factor at that time is '110', that is, R ₂ = 1, R ₁ = 1, R ₀ = It becomes zero. The relationship between the protection range and the size factor is shown in Table 1 below.

If the size factor (S) of the left channel and the size factor (S) of the right channel are determined by the protection range corresponding to each channel, the parity of each acoustic signal sample in the stereo system inserts the size factor into only the first 54 samples. A new parity bit Pi 'is generated by performing an exclusive OR of the bits Pi and the components of the magnitude factor. A method of generating a new parity bit Pi 'is as follows.

Pi ′ = Pi 1s S, where i = 1,7,13,19,25,31,37,43,49

Pi ′ = Pi 1s S, where i = 3,9,15,21,27,33,39,45,51

Pi ′ = Pi 1s S, where i = 5,11,17,23,29,35,41,47,53

Pi ′ = Pi 1s S, where i = 2,8,14,20,26,32,38,44,50

Pi ′ = Pi 1s S, where i = 4,10,16,22,28,34,40,46,52

Pi ′ = Pi 1s S, where i = 6,12,18,24,30,36,42,48,54

In the above formula, the numbers corresponding to 'i' are the identification numbers of the acoustic signals, and S or S represents the components of the left channel or right channel size factors. When the size factors S and S are transmitted on the 15-bit linear codes of the stereo sound signal in a manner of replacing the parity Pi of the acoustic signal sample with the new parity Pi ', the error correction apparatus of the receiving side is inputted. The magnitude factors S and S are extracted from the sound signal, and the error is corrected.

3 is a conceptual block diagram illustrating a conventional error correction apparatus for extracting magnitude and correcting an error in a D2 MAC packet type acoustic signal. The size factor extracting unit 31 extracts size factors S and S from sound data input in packet units, that is, in 48 sample units. When the extracted magnitude factors S and S and the above-described sound data are input to the magnitude factor inserting unit 32, the magnitude factor inserting unit 32 may include 64 sound signal samples, that is, sound data belonging to one code block. The above-described extracted size factors are stored until they are stored in the memory 33, and the acoustic data belonging to one code block is completely stored in the memory 33, and the above-described size factors corresponding to the code block are stored in the memory ( 33). The memory controller 34 outputs the magnitude factors corresponding to the acoustic data stored in the memory 33 while maintaining the continuity of the data. That is, the error adjusting unit 35 outputs the magnitude factor among the predetermined code blocks and the corresponding size factors to the error adjusting unit 35 so that the error correction unit 35 can easily perform error correction, and then outputs the acoustic data of the code block to the error adjusting unit. Output to (35).

In the conventional error correction device as described above, the acoustic data of the D2 MAC packet type is stored in the same memory, and then the magnitude factor is first outputted among the magnitude factors and the acoustic data associated with each other using a memory controller, and the acoustic data is output later. There is a problem in that the hardware of the memory controller for controlling the synchronous output of the size factor and the size is complicated.

An object of the present invention for solving the above problems is to store the acoustic data in a code block unit and to store the acoustic data stored in the memory until the extraction of the size factor corrects an error of the acoustic data stored in the memory. The present invention provides a sound data error correcting device in a D2 MAC packet system that can synchronize predetermined sound data and a magnitude factor for its error correction by delaying an output.

The object of the present invention as described above, in the device for correcting the error occurred in the D2, MAC packet type acoustic data, receiving the acoustic data and extracting the magnitude factor from the acoustic data of the predetermined code block, and then the A magnitude factor extraction unit for outputting acoustic data, a first storage unit for storing the acoustic data output from the magnitude factor extraction unit in the code block unit, a second storage unit for storing the extracted magnitude factor, and Delaying the acoustic data stored in the first storage unit to synchronize the acoustic data belonging to the predetermined code block with the magnitude factor stored in the second storage unit and used for error correction of the acoustic data belonging to the predetermined code block. D2 MAC including a control unit and an error control unit for receiving the output data of the first storage unit and the second storage unit to correct the error of the sound data It is achieved by the sound data error correcting apparatus in a kit system.

Hereinafter, a sound data error correcting apparatus in a D2 MAC packet system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram illustrating an acoustic data error correcting apparatus according to an exemplary embodiment of the present invention, and illustrates an acoustic data error correcting apparatus that stores acoustic data in two RAMs in units of 64 acoustic signal samples. .

5 is a timing diagram of a memory controller, and illustrates a timing diagram for controlling memory write / read of acoustic data and size factors. In addition, the numbers displayed between (c) and (d) of FIG. 5 show that 48 samples form one packet among a code block composed of 64 sound signal samples.

The apparatus of FIG. 4 includes a size factor extractor 41 for receiving digital data and extracting a size factor, and a first ram 42 and a second having a capacity of 1 kilobit (1 Kbit) for storing sound data. A RAM 43, a register 46 for storing the size factor, a memory controller for controlling data input and output of the RAM 42, 43, and the register 46, and a size factor and sound data. It includes an error adjusting unit 49 for correcting the error of. A logic sum circuit 47 is connected to the output ends of the first ram 42 and the second ram 43, and a control signal of the memory controller is provided as an input terminal between the logic sum circuit 47 and the error controller 49. And a logical multiplication circuit 48 for receiving the output data of the logical sum circuit 47 as another input terminal.

The above-described memory controller applies the latch signal SCF_LAT to the register 46 and the read signal R_EN to the AND circuit 48, and the control signal CNTL of the microcom 44. It is provided with a address generator 45 for receiving the input to supply the read / write address to the above-described RAM (42, 43). The microcomputer 44 has a read / write enable signal RAM_EN output terminal for reading and writing data to and from the RAMs 42 and 43 by the address signal generated by the address generator 45.

The magnitude factor extracting unit 41 calculates a parity bit value for each sample of acoustic data input in units of packets. That is, in the parity application area and parity area of the acoustic signal sample consisting of 12 bits Pi to X in FIG. 1, the number of bit values is counted as '1', and if the number of bit values is '1', odd number (odd If the number of parity and the bit value is '1' is even, it is determined as even parity. The acoustic signal sample whose parity is determined is output from the magnitude factor extracting unit 41 and stored in the RAM 42 or 43. The parity data obtained from the acoustic signal sample is stored in a memory built in the size factor extracting unit 41.

The microcomputer 44 reads and writes each of the first RAM 42 and the second RAM 43 using the RAM read / write enable signal RAM_EN of FIG. 5A which is inverted at the code block interval. To control. When the 'low' signal of the read / write signal RAM_EN is a writeable signal and the 'high' signal is a readable signal, the first RAM 42 is writable by the low signal in the pulse of FIG. The second RAM 43 is in a readable state. When the microcomputer 44 receiving the packet enable signal PAC_EN of FIG. 5 (b) controls the address generator 45 to generate and output the address for the packet enable time (CNTL), the magnitude factor extracting unit After parity is determined at 41, the acoustic data of the first packet to be output is stored in the first RAM 42 in accordance with the packet enable signal PAC_EN and the address of the address generator 45.

The magnitude factor extracting unit 41 continuously determines the parity of acoustic signal samples and stores the parity of the acoustic signal samples in an internal memory, and stores a sample group corresponding to a predetermined component (S or S) of the magnitude factor, for example, S component. In the sample group consisting of sample numbers 1, 7, 13, 19, 25, 31, 37, 43, and 49, the parity value determined above is an odd parity number and an even parity number. Determined by the component value of the component (S in the above). That is, if the number of odd parity is large, the component value of the size factor is '1', and if the number of even parity is large, the component value is determined as '0'. In the same manner, all six magnitude factor components corresponding to the sample group are obtained from the 54 acoustic signal samples of one code block.

The extracted size factors S and S are stored in the register 46. However, the amplitude factors S and S for the left and right channels of the stereo sound signal can be extracted using only 54 sound signal samples, but 64 sound signal samples form a code block that becomes an error correction range. Accordingly, the extracted magnitude factors S and S are generated in the microcomputer 44 and are not output from the register 46 by the magnitude factor latch signal SCF_LAT having a low level. When 64 sound signal samples are stored in the first RAM 42, the microcomputer 44 switches the first RAM 42 into a readable state, and the second RAM 43 switches into a writable state. The latch signal SCF_LAT having a magnitude of 5 degrees (d) is output to the register 46, and the readable signal R_EN of FIG. 5 (e) is applied to the logic sum circuit 47. In addition, the microcomputer 44 controls the address generator 45 to generate the address signal. The data stored in the first RAM 42 outputs the logic sum circuit 47 by the read / write enable signal RAM_EN 'high', and the acoustic data belonging to the code blocks in the order output from the size factor extractor 41 is It is stored in the second ram 43. The sound data output from the logical sum circuit 47 is output to the error control unit 49 by the high level readable signal R_EN applied to the logical multiplication circuit 48. In addition, the magnitude factors S and S output from the register 46 are also input to the error control unit 49 by the magnitude factor latch signal SCF_LAT.

The above-described size factors S and S obtained using 54 samples have corresponding protection ranges as shown in FIG. Accordingly, the error control unit 49 applies the protection range determined by the magnitude factors S and S to the same binary value of the bit value within the protection range by applying the X bit from each sample of the stereo sound signal shown in FIG. Change it to a value. For example, if the protection range is 4, X to X are matched with the same bit value. Therefore, an error occurring within the protection range among the errors occurring in the data transmission is corrected.

According to the acoustic data error correcting apparatus of the D2 MAC packet system of the present invention as described above, when the acoustic data is stored for each code block that is the unit of error correction, the extraction of the magnitude factor that corrects the error occurring in the acoustic data of the predetermined code block By delaying the sound data of the code block until this is completed, there is an effect that the circuit configuration of the controller for synchronizing the sound data with the magnitude factor and outputting them can be simplified.

Claims (3)

An apparatus for correcting an error occurring in D2 MAC packet type audio data, comprising: receiving acoustic data, extracting a magnitude factor from acoustic data of a predetermined code block, and then outputting the extracted magnitude factor and acoustic data; Wow; A first storage unit for storing the acoustic data output from the magnitude factor extracting unit in the code block unit; A second storage unit for storing the extracted size factor; By delaying the sound data stored in the first storage unit, the data is stored in synchronization with the magnitude factor used in the error correction of the sound data stored in the second storage unit and the sound data belonging to the predetermined code block. A control unit; And an error control unit which receives the output data of the first storage unit and the second storage unit and corrects an error of the acoustic data. 2. The memory device of claim 1, wherein the first storage unit comprises a first memory for storing sound data belonging to a predetermined code block, and a second memory for storing sound data belonging to a code block corresponding to the order of the predetermined code block. Audio data error correction device in the D2 MAC packet system characterized in that. The memory device of claim 2, wherein the controller is further configured to make the second memory writable when the first memory is in a readable state, and to make the second memory readable when the first memory is in a writable state. And a address generator for generating a read / write address of the memories according to a control signal of the microcomputer and a microcomputer for controlling a memory.