JPS63316091A - Video display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video display device that displays images such as characters and figures, and more specifically, a CRT (cathode ray t).
The present invention relates to a video display device using the UBE.

[Prior Art] Conventionally, a video display device using a CRT, for example, is known as a video display device that displays characters, figures, etc. according to video information input manually from the outside, and is used in input/output devices such as computers. has been done.

This type of video display device includes a CRT controller and a CRT display device, which will be described below. First, a CRT controller is a circuit that outputs a video signal, a synchronization signal, etc. in accordance with video information output from a computer or the like. The CRT display device is a device that displays images on a CRT according to the video signal, synchronization signal, etc.
A device consisting of a deflection circuit, a brightness modulation circuit, etc. [Problems to be Solved by the Invention] However, in such a video display device, when trying to display thin lines close to the resolution limit of the CR7 display device, the CRT The problem was that the display at the top became thinner and harder to see. This phenomenon will be explained using FIG. 6. This figure corresponds to the case where white IIIg on a black background is displayed on a CRT.

In other words, by repeating the video signal in the same figure at a predetermined vertical synchronization frequency, a thin white line perpendicular to the horizontal scanning line appears on the CRT.
displayed above.

Here, first, the video signal is a digital signal that is generated by a CRT controller in accordance with video information output from a computer or the like and manually input to a CR7 display device.

Next, the display brightness is the brightness displayed on the CRT according to the video signal, and the visual threshold is the brightness displayed on the CRT according to the video signal.
This is the brightness that is the threshold when humans look at the above image and judge that it is white or black. The display duty ratio is the area ratio between white and black that is visually recognized on the CRT.

As shown in the figure, in the conventional video display device, since the responsiveness of display brightness is poor, the pulse width T1 of the video signal. If I is close to the resolution limit of the display device, the display brightness will not rise sufficiently and the period TH over which the visual threshold is exceeded will be shortened. As a result, the display duty ratio deteriorates, that is, C
This has caused a phenomenon in which the width TH of the white line on RT becomes narrower than the width T- corresponding to the video signal. As described above, when displaying a straight line perpendicular to the horizontal scanning line, the pulse width of the video signal becomes shorter than when displaying a straight line parallel to the horizontal scanning line, so this phenomenon is particularly noticeable. there were.

Also, when displaying a thin black line on a white background on a CRT,
A similar phenomenon occurred because the characteristics shown in FIG. 6 were reversed.

By the way, the above-mentioned phenomenon can be prevented by improving the responsiveness of display brightness and increasing the resolution of the CR7 display device. However, in order to increase the resolution of the CR7 display device, it is necessary to improve the frequency characteristics of the deflection circuit and the phosphor material applied to the phosphor screen. In this case, the circuit configuration is more complex than that of a normal CR7 display device, requiring the use of a large number of components and high-quality materials.
This has the disadvantage of increasing costs and decreasing reliability.

Therefore, the present invention provides a video display device that can suitably display thin lines on a CRT close to the resolution limit by simply adding a simple circuit for video signal correction to a conventional video display device. The purpose is to

[Means for Solving the Problems] The present invention, which has been made to solve the above problems, includes at least a video signal generating means for outputting a video signal, and a display for displaying a video on a CRT based on the video signal. A video signal display device comprising: further comprising: an extension means for extending the pulse width of the video signal and outputting the video signal; and a correction limit signal generating means for generating a correction limit signal according to a correction allowable maximum pulse width predetermined for the video signal based on the resolution of the display means; A corrected image that generates a corrected video signal in which the pulse width of the video signal is extended and corrected based on the signal and the correction limit signal, and outputs it to the display means only when the video signal is equal to or less than the correction allowable maximum pulse width. The gist of the present invention is a video display device characterized by comprising a signal generating means.

[Function] In the video display device of the present invention, the video signal generating means outputs at least a video signal, and the display means displays the video on a CRT based on the video signal.

Further, the extension means outputs a signal obtained by extending the pulse width of the video signal, and the correction limit signal generation means generates a signal from the video signal and a reference signal of a constant period corresponding to the minimum display unit of the video signal. , the corrected video signal generating means generates a correction limit signal according to a predetermined correction allowable maximum pulse width for the video signal based on the resolution of the display means, and the corrected video signal generating means・Based on the above-mentioned correction limit signal and the above-mentioned correction limit signal, only when the above-mentioned video signal is below the above-mentioned correction permissible maximum pulse width, generate a corrected video signal in which the pulse width of the above-mentioned video signal is extended and corrected, and output it to the above-mentioned display means. to work.

[Embodiments] In order to further clarify the structure and operation of the present invention described above, preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing a video display device as an embodiment of the present invention. The video display device shown in the figure is CR
In addition to the T controller 1 and the CR7 display device 2, a correction limit signal generation circuit 3 and a delay circuit 4 (corresponding to extension means in the claims of the present patent application) are provided as circuits for correcting video signals.
and a corrected video signal generation circuit 5. In this embodiment, a case will be described in which only a pulse corresponding to the minimum display unit on a CRT, that is, one dot (hereinafter referred to as one dot pulse) out of a pulse train included in a video signal is corrected. The configuration and operation of each circuit will be explained in detail below.

First, the CRT controller 1 is a circuit that outputs digital signals such as a video signal (2), a synchronization signal, and a clock signal in response to video information output from a computer or the like (not shown). Here, the video signal (2) is a signal corresponding to the brightness of each dot of the video displayed on the CRT, and the synchronization signal is a signal that determines the display position of each dot. Further, the clock signal is a signal with a constant period that serves as a reference for the video signal (2), and the period is the pulse width of one dot pulse.

Next, the CR7 display device 2 is a device that displays an image on a CRT based on a corrected video signal (■) obtained by correcting the video signal (■) and a synchronization signal, and is a well-known device consisting of a CRT (not shown), a deflection circuit, a brightness modulation circuit, etc. This is a CRT display device.

Further, the correction limit signal generation circuit 3 generates a correction target pulse,
That is, this circuit generates a correction limit signal (2) for prohibiting correction of a pulse having a pulse width larger than a one-dot pulse, and is composed of D-type flip-flops 6.7. The D-type flip-flop 6 uses the video signal (2) and the clock signal as a data human input signal (D human input signal) and a clock human input signal (CK input signal), respectively, and outputs a data output signal (Q output signal). And the D type flip-flop 7 is
The Q output signal and clock signal of the D-type flip-flop 6 are respectively used as a data input signal (D input signal) and a clock input signal (CK input signal), and a data output signal (Φ output signal).
is output as a correction limit signal ■.

The delay circuit 4 is a circuit that delays the video signal (2) by a predetermined time and outputs a delayed signal (2), and includes, for example, a delay circuit using a capacitor and a resistor, a delay circuit using a propagation delay time of a gate circuit, It can be configured with a well-known circuit such as a shift register.

Then, the corrected video signal generation circuit 5 generates a corrected video signal ■ based on the video signal ■, the correction limit signal ■, and the delay signal ■.
This circuit generates AND gate 8. 9. 10
and an OR gate 11. First, AND
8, 9, and 10 are circuits that select two of the three signals, the video signal (2), the correction limit signal (2), and the delay signal (2), and output the logical product thereof. That is, the AND gate 8 outputs the logical product of ■ and ■ out of the above three signals as the output signal ■, the AND gate 9 outputs the logical product of ■ and ■ as the output signal ■, and the AND gate 10 outputs the logical product of ■ and ■ as the output signal ■. The AND of ■ and ■ is output as an output signal ■.

Then, the OR gate 11 receives these output signals ■.

The logical sum of ■ and ■ is output as a corrected video signal ■.

The specific operation of the video display device of this embodiment described above is as follows.
The correction operations performed by the correction limit signal generation circuit 3, the delay circuit 4, and the correction video signal generation circuit 5 will be mainly explained using the timing charts shown in FIGS. 2 to 5.

FIG. 2 shows a signal (hereinafter referred to as positive 1
This figure shows the correction operation in the case of a dot pulse (referred to as a dot pulse). This corresponds to displaying a white line with the minimum line width on a black background on a CRT.

In other words, by repeating the video signal shown in the figure at a predetermined vertical synchronization frequency, the white m line perpendicular to the horizontal scanning line is
Displayed on RT. The correction operation shown in the figure will be explained below.

First, the video signal ■ is processed by the correction limit signal generation circuit 3.
After delaying by 1.5 Tc, it is inverted to generate the correction limit signal ■. At the same time, the delay circuit 4 delays the video signal (2) by a predetermined delay time To to produce a delayed signal (2). Here, the delay time T[+ is a value that is a correction amount when extending and correcting the pulse width of the video signal (2), and is, for example, a value of about 20 to 30% of the period Tc of the clock signal.

Next, the signals (■) and (■) are converted to the AN
A manual input is made to the D gate 8, and the logical product is outputted as an output signal ■. Similarly, by AND gates 9 and 10, respectively,
The logical product of ■ and ■, and the logical product of ■ and ■ are taken, and the output signals ■ and ■ are output.

Then, these output signals ■, ■, ■ are connected to an OR gate 11.
manually, and output the logical sum as a corrected video signal ■.

The corrected video signal ■ generated as described above is a signal that rises at the same time as the video signal ■ rises and falls simultaneously with the fall of the delayed signal ■, and its pulse width is wider by To than before correction. ing. Therefore, C
On RT, the maximum value of the display brightness is larger than the characteristic before correction shown by the broken line, and the period in which the display brightness exceeds the visual threshold becomes longer. As a result, the white line, which was conventionally displayed thin, is displayed thicker, and the display duty ratio is improved to be equal to the duty ratio of the video signal (2).

Note that the above correction amount depends on the resolution of the CRT display device.
The delay time TD of the delay circuit 4 can be set, but its maximum value is limited by Tc/2. In other words, the second
Even if the delay time To of the delayed signal ■ shown in the figure is greater than or equal to Tc/2, the amount of correction of the finally generated corrected video signal ■ will be Tc/2 because the logical product with the correction limit signal ■ is taken. That's true.

Therefore, even if the delay time To becomes abnormally large compared to the set value due to power supply voltage fluctuations, temperature changes, component deterioration, etc., the correction amount will be limited to Tc/2 and the display duty ratio will deteriorate significantly. There's nothing to do.

FIG. 3 shows a correction operation when the video signal (2) is a signal (hereinafter referred to as a negative one-dot pulse) that remains at a low level only for a period equal to the period Tc of the clock signal. This corresponds to displaying a black line with the minimum line width on a white background on a CRT. That is, by repeating the video signal shown in the figure at a predetermined vertical synchronization frequency, a thin black line perpendicular to the horizontal scanning line is displayed on the CRT. In the figure, the signal levels of the signals ■, ■, ■ are reversed from those in FIG. 2. Therefore, the finally generated corrected video signal ■ is a signal that falls at the same time as the video signal ■ falls and rises simultaneously with the rise of the delayed signal ■, and has a pulse width wider by To than the video signal ■. It has become.

Therefore, on the CRT, the minimum value of display brightness is smaller than the characteristic before correction shown by the broken line, and the period in which the display brightness is lower than the visual threshold becomes longer. As a result, the black line, which was conventionally displayed thin, is displayed thicker, and the display duty ratio is improved to be equal to the duty ratio of the video signal (2).

Figure 4 shows that the video signal ■ is a 1-dot pulse A with alternating positive and negative signals.
1. A2. A correction operation in the case of A3... is shown. This corresponds to the case where white lines and black lines with the minimum line width are alternately displayed on the CRT. That is, by repeating the video signal shown in the figure at a predetermined vertical synchronization frequency, white lines and black lines perpendicular to the horizontal scanning line are alternately displayed on the CRT.

In this case, only the first positive one-dot pulse A1 is
Correction is made in the same manner as in the case of FIG. That is, in the finally generated corrected video signal (2), only the first positive one-dot pulse B1 is extended and corrected by To, and the subsequent negative or positive one-dot pulse B2 . The pulse width of B3・◆φ remains unchanged at Tc.

When only the first positive one-dot pulse A1 is corrected in this manner, the display luminance characteristic shifts upward as a whole, that is, in a direction in which the display luminance increases, compared to the characteristic before correction shown by the broken line. Therefore, the period in which the display brightness exceeds the visual threshold becomes longer, and the white line, which was conventionally displayed thin, is displayed thicker.

As a result, the display duty ratio is improved to be close to the duty ratio of the video signal (2). Also, since only the first positive one-dot pulse A1 is corrected, the positive and negative one-dot pulses AI, A2 . Even if A3◆◆◆ continues for a long time, unlike the case where all one-dot pulses are corrected, the extension correction amount To of each pulse will not be accumulated and the deviation of the display position will not become large.

In the video display device of this embodiment, even when the signal level of the video signal (2) is opposite to that shown in FIG. Extend and correct only the negative one-dot pulse. In this case as well, effects similar to those described above can be obtained.

FIG. 5 shows the correction operation when the video signal (2) includes a 2-dot pulse, that is, a pulse with a pulse width twice that of a 1-dot pulse. In the figure, the video signal (2) includes a positive one-dot pulse CI, a negative two-dot pulse C2, and a positive two-dot pulse C3. By repeating the video signal shown in the figure at a predetermined vertically equivalent frequency, a plurality of thin lines perpendicular to the horizontal scanning line, that is, a white line with a minimum ljA width, a black line with a line width twice the minimum line width, and a white line are created. displayed continuously.

In such a case, in principle, only one dot pulse is corrected, and pulses of two or more dots are not corrected. However, even if the pulse is 2 or more dots, there is an exception if it is immediately after a 1-dot pulse, and the pulse width is corrected to be shortened. That is, in the corrected video signal ■, the pulse width of the first positive one-dot pulse D1 is corrected to be extended by To, the pulse width of the next negative two-dot pulse D2 is corrected to be shortened by To, and the pulse width of the following negative two-dot pulse D3 is corrected to be shortened by To. Width is 2T
It remains unchanged at C.

The reason for correcting only the one-dot pulse in this way is that in the CR7 display device of this embodiment, pulses of two or more dots (for example, the two-dot pulse C3 in FIG. 5) have either the maximum value or the minimum value of display brightness. This is because the display duty ratio does not deteriorate as in the case of a one-dot pulse, and no correction is required, since the display duty ratio reaches a sufficient level (saturation level). As mentioned above, in the video display device of this embodiment, CR
7 Based on the resolution of the display device, the one-dot pulse C1 that requires correction is extended and corrected, so as in the case of correcting all pulses, the display duty ratio can be adjusted by correcting pulses of two or more dots that do not need correction. There is no possibility that the display position becomes worse or that the extension correction amount TO of all pulses is accumulated and the display position shift becomes large.

Also, a 2-dot pulse D2 immediately after the 1-dot pulse D1
Since the correction is made to shorten by To, the extension correction amount To of the one-dot pulse D1 is canceled out, and the display position will not shift thereafter.

In this embodiment described above, only one dot pulse is the target of correction, but the pulse to be corrected can be changed according to the resolution of the CRT display device 2, and the change can be made by changing the D of the correction limit signal generation circuit 3. This is possible by changing the number of stages of the type flip-flops 6 and 7. For example, if up to 2 dot pulses are to be subject to correction, by adding another stage of D-type flip-flops and further delaying the correction limit signal ■ by Tc (clock signal period), correction can also be made for 2 dot pulses. becomes possible.

[Effects of the Invention] As explained above, according to the present invention, by simply adding a simple circuit to the conventional device, the pulse width can be reduced only when the pulse width of the video signal is less than or equal to a predetermined pulse width. Therefore, thin lines can be suitably displayed on a CRT close to the resolution limit.

Moreover, since it does not require improvements such as increasing the resolution of the CR7 display device, which would result in an increase in the number of parts, it is also excellent in terms of cost and reliability.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a video display device as an embodiment of the present invention, FIGS. 2 to 5 are timing charts showing its operation, and FIG. 6 is a timing chart showing the operation of a conventional video display device. It is a chart. 1φφ◆CRT controller 2...CR7 display device 3...Correction limit signal generation circuit 4...Delay circuit 5...Correction video signal generation circuit

Claims (1)

[Scope of Claims] 1. A video display device comprising at least a video signal generating means for outputting a video signal, and a display means for displaying a video on a CRT based on the video signal, further comprising: extending means for extending the pulse width and outputting it; a correction limit signal generation means for generating a correction limit signal according to a predetermined correction permissible maximum pulse width; A video display device comprising: corrected video signal generation means for generating a corrected video signal by extending and correcting the pulse width of the video signal only when the pulse width is equal to or less than the pulse width, and outputting the corrected video signal to the display means.