JPS6331430U

JPS6331430U -

Info

Publication number: JPS6331430U
Application number: JP12625386U
Authority: JP
Priority date: 1986-08-18
Filing date: 1986-08-18
Publication date: 1988-03-01

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の概略構成図である
。１……ＣＰＵ、５……メインメモリ、６……カ
ードエツジコネクタ、７……アドレスバス、８…
…コントロールバス、９……データバス、１２…
…マイクロスイツチ、１３……判別手段、１３ａ
……デコーダ、１３ｂ……Ｄフリツプフロツプ、
１５……ＡＮＤゲート（リセツト信号制御手段）
、１６……リセツト信号発生回路。 FIG. 1 is a schematic diagram of an embodiment of the present invention. 1...CPU, 5...Main memory, 6...Card edge connector, 7...Address bus, 8...
...Control bus, 9...Data bus, 12...
...Micro switch, 13...Discrimination means, 13a
...Decoder, 13b...D flip-flop,
15...AND gate (reset signal control means)
, 16...Reset signal generation circuit.

Claims

[Scope of utility model registration request]

In an electronic device equipped with a replaceable memory cartridge in which part of the memory is packaged, a switch means for requesting the generation of a reset signal when the memory cartridge is removed, and a switch means for requesting generation of a reset signal when the memory cartridge is removed, and a switch means for requesting generation of a reset signal when the memory cartridge is removed, and a switch means for requesting generation of a reset signal when the memory cartridge is removed, and a switch means for requesting generation of a reset signal when the memory cartridge is removed; a determination means for determining whether or not a process is being executed; and a request for generation of a reset signal by the switch means;
and reset signal control means for generating a control signal when the determination means determines that information processing is not being executed on the memory in the cartridge;
An electronic device comprising: reset signal generating means for generating a reset signal in response to a control signal from the reset signal controlling means.