JPS6331409Y2 - - Google Patents

Info

Publication number
JPS6331409Y2
JPS6331409Y2 JP1981081715U JP8171581U JPS6331409Y2 JP S6331409 Y2 JPS6331409 Y2 JP S6331409Y2 JP 1981081715 U JP1981081715 U JP 1981081715U JP 8171581 U JP8171581 U JP 8171581U JP S6331409 Y2 JPS6331409 Y2 JP S6331409Y2
Authority
JP
Japan
Prior art keywords
hybrid integrated
integrated circuit
circuit
frame
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981081715U
Other languages
Japanese (ja)
Other versions
JPS57193239U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981081715U priority Critical patent/JPS6331409Y2/ja
Publication of JPS57193239U publication Critical patent/JPS57193239U/ja
Application granted granted Critical
Publication of JPS6331409Y2 publication Critical patent/JPS6331409Y2/ja
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は混成集積回路、特に1対の回路基板を
用いて1つの気密空間を構成せしめた混成集積回
路の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit, and particularly to the structure of a hybrid integrated circuit in which a pair of circuit boards are used to form one airtight space.

従来、絶縁基板の一方の面に複数個の回路素子
を形成及び搭載するとともに、該基板の端部に複
数個のリード端子を取着し、かつ、該基板を用い
て主回路領域が収納される気密空間を構成する混
成集積回路は、DIP(デユアル・インライン・パ
ツケージ)型と、SIP(シングル・インライン・
パツケージ)型とがある。
Conventionally, a plurality of circuit elements are formed and mounted on one surface of an insulating substrate, a plurality of lead terminals are attached to the edge of the substrate, and the main circuit area is housed using the substrate. The hybrid integrated circuits that make up the hermetic space are of the DIP (dual inline package) type and the SIP (single inline package) type.
There is a package (package) type.

第1図はDIP型混成集積回路の斜視図、第2図
はその概略側断面図、第3図はSIP型混成集積回
路の概略側断面図を示したものである。
FIG. 1 is a perspective view of a DIP type hybrid integrated circuit, FIG. 2 is a schematic side sectional view thereof, and FIG. 3 is a schematic side sectional view of a SIP type hybrid integrated circuit.

第1図及び第2図において、従来のDIP型混成
集積回路1は、セラミツクスにてなる基板2と、
複数個の回路素子3と、セラミツクスにてなるカ
バー4と、基板2お左右対向端部にそれぞれ取着
された複数個のリード端子5頭で構成され、素子
3を形成及び搭載してなる基板2の上の主回路領
域は、基板2とカバー4とが構成する気密空間6
に収納される。
1 and 2, a conventional DIP type hybrid integrated circuit 1 includes a substrate 2 made of ceramics,
A board comprising a plurality of circuit elements 3, a cover 4 made of ceramics, and a plurality of five lead terminals attached to the left and right opposing ends of the board 2, on which the elements 3 are formed and mounted. The main circuit area above 2 is an airtight space 6 formed by the board 2 and the cover 4.
is stored in.

第3図において、従来のSIP型混成集積回路1
1は、セラミツクスにてなる基板12と、複数個
の回路素子13と、セラミツクスにてなるカバー
14と、基板12の一方の端部に取着された複数
個のリード端子15等で形成され、素子13を形
成及び搭載してなる基板12の上の主回路領域
は、基板12とカバー14とが構成する気密空間
16に収納されている。
In Figure 3, a conventional SIP type hybrid integrated circuit 1
1 is formed of a substrate 12 made of ceramics, a plurality of circuit elements 13, a cover 14 made of ceramics, a plurality of lead terminals 15 attached to one end of the substrate 12, etc. The main circuit area on the substrate 12 on which the elements 13 are formed and mounted is housed in an airtight space 16 formed by the substrate 12 and the cover 14.

このように、従来構成になる混成集積回路は、
回路基板とカバーとが1対1で対応して主回路領
域の気密空間を構成し、該回路の集積密度は各回
路素子の微細化及び搭載技術の改善等で対処する
一方、該回路をプリント板等に実装する密度は回
路基板及びカバーの小形化等で対処してきた。し
かし、前記対処には製造装置を含めた技術的困難
性と限界とがあり、現在はその極限に到達してい
る。
In this way, hybrid integrated circuits with conventional configurations are
The circuit board and cover correspond one-to-one to form an airtight space in the main circuit area, and while the integration density of the circuit is addressed by miniaturizing each circuit element and improving mounting technology, the circuit is printed. The density of mounting on boards has been addressed by downsizing circuit boards and covers. However, the above solution has technical difficulties and limitations including the manufacturing equipment, and the limits have now been reached.

本考案の目的は前記極限を打破した混成集積回
路構造を提供することであり、この目的はセラミ
ツクス等にてなる絶縁枠体を挟んで積重ね該枠体
との接合部を気密封止した1対の基板は、それぞ
れの一方の面に形成した主回路領域が前記枠体の
包囲内で対向し、前記枠体の外方へ延長する前記
基板の端部に取着した複数個のリード端子が、前
記1対の基板のそれぞれの前記端部に接続する1
対の挟挿入部を一体に形成してなることを特徴と
した混成集積回路により達成される。
The purpose of the present invention is to provide a hybrid integrated circuit structure that overcomes the above-mentioned limitations.The purpose of this invention is to provide a hybrid integrated circuit structure in which a pair of insulating frames made of ceramics or the like are stacked and the joints with the frame are hermetically sealed. The main circuit areas formed on one side of each board face each other within the enclosure of the frame, and a plurality of lead terminals are attached to the ends of the board extending outward from the frame. , 1 connected to the ends of each of the pair of substrates.
This is achieved by a hybrid integrated circuit characterized by integrally forming a pair of sandwiched insertion parts.

以下、図面を用いて本考案を説明する。 The present invention will be explained below with reference to the drawings.

第4図は本考案の一実施例に係わる混成集積回
路の概略側断面図、第5図は前記混成集積回路に
用いた絶縁枠体の斜視図、第6図は前記混成集積
回路に用いたリード端子の一部分の拡大斜視図で
ある。
FIG. 4 is a schematic side sectional view of a hybrid integrated circuit according to an embodiment of the present invention, FIG. 5 is a perspective view of an insulating frame used in the hybrid integrated circuit, and FIG. 6 is a schematic side sectional view of a hybrid integrated circuit according to an embodiment of the present invention. FIG. 3 is an enlarged perspective view of a portion of the lead terminal.

第4図において、混成集積回路51へ1対のセ
ラミツクス基板52及び53と、基板52及び5
3にそれぞれ形成及び搭載された回路素子54及
び55と、セラミツクス枠体26と、基板52及
び53の対向延長端部に共通取着した複数個のリ
ード端子56等で構成される。
In FIG. 4, a pair of ceramic substrates 52 and 53 and a pair of ceramic substrates 52 and 5 are connected to a hybrid integrated circuit 51.
3, a ceramic frame 26, and a plurality of lead terminals 56 commonly attached to opposing extended ends of substrates 52 and 53.

基板52と53は、セラミツクスよりなり第5
図に示す如き角形枠体26を挟んで積重ね、その
各接続面をエポキシ系樹脂接着剤等で気密封止し
回路素子54又は55を形成及び搭載した基板5
2及び53の主回路領域が、基板52及び53並
びに枠体26で構成する気密空間57の内側にて
対向するようにされる。
The fifth substrates 52 and 53 are made of ceramics.
Boards 5 are stacked with square frames 26 in between as shown in the figure, each connection surface of which is hermetically sealed with an epoxy resin adhesive, etc., and circuit elements 54 or 55 are formed and mounted thereon.
The main circuit areas 2 and 53 are arranged to face each other inside an airtight space 57 formed by the substrates 52 and 53 and the frame 26.

一方、各リード端子56は第6図に示す如く、
基板52の端部に取着するためのフオーク状挟挿
部56′と、基板53の端部に取着するためのフ
オーク状挟挿部56″とが、切抜き曲げ加工手段
で一体形成してなる。即ち、各リード端子56が
同一方向に突出する混成集積回路51は、第1図
に示す従来構成の2個の混成集積回路1を一体化
し、かつ、相方の集積回路1がリード端子56を
介して電気的に共通接続されたDIP型構成であ
る。
On the other hand, each lead terminal 56 is as shown in FIG.
A fork-shaped clamping part 56' for attaching to the end of the board 52 and a fork-shaped clamping part 56'' for attaching to the end of the board 53 are integrally formed by cutting and bending processing means. That is, the hybrid integrated circuit 51 in which each lead terminal 56 protrudes in the same direction is obtained by integrating two hybrid integrated circuits 1 of the conventional configuration shown in FIG. It is a DIP type configuration with electrical common connections via.

なお、上記実施例においてはセラミツクスにて
なる枠体を使用しているが、絶縁性を有するプラ
スチツク等にて該枠体を形成することができる。
また、本考案になる混成集積回路の冷却性を高め
るため、回路基板の相方又は一方の裏面に放熱板
や放熱フインを接着することもよい。
Although the frame made of ceramics is used in the above embodiment, the frame may be made of insulating plastic or the like.
Furthermore, in order to improve the cooling performance of the hybrid integrated circuit according to the present invention, a heat sink or a heat sink may be bonded to the back surface of one or the other side of the circuit board.

以上説明した如く本考案によれば、1対の回路
基板と絶縁枠体および、一対の該基板の回路を相
互接続するリード端子とを具え、従来の2個を一
体化した混成集積回路が構成され、該回路をプリ
ンタ板等に実装する所要スペースは、従来構成に
な1個の混成集積回路のそれとほぼ等しいため、
実質(収納)的に高密度で所要実装スペースの小
さい混成集積回路を実現し得た実用上の効果があ
る。特に、回路基板の両面に搭載できないベアチ
ツプを含み大形化した従来の集積回路が、本考案
によつて向かい合わせの2枚の回路基板に分割し
構成することが回路変更なしに可能となり、コン
バクト構成になると共に、その実装スペースが狭
くて済む効果は極めて大きい。
As explained above, according to the present invention, a hybrid integrated circuit comprising a pair of circuit boards, an insulating frame, and lead terminals for interconnecting the circuits of the pair of circuit boards, unlike the conventional two integrated circuits, is constructed. The space required to mount the circuit on a printer board, etc., is approximately equal to that of one hybrid integrated circuit in the conventional configuration.
This has the practical effect of realizing a hybrid integrated circuit that has high density in terms of storage and requires small mounting space. In particular, conventional integrated circuits that have become large and include bare chips that cannot be mounted on both sides of a circuit board can now be divided into two circuit boards facing each other without changing the circuits, making it possible to create a compact circuit. In addition to the structure, the effect that the mounting space is small is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来構成になるDIP型混成集積回路の
斜視図、第2図は前記DIP型混成集積回路の概略
側断面図、第3図は従来構成になるSIP型混成集
積回路の概略側断面図、第4図は本考案の一実施
例に係わる混成集積回路の概略側断面図、第5図
は前記混成集積回路に用いた絶縁枠体の斜視図、
第6図は前記混成集積回路に用いたリード端子の
一部分の拡大斜視図、である。 図中において、1,11,51,は混成集積回
路、2,12,52,53は回路基板、3,1
3,54,55,は回路素子、5,15,56は
リード端子、6,57は気密空間、26は枠体、
56′,56″はリード端子56のフオーク状挟挿
部、を示す。
Figure 1 is a perspective view of a DIP type hybrid integrated circuit with a conventional configuration, Figure 2 is a schematic side sectional view of the DIP type hybrid integrated circuit, and Figure 3 is a schematic side sectional view of a SIP type hybrid integrated circuit with a conventional configuration. 4 is a schematic side sectional view of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 5 is a perspective view of an insulating frame used in the hybrid integrated circuit.
FIG. 6 is an enlarged perspective view of a portion of the lead terminal used in the hybrid integrated circuit. In the figure, 1, 11, 51 are hybrid integrated circuits, 2, 12, 52, 53 are circuit boards, 3, 1
3, 54, 55 are circuit elements, 5, 15, 56 are lead terminals, 6, 57 are airtight spaces, 26 is a frame body,
Reference numerals 56' and 56'' indicate fork-shaped insertion portions of the lead terminals 56.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板の上に複数個の回路素子を形成及び搭載し
てなる主回路領域を気密空間に収納するととも
に、前記基板の端部に複数個のリード端子を取着
してなる混成集積回路において、セラミツクス等
にてなる絶縁枠体を挟んで積重ね該枠体との各接
合部を気密封止した1対の基板は、それぞれの一
方の面に形成した主回路領域が前記枠体の包囲内
で対向し、前記枠体の外方へ延長する前記基板の
端部に取着した複数個のリード端子が、前記1対
の基板のそれぞれの前記端部に接続する1対の挟
挿部を一体に形成してなることを特徴とした混成
集積回路。
In a hybrid integrated circuit in which a main circuit area in which a plurality of circuit elements are formed and mounted on a substrate is housed in an airtight space, and a plurality of lead terminals are attached to the ends of the substrate, ceramic A pair of substrates are stacked with an insulating frame made of materials such as the like and hermetically sealed at each junction with the frame, and the main circuit areas formed on one side of each substrate face each other within the framework of the frame. and a plurality of lead terminals attached to the ends of the substrates extending outward from the frame integrally connect a pair of clamping portions connected to the ends of each of the pair of substrates. A hybrid integrated circuit characterized by being formed by forming.
JP1981081715U 1981-06-03 1981-06-03 Expired JPS6331409Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981081715U JPS6331409Y2 (en) 1981-06-03 1981-06-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981081715U JPS6331409Y2 (en) 1981-06-03 1981-06-03

Publications (2)

Publication Number Publication Date
JPS57193239U JPS57193239U (en) 1982-12-07
JPS6331409Y2 true JPS6331409Y2 (en) 1988-08-22

Family

ID=29877215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981081715U Expired JPS6331409Y2 (en) 1981-06-03 1981-06-03

Country Status (1)

Country Link
JP (1) JPS6331409Y2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61166148A (en) * 1985-01-18 1986-07-26 Sanyo Electric Co Ltd Multilayer hybrid integrated circuit device
JPH0433657Y2 (en) * 1986-09-25 1992-08-12
JP5951967B2 (en) * 2011-11-22 2016-07-13 日本碍子株式会社 Circuit board for peripheral circuit of large capacity module and large capacity module including peripheral circuit using the circuit board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729319Y2 (en) * 1975-12-04 1982-06-26
JPS5812445Y2 (en) * 1977-10-14 1983-03-09 東光株式会社 Semiconductor integrated circuit container

Also Published As

Publication number Publication date
JPS57193239U (en) 1982-12-07

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