JPS63312710A - Variable attenuator - Google Patents

Abstract

PURPOSE:To obtain an excellent high frequency variable attenuator to be able to decrease a distortion by forming the FET of the serial part of a pi type high frequency attenuator by plural FETs. CONSTITUTION:Plural FETs 101-104 are pi-type-connected serially and in parallel. At the serial part of a pi type connection, plural FETs 101 and 102 are used. Then, by controlling the potential of attenuating quantity control terminals 111 and 112, a desired attenuating quantity is obtained. Thus, an excellent high frequency variable attenuator to be able to decrease the distortion is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a variable attenuator for high frequencies that has low distortion, low loss, wide band, and low power consumption.

2. Description of the Related Art In recent years, with the miniaturization and reduction in power consumption of high-frequency equipment, there has been a growing demand for high-frequency variable attenuators to be integrated and to reduce power consumption.

A conventional high frequency variable attenuator will be explained below.

FIG. 3 shows a circuit diagram of a conventional π-type attenuator. In FIG. 3, 301 to 303 are field effect transistors (hereinafter abbreviated as FET) 304 to 30.
6 is a resistor, 307 is a high frequency input terminal, 308 is a high frequency output terminal, 309.310 is an attenuation amount control terminal, 311.3
12 is ground.

The operation of the π-type attenuator configured as described above will be described below.

The high frequency signal input from the high frequency input terminal 307 is F
It passes through the drain-source of ET301 and is output to the high-frequency output terminal 308, but if the gate potential of FET301 is controlled by the attenuation amount control terminal 309 and the drain-source resistance of FET301 is changed, the high-frequency output changes accordingly. It changes accordingly. At this time, the input/output impedance changes, so by controlling the potential of the attenuation amount control terminal 310, the drain-source resistance of the FETs 302 and 303 is changed to perform input/output matching.

Problems to be Solved by the Invention However, in the conventional configuration described above, as the gate bias is deepened, the I-■ characteristic shifts from the zero bias curve 401 to the curve 402, as shown in FIG.
This has the disadvantage that distortion occurs in the output signal due to the strong nonlinearity of the FET. In FIG. 4, the curve 403 is the locus of the current saturation point, and the curve 404 is the saturation voltage (Vs-t).
405 is an input signal (level).

The present invention solves the above-mentioned conventional problems, and aims to provide a low-distortion high-frequency attenuator that suppresses the occurrence of distortion.

Means for Solving the Problems In order to achieve this object, the attenuator of the present invention connects a plurality of FETs in series and parallel in a π-shape, and connects a plurality of FETs or a plurality of FETs in the series part of the π-shape connection. It has a configuration using an FET having two gates.

As can be seen from FIG. 4, the distortion due to the nonlinearity of the FET increases as the input signal increases. In other words, F
The smaller the signal voltage applied between the drain and source of the ET, the smaller the distortion.

Therefore, according to the present invention, the voltage applied to one FET can be reduced to 1/the number of FETs, and as a result, output signal distortion can be reduced.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an equivalent circuit diagram of a high frequency variable attenuator in a first embodiment of the present invention. In FIG. 1, 101 to 104 are FETs.

105 to lO8 are resistors, 109 is a high frequency input terminal, 11
0 is a high frequency output terminal, and 111 and 112 are attenuation amount control terminals.

The high frequency variable attenuator configured as above is
Similar to the conventional π-type attenuator, the attenuation amount control terminal 111
By controlling the potentials of and 112, a desired amount of attenuation can be obtained. By using two FETs 10I and 102 in the π-shaped series part in this way, the FE of the circuit part is
Compared to the case of one T, the cross modulation (1M3) ratio is approximately +1
An improvement effect of 0 dB was obtained. (When the attenuation amount is 20 dB) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is an equivalent circuit diagram of an attenuator showing a second embodiment of the present invention. In the same figure, 201 to 203 are F
ET, 204 to 207 are resistors, 208 is a high frequency input terminal, 209 is a high frequency output terminal, 210 and 211 are attenuation amount control terminals, and 212 and 213 are grounding. The difference from the configuration in Figure 1 is that FETs 101 and 102 are dual gate FETs.
This is the point where it was replaced with ET201.

The operation of the high frequency attenuator configured as above is as follows.
Exactly the same as the first embodiment, dual gate FET
By using 201, an improvement effect of +10 dB in cross modulation (1M3) ratio was obtained compared to the case of a single gate FET. (When the attenuation amount is 20 dB) In the first embodiment shown in the first figure, the F of the π-shaped stone row part
Although two ETs, FET10I and 102, are used, the same or better effect can be obtained by using three or more FETs. In addition, the FET of the π-type parallel section is FET103
, 104 are used, but a plurality of them may be used.

In addition, in the second embodiment shown in the second diagram, the FET 201
Although a dual-gate FET is used in this example, the same or better effect can be obtained by using an FET having a plurality of gates.

Further, although single gate FETs are used as the FETs 202 and 203, FETs having a plurality of gates may be used.

Alternatively, it goes without saying that similar effects can be obtained by appropriately combining the first embodiment and the second embodiment.

Effects of the Invention As described above, the present invention has an excellent advantage of reducing distortion by configuring the FET in the series section of the π-type high frequency attenuator with a plurality of FETs or an FET having a plurality of gates. This makes it possible to realize a variable attenuator for high frequencies.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of a high frequency variable attenuator according to a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a high frequency variable attenuator according to a second embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram of a high frequency variable attenuator according to a second embodiment of the present invention. An equivalent circuit diagram of a variable attenuator for π water high frequency, and FIG. 4 is an IV characteristic diagram of an FET. 101-104.201-203...FET,
105~108.204~207...Resistance, 1
09゜208...High frequency input terminal, 110.2
09...High frequency output terminal, 111, 112, 2
10.211...Attenuation control terminal, 113,1
14,212°213... Ground. Name of agent: Patent attorney Toshio Nakao One idiot Figure 1

Claims (1)

[Claims] A variable attenuation characterized in that a plurality of field effect transistors are connected in series and parallel in a π-shape, and a plurality of field-effect transistors or multi-gate field-effect transistors are arranged in the series part of the π-shape connection. vessel.