CN116505912B - Full positive control low additional phase shift attenuator - Google Patents

Full positive control low additional phase shift attenuator Download PDF

Info

Publication number
CN116505912B
CN116505912B CN202310753691.1A CN202310753691A CN116505912B CN 116505912 B CN116505912 B CN 116505912B CN 202310753691 A CN202310753691 A CN 202310753691A CN 116505912 B CN116505912 B CN 116505912B
Authority
CN
China
Prior art keywords
field effect
attenuator
source
resistor
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202310753691.1A
Other languages
Chinese (zh)
Other versions
CN116505912A (en
Inventor
吴泽
周鹏
黄华
全金海
王亚文
周阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhongke Haigao Chengdu Electronic Technology Co ltd
Original Assignee
Zhongke Haigao Chengdu Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhongke Haigao Chengdu Electronic Technology Co ltd filed Critical Zhongke Haigao Chengdu Electronic Technology Co ltd
Priority to CN202310753691.1A priority Critical patent/CN116505912B/en
Publication of CN116505912A publication Critical patent/CN116505912A/en
Application granted granted Critical
Publication of CN116505912B publication Critical patent/CN116505912B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/24—Frequency-independent attenuators
    • H03H11/245—Frequency-independent attenuators using field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/16—Networks for phase shifting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The application relates to the field of integrated circuits, in particular to an all positive control low-additional phase-shift attenuator, which comprises the following components: a 0.5dB attenuator, a 1dB attenuator, a 2dB attenuator, a 4dB attenuator, an 8dB attenuator, and a 16dB attenuator that are cascaded together; the positive power supply is respectively connected with the input end IN1, the input end IN2, the input end IN3, the input end IN4, the input end IN5 and the input end IN6 of the 0.5dB attenuator, the 1dB attenuator, the 2dB attenuator, the 4dB attenuator, the 8dB attenuator and the 16dB attenuator through a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6. The application has the effect of low additional phase shift, optimizes the performance of the attenuator, widens the use scene, has the function of realizing full positive control, and is convenient for the practical use of the field effect transistor.

Description

Full positive control low additional phase shift attenuator
Technical Field
The present application relates to the field of integrated circuits, and more particularly to an all positive control low add-on phase shift attenuator.
Background
At present, the radio frequency numerical control attenuator mainly controls the on and off of a switching transistor in the attenuator by a digital control signal, so that each bit of the numerical control attenuator can work in two working states of direct connection and attenuation, and the combination of different attenuation amounts can be realized by adjusting the digital control signal, thereby realizing the function of numerical control attenuation. As the frequency increases, the parasitic effects of the various components in the circuit, particularly the transistors, become more pronounced, causing rapid deterioration of the added phase shift of the digitally controlled attenuator. In addition, the switching transistor in the common numerical control attenuator is usually turned off when the voltage of-5V is loaded and turned on when the voltage of 0V is loaded, so that the radio frequency switch in the existing design often needs to be loaded with negative voltage to realize the on-off function, and the practical use of the chip is greatly inconvenient in consideration of specific application scenes.
Disclosure of Invention
In order to solve the technical problems of high additional dependence and negative charge in the actual use of a chip, the application provides an all positive control low additional phase shift attenuator.
The application provides an all positive control low-additional phase shift attenuator which adopts the following technical scheme:
provided is an all positive control low additional phase shift attenuator, the working frequency band is 0.5-18GHz, comprising: a 0.5dB attenuator, a 1dB attenuator, a 2dB attenuator, a 4dB attenuator, an 8dB attenuator, and a 16dB attenuator that are cascaded together; the positive power supply VDD is connected to the respective first, second, third, fourth, fifth and sixth inputs IN1, IN2, IN3, IN4, IN5 and IN6 of the 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB attenuators through first, second, third, fourth, fifth and sixth resistors R1, R2, R3, R4, R5 and R6, respectively.
Preferably, the method comprises the steps of: the 0.5dB attenuator comprises: between the first input terminal IN1 and the output terminal OUT1, connected to the ground terminal GND through an inductance L1, a field effect transistor FET1, a resistance R11, and a capacitance Cg 1;
the 1dB attenuator has the following composition: between the second input terminal IN2 and the output terminal OUT2, connected to the ground terminal GND through an inductance L2, a field effect transistor FET2, a resistance R21 and a capacitance Cg 2;
the gates of the field effect transistor FET1 and the field effect transistor FET2 are respectively connected with a digital voltage input port.
Preferably, the method comprises the steps of: the 2dB attenuator comprises: a third resistor R3 and a capacitor C1 for adjusting the phase offset of the full positive attenuator are connected IN parallel between the third input terminal IN3 and the output terminal OUT3 by the source and the drain of the field effect transistor FET 3;
the source electrode of the FET3 is connected to the ground GND through the FET31, the resistor R31 and the capacitor Cg 31;
the source electrode of the FET3 is connected to the ground GND through the FET32, the resistor R32 and the capacitor Cg 32;
the grids of the field effect tube FET3, the field effect tube FET31 and the field effect tube FET32 are respectively connected with a digital voltage input port;
the 4dB attenuator comprises: a fourth resistor R4 and a capacitor C2 for adjusting the phase offset of the full positive attenuator are connected IN parallel between the fourth input terminal IN4 and the output terminal OUT4 by the source and the drain of the field effect transistor FET 4;
the source of the FET4 is connected to the ground GND through the FET41, the resistor R41 and the capacitor Cg 41;
the source electrode of the FET4 is connected to the ground GND through the FET42, the resistor R42 and the capacitor Cg 42;
the gates of the FET4, FET41 and FET42 are respectively connected to the digital voltage input ports.
Preferably, the method comprises the steps of: the 8dB attenuator comprises: a fifth resistor R5 is connected IN parallel between the fifth input terminal IN5 and the output terminal OUT5 by the source and the drain of the FET 5;
a phasing module M1 is connected in series between the source electrode of the FET5 and the ground end GND, and a phasing module M2 is connected in series between the drain electrode of the FET5 and the ground end GND;
a field effect tube FET51, a resistor R51 and a capacitor Cg51 are also connected in series between the source of the field effect tube FET5 and the ground GND; the drain of the FET51 is connected with the source of the FET5, and the source of the FET51 is connected with one end of the resistor R51;
a field effect tube FET52, a resistor R52 and a capacitor Cg52 are also connected in series between the drain electrode of the field effect tube FET5 and the ground end GND; the drain of the FET52 is connected with the source of the FET5, and the source of the FET52 is connected with one end of the resistor R52;
the gates of the field effect transistor FET5, the field effect transistor FET51 and the field effect transistor FET52 are respectively connected with a digital voltage input port.
Preferably, the phase modulation module M1 includes: the drain of the FET53 is connected to the fifth input IN5, and the source of the FET53 is connected to the ground GND through the capacitor C51;
the phase modulation module M2 includes: the drain of the FET54 is connected to the output OUT5, and the source of the FET53 is connected to the ground GND through the capacitor C52;
the gates of the field effect transistor FET53 and the field effect transistor FET54 are respectively connected with a digital voltage input port.
Preferably, the 16dB attenuator includes: a phasing module M5 and a source electrode and a drain electrode of the field effect tube FET6 are connected IN series between the sixth input end IN6 and the output end OUT6, and a sixth resistor R6 is connected IN parallel between the source electrode and the drain electrode of the field effect tube FET 6;
a phasing module M3 is connected IN series between the source electrode of the FET6 and the ground end GND, a phasing module M4 is connected IN series between the drain electrode of the FET6 and the ground end GND, and a phasing module M5 is connected IN series between the source electrode of the FET6 and the radio frequency signal input port IN6;
a field effect tube FET61, a resistor R61 and a capacitor Cg61 are also connected in series between the source of the field effect tube FET6 and the ground GND; the drain of the FET61 is connected with the source of the FET6, and the source of the FET61 is connected with one end of the resistor R61;
a field effect tube FET62, a resistor R62 and a capacitor Cg62 are also connected in series between the drain of the field effect tube FET6 and the ground GND; the drain of the FET62 is connected to the source of the FET6, and the source of the FET62 is connected to one end of the resistor R62.
Preferably, the phase modulation module M3 includes: the drain of the FET63 is connected to the sixth input IN6, and the source of the FET63 is connected to the ground GND through the capacitor C61;
the phase modulation module M4 includes: the drain of the FET64 is connected to the output OUT6, and the source of the FET63 is connected to the ground GND through the capacitor C62;
the grids of the FET63 and the FET64 are respectively connected with a digital voltage input port;
the phase modulation module M5 includes: a field effect tube FET7 is connected IN series between the source electrode of the field effect tube FET6 and the sixth input end IN6, the source electrode of the field effect tube FET7 is connected with the sixth input end IN6, and the drain electrode of the field effect tube FET7 is connected with the source electrode of the field effect tube FET 6; an inductor L3 is connected in parallel between the source electrode and the drain electrode of the FET 7;
the source electrode of the FET7 is connected to the ground GND through the FET8 and the capacitor C81; the drain electrode of the FET8 is connected with the source electrode of the FET7, and the source electrode of the FET8 is connected with one end of the capacitor C81;
the drain electrode of the FET7 is connected to the ground GND through the FET9 and the capacitor C91; the drain of the FET9 is connected with the drain of the FET7, and the source of the FET9 is connected with one end of the capacitor C81.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the numerical control attenuator realizes the function of full positive control by improving the circuit, thereby greatly facilitating the actual use of the transistor;
2. the attenuator solves the technical problem that the additional phase shift is larger when the numerical control attenuator works at the frequency above 10GHz, so that the working frequency of the numerical control attenuator can be expanded to higher frequency;
3. lower additional phase shifts. The digital control attenuator can reduce the additional phase shift of the digital control attenuator by adjusting the size of a capacitor, an inductor and/or a field effect transistor, and the additional phase shift of the traditional digital control attenuator structure can be large at high frequency due to the influence of a parasitic capacitor Coff of a transistor;
4. lower insertion loss. In order to solve the problem of additional phase shift of a large-attenuation numerical control attenuator, a plurality of small-attenuation numerical control attenuators are usually adopted in cascade connection or a radio frequency switch is directly used for switching through and an attenuation circuit.
Drawings
FIG. 1 is a diagram of an all positive control low add-on phase shift attenuator configuration;
FIG. 2 is a diagram of a 0.5dB attenuator configuration;
fig. 3 is a first equivalent circuit diagram of a 0.5dB attenuator;
fig. 4 is a second equivalent circuit diagram of a 0.5dB attenuator;
fig. 5 is a construction diagram of a 2dB attenuator;
fig. 6 is a first equivalent circuit diagram of a 2dB attenuator;
fig. 7 is a second equivalent circuit diagram of a 2dB attenuator;
fig. 8 is a first configuration diagram of an 8dB attenuator;
fig. 9 is a first equivalent circuit diagram of an 8dB attenuator;
fig. 10 is a second equivalent circuit diagram of an 8dB attenuator;
FIG. 11 is a second construction diagram of an 8dB attenuator;
fig. 12 is a first configuration diagram of a 16dB attenuator;
fig. 13 is a first equivalent diagram of a 16dB attenuator;
fig. 14 is a second equivalent plot of a 16dB attenuator;
fig. 15 is a second configuration diagram of a 16dB attenuator.
Description of the embodiments
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to fig. 1 to 15 and the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In a first aspect, as shown in fig. 1, there is provided an all positive control low add-on phase shift attenuator with an operating frequency range of 0.5 GHz to 18GHz, comprising: a 0.5dB attenuator, a 1dB attenuator, a 2dB attenuator, a 4dB attenuator, an 8dB attenuator, and a 16dB attenuator that are cascaded together; the positive power supply VDD is connected to the respective first, second, third, fourth, fifth and sixth inputs IN1, IN2, IN3, IN4, IN5 and IN6 of the 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB attenuators through first, second, third, fourth, fifth and sixth resistors R1, R2, R3, R4, R5 and R6, respectively. The arrangement sequence of the attenuators can be adjusted according to the needs, can be sequentially cascaded according to the existing sequence, and can also be adjusted according to the actual needs. In this embodiment, the all positive control attenuator also has the function of a low additional phase shift.
Preferably, as shown in fig. 2, it includes: the 0.5dB attenuator comprises: between the first input terminal IN1 and the output terminal OUT1, connected to the ground terminal GND through an inductance L1, a field effect transistor FET1, a resistance R11, and a capacitance Cg 1; the gate of the FET1 is connected to a control voltage V5 through a resistor R12; the large resistor R12 (the size is usually about 2KΩ) is an isolation resistor, which can prevent the radio frequency signal from leaking to the grid of the FET 1; the resistor R11 controls the attenuation of the 0.5dB attenuator;
when the control voltage V5 is 0V, the FET1 is turned off, the radio frequency signal does not pass through the attenuation resistor R11, and does not attenuate, and is in the ground state, and the equivalent circuit of the attenuator is shown in fig. 3, where Cds is the source-drain parasitic capacitance of the FET 1. When the control voltage V5 is 5V, the FET1 is turned on, and the radio frequency signal is attenuated by the attenuation resistor R11, and is in an attenuated state, and the equivalent circuit of the attenuator is shown in fig. 4, where Rds is the source-drain parasitic resistor of the FET 1. Compared with the traditional negative pressure control attenuator structure, each stage of the attenuator is connected with a capacitor Cg1 in series at the ground end GND of the field effect tube for realizing the attenuation function, and the input end of a radio frequency signal is connected with control voltage through a large resistor, at the moment, the source voltage of the field effect tube FET1 is raised to 0v, the drain voltage is raised to +5v, a potential difference is formed between the drain and the source of the field effect tube FET1, and the field effect tube FET1 is conducted to realize the full positive control of the attenuator.
The 0.5dB attenuator is characterized in that the influence of the parasitic capacitance Cds of the field effect transistor on the additional phase shift of the 0.5dB attenuator is reduced by connecting the inductance L1 in series with the parasitic capacitance Cds of the field effect transistor, and the additional phase shift of the 0.5dB attenuator can be adjusted by adjusting the magnitude of the inductance L1. The smaller the inductance L1, the smaller the phase difference between the ground state and the attenuation state of the 0.5dB attenuator, and the smaller the additional phase shift of the 0.5dB attenuator, but at the same time, the smaller the inductance L1 will decrease the attenuation amount of the 0.5dB attenuator, and even at low frequencies, the 0.5dB attenuator will not work properly. Therefore, the magnitude of the inductance L1 needs to be adjusted according to a plurality of performance indexes such as the working frequency, the bandwidth, the attenuation precision, the additional phase shift and the like of the 0.5dB attenuator.
The 1dB attenuator has the following composition: between the second input terminal IN2 and the output terminal OUT2, connected to the ground terminal GND through an inductance L2, a field effect transistor FET2, a resistance R21 and a capacitance Cg 2; the structure of the 1dB attenuator is identical to that of the 0.5dB attenuator. The 1dB attenuator may be constructed with reference to the 0.5dB attenuator of fig. 2; each of the components in fig. 2 is equally applicable to a 1dB attenuator. Each of the components in fig. 3, 4 is equally applicable to a 1dB attenuator.
The gates of the field effect transistor FET1 and the field effect transistor FET2 are respectively connected with a digital voltage input port.
Preferably, as shown in fig. 5, it includes: the 2dB attenuator comprises: a third resistor R3 and a capacitor C1 for adjusting the phase offset of the full positive attenuator are connected IN parallel between the third input terminal IN3 and the output terminal OUT3 by the source and the drain of the field effect transistor FET 3;
similar to the 0.5dB and 1dB principle described above, the conventional pi-type attenuator is based on an improvement, as shown IN fig. 5, IN3 represents the input terminal, OUT3 represents the output terminal, A, B represents the digital control voltage input port, and the conventional pi-type attenuator is based on an improvement. The same as the above 0.5dB is 1dB, a capacitor Cg31, cg32 is respectively connected in series to the ground GND of the FET31 and FET32 for attenuation, and a control voltage is terminated at the input end of the rf signal through a large resistor, so that the source voltages of the FET31, FET32 are raised to 0v, the drain voltages are raised to +5v, a potential difference is formed between the drains and sources of the FET31, FET32, and the FET is turned on to realize full positive control of the attenuator. The source of FET31 is connected to ground GND through resistor R31 and capacitor Cg 31; the source of FET32 is connected to ground GND through resistor R32 and capacitor Cg 32; the third resistors R3, R31 and R32 form a pi-type attenuation network, and the resistance value is 3-300 omega. Besides, a capacitor C1 is connected in parallel between the drain and the source of the FET3 field effect transistor for adjusting the phase shift of the 2dB attenuator.
When the control voltage input end A is connected with 0V direct current voltage and the control voltage input end B is connected with 5V direct current voltage, the field effect transistor FET3 is in a conducting state, the field effect transistor FET31 and the transistor FET32 are in a cutting-off state, and at the moment, the numerical control attenuator presents a straight-through state and an equivalent circuit diagram is shown in fig. 6. Because of the large size of the FET3, the on-state parasitic resistor Ron3 has a small resistance, typically within 2Ω, which is much smaller than the resistance of the third resistor R3. The sizes of the FET31 and the FET32 are small, and at this time, the capacitance values of the parasitic capacitances Coff2 and Coff4 of the FET are small, which are generally much smaller than 0.05pF, and the digitally controlled attenuator presents a pass-through state with low insertion loss due to the small resistance value of the parasitic resistor Ron3 of the FET 3.
When the control voltage input end A is connected with 5V direct current voltage and the control voltage input end B is connected with 0V direct current voltage, the field effect tube FET3 is in an off state, the field effect tube FET31 and the field effect tube FET32 are in an on state, and at the moment, the numerical control attenuator is in an attenuation state, and an equivalent circuit diagram is shown in fig. 7. Due to the large size of FET3, the parasitic capacitance Coff3 in the off state is large, typically greater than 0.15pF, which introduces a relatively large phase shift to the digitally controlled attenuator attenuation state, causing degradation of the additional phase shift. The FET31 and the FET32 have smaller sizes, and the parasitic resistance Ron2 and the resistance Ron4 in the on state have larger resistance values, wherein the parasitic resistance Ron2 and the resistance Ron4 are respectively connected with the resistor R31 and the resistor R32 in series and form a pi-type attenuation network of the numerical control attenuator together with the first resistor R1; the capacitor C1 is connected in parallel with the third resistor R3 to form an RC parallel network for modulating the phase of the attenuation state of the digital control attenuator, so that the phase offset caused by the parasitic capacitance Coff3 of the FET3 is reduced, and the additional phase shift of the digital control attenuator is reduced.
The source electrode of the FET3 is connected to the ground GND through the FET31, the resistor R31 and the capacitor Cg 31;
the source electrode of the FET3 is connected to the ground GND through the FET32, the resistor R32 and the capacitor Cg 32;
the grids of the FET3, FET31 and FET32 are respectively connected with a digital voltage input port A, B; A. the digital control signals of the terminals B are complementary, namely, when the positive voltage signals are input to the terminal A, the voltage signals of 0 are input to the terminal B.
The 4dB attenuator comprises: a fourth resistor R4 and a capacitor C2 for adjusting the phase offset of the full positive attenuator are connected IN parallel between the fourth input terminal IN4 and the output terminal OUT4 by the source and the drain of the field effect transistor FET 4;
the source of the FET4 is connected to the ground GND through the FET41, the resistor R41 and the capacitor Cg 41;
the source electrode of the FET4 is connected to the ground GND through the FET42, the resistor R42 and the capacitor Cg 42;
the gates of the FET4, FET41 and FET42 are respectively connected to the digital voltage input ports. The structure and the working principle of the 4dB attenuator are the same as those of the 2dB attenuator, and are not repeated here. The construction of the 4dB attenuator may be referred to the construction diagram of the 2dB attenuator of fig. 5; each of the components in fig. 5 is equally applicable to a 4dB attenuator. Each of the components in fig. 6, 7 is equally applicable to a 4dB attenuator.
Preferably, as shown in fig. 8, it includes: the 8dB attenuator comprises: a fifth resistor R5 is connected IN parallel between the fifth input terminal IN5 and the output terminal OUT5 by the source and the drain of the FET 5;
a phasing module M1 is connected in series between the source electrode of the FET5 and the ground end GND, and a phasing module M2 is connected in series between the drain electrode of the FET5 and the ground end GND;
a field effect tube FET51, a resistor R51 and a capacitor Cg51 are also connected in series between the source of the field effect tube FET5 and the ground GND; the drain of the FET51 is connected with the source of the FET5, and the source of the FET51 is connected with one end of the resistor R51; the source of the FET51 is connected to the ground GND through a resistor R51 and a capacitor Cg51;
a field effect tube FET52, a resistor R52 and a capacitor Cg52 are also connected in series between the drain electrode of the field effect tube FET5 and the ground end GND; the drain of the FET52 is connected with the source of the FET5, and the source of the FET52 is connected with one end of the resistor R52; the source of FET52 is connected to ground GND through resistor R52 and capacitor Cg52;
the FET5 is a series FET of the numerical control attenuation network, the FET51 and the FET52 are parallel FETs of the numerical control attenuation network, and the phase modulation modules M1 and M2 mainly play a role in adjusting additional phase shift.
The structure of the two attenuators is the same as that of the two attenuators, the 8dB attenuators are also connected with a capacitor Cg51 and a capacitor Cg52 in series at the grounding end GND of the field effect tube FET51 and the grounding end GND of the FET52 respectively, and the input end of a radio frequency signal is connected with a control voltage through a large resistor, so that the source voltage of the field effect tube is raised to 0v, the drain voltage is raised to +5v, a potential difference is formed between the drain and the source of the field effect tube, and the field effect tube is conducted to realize the full positive control of the attenuators.
When the control voltage input end A is connected with 0V direct current voltage and the control voltage input end B is connected with 5V direct current voltage, the field effect transistor FET5 is in a conducting state, the transistor FET51 and the transistor FET52 are in a cutting-off state, and at the moment, the numerical control attenuator presents a straight-through state and an equivalent circuit diagram is shown in fig. 9. Because of the large size of FET5, the on-state parasitic resistance Ron5 is small, typically within 2Ω, which is much smaller than the fifth resistor R5. The FET51 and FET52 are small in size, and the parasitic capacitances Coff1 and Coff2 of the FETs are small, which is generally much smaller than 0.05pF. At this time, the numerical control attenuator exhibits a pass-through state of low insertion loss because the parasitic resistance Ron5 of the FET5 is small.
When the control voltage input end A is connected with 5V direct current voltage and the control voltage input end B is connected with 0V direct current voltage, the field effect transistor FET5 is in an off state, the transistor FET51 and the transistor FET52 are in an on state, and at the moment, the numerical control attenuator presents an attenuation state, and an equivalent circuit diagram is shown in fig. 10. Due to the large size of FET5, the parasitic capacitance Coff5 in the off state is large, typically greater than 0.15pF, which introduces a relatively large phase shift to the digitally controlled attenuator attenuation state, causing degradation of the additional phase shift. The field effect transistors FET51, FET52, FET53 and FET54 have smaller sizes, and the parasitic resistances Ron1, ron2, ron4 and Ron5 in the on state have larger resistance values, wherein the parasitic resistances Ron2 and Ron4 are respectively connected with the resistor R51 and the resistor R52 in series, and form a pi-type attenuation network of the numerical control attenuator together with the fifth resistor R5 connected in parallel; parasitic resistors Ron1 and Ron5 are respectively connected with a capacitor C1 and a resistor C2 in series to form an RC series circuit to modulate the phase of the attenuation state of the digital attenuator, so that the phase offset caused by parasitic capacitor Coff5 of FET5 is reduced, and the additional phase shift of the digital attenuator is reduced.
The gates of the field effect transistor FET5, the field effect transistor FET51 and the field effect transistor FET52 are respectively connected with a digital voltage input port.
Preferably, as shown in fig. 8 and 11, the phase modulation module M1 includes: the drain of the FET53 is connected to the fifth input IN5, and the source of the FET53 is connected to the ground GND through the capacitor C51;
the phase modulation module M2 includes: the drain of the FET54 is connected to the output OUT5, and the source of the FET53 is connected to the ground GND through the capacitor C52; in this embodiment, the biggest characteristic is that the phase of the attenuation state of the digital attenuator is modulated by introducing the FET53, FET54, C1 and C2 without affecting the insertion loss of the on state of the digital attenuator, so as to reduce the phase shift of the attenuation state of the digital attenuator, thereby reducing the additional phase shift of the digital attenuator at high frequency and improving the high frequency bandwidth of the digital attenuator. The source of the FET53 is connected to the ground GND; the source of FET54 is connected to ground GND;
the gates of the field effect transistor FET53 and the field effect transistor FET54 are respectively connected with a digital voltage input port.
Preferably, as shown in fig. 12, the 16dB attenuator includes: a phasing module M5 and a source electrode and a drain electrode of the field effect tube FET6 are connected IN series between the sixth input end IN6 and the output end OUT6, and a sixth resistor R6 is connected IN parallel between the source electrode and the drain electrode of the field effect tube FET 6;
a phasing module M3 is connected IN series between the source electrode of the FET6 and the ground end GND, a phasing module M4 is connected IN series between the drain electrode of the FET6 and the ground end GND, and a phasing module M5 is connected IN series between the source electrode of the FET6 and the radio frequency signal input port IN6;
a field effect tube FET61, a resistor R61 and a capacitor Cg61 are also connected in series between the source of the field effect tube FET6 and the ground GND; the drain of the FET61 is connected with the source of the FET6, and the source of the FET61 is connected with one end of the resistor R61;
a field effect tube FET62, a resistor R62 and a capacitor Cg62 are also connected in series between the drain of the field effect tube FET6 and the ground GND; the drain of the FET62 is connected to the source of the FET6, and the source of the FET62 is connected to one end of the resistor R62.
As shown in fig. 12, the structure of the right part is identical to the structure and circuit function of the 8dB attenuator, and a capacitor Cg61, cg62 is connected in series to the ground GND of the FET61 and FET62, respectively, and the control voltage is terminated at the input end of the rf signal by a large resistor, so that the source voltage of the FET is raised to 0v, the drain voltage is raised to +5v, a potential difference is formed between the drain and source of the FET, and the FET is turned on, so as to realize the full positive control of the attenuator.
When the control voltage input end A is connected with 0V direct current voltage and the control voltage input end B is connected with 5V direct current voltage, the field effect transistor FET7, the FET6 are in a conducting state, the field effect transistors FET71, the FET72, the FET61 and the FET62 are in a closing state, and at the moment, the numerical control attenuator presents a straight-through state with low insertion loss, and an equivalent circuit is shown in fig. 13. When the control voltage input end A is connected with 5V direct current voltage and the control voltage input end B is connected with 0V direct current voltage, the field effect transistor FET7 and the FET6 are in an off state, the field effect transistor FET71, the FET72, the FET61 and the FET62 are in an on state, the equivalent circuit is shown in figure 14, at the moment, the field effect transistor FET6 is still the same as the attenuation state of the 8dB attenuator, a larger parasitic capacitance is generated, the phase shift is caused, at the moment, the field effect transistor FET63, the field effect transistor FET64, the field effect transistor FET61 and the field effect transistor FET62 are smaller in size, the parasitic resistance Ron1, the resistance Ron2, the resistance Ron4 and the resistance Ron4 in the on state are larger, and the parasitic resistance Ron2 and the resistance Ron4 are respectively connected with the third resistance R3 and the resistance R7 in series, and form a pi-type attenuation network of the numerical control attenuator together with the fifth resistance R5; parasitic resistors Ron1 and Ron5 are respectively connected with a capacitor C1 and a resistor C2 in series to form an RC series circuit to modulate the phase of the attenuation state of the digital attenuator, so that the phase offset caused by parasitic capacitor Coff6 of FET6 is reduced, and the additional phase shift of the digital attenuator is reduced. The FET7 is in a large parasitic capacitance Coff7 in a closed state, a parallel LC loop is formed by the FET7 and an inductor L3 between the drain electrode and the source stage of the FET, the FET71 and the FET72 are small in size, the parasitic resistances Ron8 and Ron9 in the conducting state are large in resistance, and are respectively connected with the C3 and the C4 in series at the moment to form an RC series network, the function of modulating the attenuation state phase of the digital attenuator is also achieved, the phase offset caused by the parasitic capacitance Coff6 of the FET6 is reduced, and the additional phase shift of the digital attenuator is reduced.
Preferably, as shown in fig. 12 and 15, the phase modulation module M3 includes: the drain of the FET63 is connected to the sixth input IN6, and the source of the FET63 is connected to the ground GND through the capacitor C61;
the phase modulation module M4 includes: the drain of the FET64 is connected to the output OUT6, and the source of the FET63 is connected to the ground GND through the capacitor C62;
the grids of the FET63 and the FET64 are respectively connected with a digital voltage input port; the source of FET63 is connected to ground GND; the source of FET64 is connected to ground GND;
the phase modulation module M5 includes: a field effect tube FET7 is connected IN series between the source electrode of the field effect tube FET6 and the sixth input end IN6, the source electrode of the field effect tube FET7 is connected with the sixth input end IN6, and the drain electrode of the field effect tube FET7 is connected with the source electrode of the field effect tube FET 6; an inductor L3 is connected in parallel between the source electrode and the drain electrode of the FET 7;
the source electrode of the FET7 is connected to the ground GND through the FET8 and the capacitor C81; the drain electrode of the FET8 is connected with the source electrode of the FET7, and the source electrode of the FET8 is connected with one end of the capacitor C81;
the drain electrode of the FET7 is connected to the ground GND through the FET9 and the capacitor C91; the drain of the FET9 is connected with the drain of the FET7, and the source of the FET9 is connected with one end of the capacitor C81.
The phase of the attenuation state of the numerical control attenuator is modulated on the premise of not influencing the insertion loss of the conduction state of the numerical control attenuator, so that the phase deviation of the attenuation state of the numerical control attenuator is reduced, the additional phase shift of the numerical control attenuator at a high frequency is reduced, and the high frequency bandwidth of the numerical control attenuator is improved.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the numerical control attenuator realizes the function of full positive control by improving the circuit, thereby greatly facilitating the actual use of the transistor;
2. the attenuator solves the technical problem that the additional phase shift is larger when the numerical control attenuator works at the frequency above 10GHz, so that the working frequency of the numerical control attenuator can be expanded to higher frequency;
3. lower additional phase shifts. The digital control attenuator can reduce the additional phase shift of the digital control attenuator by adjusting the size of the capacitance field effect transistor, and the additional phase shift of the traditional digital control attenuator structure at high frequency can be large due to the influence of the parasitic capacitance Coff of the transistor;
4. lower insertion loss. In order to solve the problem of additional phase shift of a large-attenuation numerical control attenuator, a plurality of small-attenuation numerical control attenuators are usually adopted in cascade connection or a radio frequency switch is directly used for switching through and an attenuation circuit.
The foregoing description of the preferred embodiments of the application is not intended to limit the scope of the application in any way, including the abstract and drawings, in which case any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.

Claims (1)

1. An all positive control low add-on phase shift attenuator characterized by an operating frequency range of 0.5 GHz to 18GHz comprising: a 0.5dB attenuator, a 1dB attenuator, a 2dB attenuator, a 4dB attenuator, an 8dB attenuator, and a 16dB attenuator that are cascaded together; the positive power supply VDD is connected to the first, second, third, fourth, fifth and sixth input terminals IN1, IN2, IN3, IN4, IN5 and IN6 of the 0.5dB, 1dB, 2dB, 4dB, 8dB and 16dB attenuators through the first, second, third, fourth, fifth and sixth resistors R1, R2, R3, R4, R5 and R6, respectively; the 0.5dB attenuator comprises: between the first input terminal IN1 and the output terminal OUT1, connected to the ground terminal GND through an inductance L1, a field effect transistor FET1, a resistance R11, and a capacitance Cg 1;
the 1dB attenuator comprises: between the second input terminal IN2 and the output terminal OUT2, connected to the ground terminal GND through an inductance L2, a field effect transistor FET2, a resistance R21 and a capacitance Cg 2;
the grid electrodes of the field effect transistor FET1 and the field effect transistor FET2 are respectively connected with a digital voltage input port;
the 2dB attenuator comprises: a third resistor R3 and a capacitor C1 for adjusting the phase offset of the full positive attenuator are connected IN parallel between the third input terminal IN3 and the output terminal OUT3 by the source and the drain of the field effect transistor FET 3;
the source electrode of the FET3 is connected to the ground GND through the FET31, the resistor R31 and the capacitor Cg 31;
the source electrode of the FET3 is connected to the ground GND through the FET32, the resistor R32 and the capacitor Cg 32;
the grids of the field effect tube FET3, the field effect tube FET31 and the field effect tube FET32 are respectively connected with a digital voltage input port;
the 4dB attenuator comprises: a fourth resistor R4 and a capacitor C2 for adjusting the phase offset of the full positive attenuator are connected IN parallel between the fourth input terminal IN4 and the output terminal OUT4 by the source and the drain of the field effect transistor FET 4;
the source of the FET4 is connected to the ground GND through the FET41, the resistor R41 and the capacitor Cg 41;
the source electrode of the FET4 is connected to the ground GND through the FET42, the resistor R42 and the capacitor Cg 42;
the grids of the field effect tube FET4, the field effect tube FET41 and the field effect tube FET42 are respectively connected with a digital voltage input port;
the 8dB attenuator comprises: a fifth resistor R5 is connected IN parallel between the fifth input terminal IN5 and the output terminal OUT5 by the source and the drain of the FET 5;
a phasing module M1 is connected in series between the source electrode of the FET5 and the ground end GND, and a phasing module M2 is connected in series between the drain electrode of the FET5 and the ground end GND;
a field effect tube FET51, a resistor R51 and a capacitor Cg51 are also connected in series between the source of the field effect tube FET5 and the ground GND; the drain of the FET51 is connected with the source of the FET5, and the source of the FET51 is connected with one end of the resistor R51;
a field effect tube FET52, a resistor R52 and a capacitor Cg52 are also connected in series between the drain electrode of the field effect tube FET5 and the ground end GND; the drain of the FET52 is connected with the source of the FET5, and the source of the FET52 is connected with one end of the resistor R52;
the gates of the field effect transistor FET5, the field effect transistor FET51 and the field effect transistor FET52 are respectively connected with a digital voltage input port;
the phase modulation module M1 includes: the drain of the FET53 is connected to the fifth input IN5, and the source of the FET53 is connected to the ground GND through the capacitor C51;
the phase modulation module M2 includes: the drain of the FET54 is connected to the output OUT5, and the source of the FET53 is connected to the ground GND through the capacitor C52;
the grids of the FET53 and the FET54 are respectively connected with a digital voltage input port;
the 16dB attenuator comprises: a phasing module M5 and a source electrode and a drain electrode of the field effect tube FET6 are connected IN series between the sixth input end IN6 and the output end OUT6, and a sixth resistor R6 is connected IN parallel between the source electrode and the drain electrode of the field effect tube FET 6;
a phasing module M3 is connected IN series between the source electrode of the FET6 and the ground end GND, a phasing module M4 is connected IN series between the drain electrode of the FET6 and the ground end GND, and a phasing module M5 is connected IN series between the source electrode of the FET6 and the radio frequency signal input port IN6;
a field effect tube FET61, a resistor R61 and a capacitor Cg61 are also connected in series between the source of the field effect tube FET6 and the ground GND; the drain of the FET61 is connected with the source of the FET6, and the source of the FET61 is connected with one end of the resistor R61;
a field effect tube FET62, a resistor R62 and a capacitor Cg62 are also connected in series between the drain of the field effect tube FET6 and the ground GND; the drain of the FET62 is connected with the source of the FET6, and the source of the FET62 is connected with one end of the resistor R62;
the phase modulation module M3 includes: the drain of FET63 is connected to the source of FET6, and the source of FET63 is connected to ground GND through capacitor C61;
the phase modulation module M4 includes: the drain of the FET64 is connected to the output OUT6, and the source of the FET64 is connected to the ground GND through the capacitor C62;
the grids of the FET63 and the FET64 are respectively connected with a digital voltage input port;
the phase modulation module M5 includes: a field effect tube FET7 is connected IN series between the source electrode of the field effect tube FET6 and the sixth input end IN6, the source electrode of the field effect tube FET7 is connected with the sixth input end IN6, and the drain electrode of the field effect tube FET7 is connected with the source electrode of the field effect tube FET 6; an inductor L3 is connected in parallel between the source electrode and the drain electrode of the FET 7;
the source electrode of the FET7 is connected to the ground GND through the FET8 and the capacitor C81; the drain electrode of the FET8 is connected with the source electrode of the FET7, and the source electrode of the FET8 is connected with one end of the capacitor C81;
the drain electrode of the FET7 is connected to the ground GND through the FET9 and the capacitor C91; the drain of the FET9 is connected with the drain of the FET7, and the source of the FET9 is connected with one end of the capacitor C81.
CN202310753691.1A 2023-06-26 2023-06-26 Full positive control low additional phase shift attenuator Active CN116505912B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310753691.1A CN116505912B (en) 2023-06-26 2023-06-26 Full positive control low additional phase shift attenuator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310753691.1A CN116505912B (en) 2023-06-26 2023-06-26 Full positive control low additional phase shift attenuator

Publications (2)

Publication Number Publication Date
CN116505912A CN116505912A (en) 2023-07-28
CN116505912B true CN116505912B (en) 2023-09-19

Family

ID=87325150

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310753691.1A Active CN116505912B (en) 2023-06-26 2023-06-26 Full positive control low additional phase shift attenuator

Country Status (1)

Country Link
CN (1) CN116505912B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448207A (en) * 1993-09-30 1995-09-05 Sony Corporation Attenuator circuit apparatus
CN103427781A (en) * 2013-08-31 2013-12-04 西安电子科技大学 Silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator
CN206835057U (en) * 2017-06-07 2018-01-02 成都振芯科技股份有限公司 A kind of numerical-control attenuator
CN110855266A (en) * 2019-11-27 2020-02-28 西安博瑞集信电子科技有限公司 Single-voltage positive-voltage driven single-chip numerical control attenuator chip
CN111988014A (en) * 2020-09-02 2020-11-24 成都芯川电子有限公司 Low phase shift broadband numerical control attenuator applied to microwave and millimeter waves
WO2021196404A1 (en) * 2020-03-30 2021-10-07 南京汇君半导体科技有限公司 Low phase deviation digital-controlled radio frequency attenuator
CN115242217A (en) * 2022-08-25 2022-10-25 无锡华睿芯微电子科技有限公司 Ultra-wideband temperature compensation voltage-controlled attenuator chip based on FET switch tube core

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448207A (en) * 1993-09-30 1995-09-05 Sony Corporation Attenuator circuit apparatus
CN103427781A (en) * 2013-08-31 2013-12-04 西安电子科技大学 Silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator
CN206835057U (en) * 2017-06-07 2018-01-02 成都振芯科技股份有限公司 A kind of numerical-control attenuator
CN110855266A (en) * 2019-11-27 2020-02-28 西安博瑞集信电子科技有限公司 Single-voltage positive-voltage driven single-chip numerical control attenuator chip
WO2021196404A1 (en) * 2020-03-30 2021-10-07 南京汇君半导体科技有限公司 Low phase deviation digital-controlled radio frequency attenuator
CN111988014A (en) * 2020-09-02 2020-11-24 成都芯川电子有限公司 Low phase shift broadband numerical control attenuator applied to microwave and millimeter waves
CN115242217A (en) * 2022-08-25 2022-10-25 无锡华睿芯微电子科技有限公司 Ultra-wideband temperature compensation voltage-controlled attenuator chip based on FET switch tube core

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
一种正电控制低温漂单片数控衰减器;韩玉鹏;赵国庆;赵瑞华;王凯;甄建宇;;半导体技术(第01期);58-62 *
超低附加相移0.5GHz～18GHz六位数控衰减芯片设计;刘云刚 等;《电子信息对抗技术》;第28卷(第3期);72-76 *

Also Published As

Publication number Publication date
CN116505912A (en) 2023-07-28

Similar Documents

Publication Publication Date Title
KR100317657B1 (en) Attenuator circuit
JP3425235B2 (en) Variable attenuator
US7817966B2 (en) Switching device with reduced intermodulation distortion
CN111988014B (en) Low phase shift broadband digital control attenuator applied to microwave and millimeter wave
WO2001067602A2 (en) Electronic switch
CN103427781A (en) Silicone substrate high-linearity low-phase-shift ultra-broad-band digital attenuator
US7123116B2 (en) Phase shifter and multibit phase shifter
CN113114162A (en) Attenuator circuit for CMOS broadband amplitude-phase multifunctional chip
CN113300682B (en) Reconfigurable amplitude limiting and attenuation integrated circuit and working method thereof
CA2132356A1 (en) Digital microwave multi-bit attenuator
CN116505912B (en) Full positive control low additional phase shift attenuator
Doddamani et al. Design of SPDT switch, 6 bit digital attenuator, 6 Bit digital phase shifter for L-Band T/R module using 0.7 μm GaAs MMIC technology
CN115242217B (en) Ultra-wideband temperature compensation pressure control attenuator chip based on FET switch tube core
US20100171541A1 (en) Constant phase digital attenuator with on-chip matching circuitry
CN113437948B (en) Switch type low-additional phase-shift digital step attenuator of all NMOS transistor
CN115333503A (en) Digital attenuator
WO2022088445A1 (en) Coupling-type single-pole double-throw switch applied to radio frequency integrated circuit
US11677392B2 (en) Bias networks for DC or extended low frequency capable fast stacked switches
CN115225073A (en) Novel double-mode change-over switch
CN112491438A (en) Radio frequency front end integrated chip
CN112468130B (en) Transformer type single-pole double-throw switch and radio frequency integrated circuit
JP3446631B2 (en) Variable attenuator and mobile communication device
US20240098906A1 (en) A circuit
CN217010827U (en) Numerical control attenuation structure with high power capacity and high linearity and attenuator
CN113300694B (en) Ultra-wideband low-loss high-isolation radio frequency switch with fully differential structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant