JPS63311767A - Semiconductor nonvolatile memory - Google Patents

Semiconductor nonvolatile memory

Info

Publication number
JPS63311767A
JPS63311767A JP14824987A JP14824987A JPS63311767A JP S63311767 A JPS63311767 A JP S63311767A JP 14824987 A JP14824987 A JP 14824987A JP 14824987 A JP14824987 A JP 14824987A JP S63311767 A JPS63311767 A JP S63311767A
Authority
JP
Japan
Prior art keywords
insulating film
gate electrode
interlayer insulating
floating gate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14824987A
Other languages
Japanese (ja)
Inventor
Yukihiro Imura
行宏 井村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP14824987A priority Critical patent/JPS63311767A/en
Publication of JPS63311767A publication Critical patent/JPS63311767A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve reliability by a method wherein an insulating film, where the highest voltage is applied and all the trap is charged up, such as an oxide film or the like is used as an interlaminar insulating film between a floating-gate electrode, a control gate and a selection gate. CONSTITUTION:A control gate electrode 7 is provided on an interlaminar insulating film 6 and the potential of a floating-gate 5 is controlled through the capacitance coupling. The interlaminar insulating film 6, which is applied with a bias once, is formed in such a manner that the voltage highest within the extent of voltage which does not break down the interlaminar insulating film 6, is applied to the control gate electrode 7 for tens of msec to a few seconds as a p-type conductor substrate 1, a source region 2, and a drain region 3 are kept at a ground level after the control gate electrode 7, other electrodes, and others are wired. Therefore, the insulating film 6 is improved in an insulating property and the ratio of ions once injected into the stray gate electrode 5 to those volatiled through the interlaminar insulating film 6 can be reduced. By these processes, the semiconductor nonvolatile memory can be improved in reliability.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、EFROM−E” FROMなどの半導体
不揮発性メモリに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor non-volatile memories such as EFROM-E'' FROM.

〔発明の概要〕[Summary of the invention]

この発明は、浮遊ゲート構造を有するEPROM−E”
 PROMなどの半導体不揮発性メモリにおいて、浮遊
ゲート電極の周囲の層間絶縁膜に、通常の動作時に加わ
る電圧よりも高い電圧を1度加えて、層間絶縁膜中の電
子や正孔のトラップをチャージアップし、層間絶縁膜を
流れる電流を少なくすることにより、浮遊ゲート電極か
らの電子の揮発を少なくし、半導体不揮発性メモリの信
顛性を高めるようにしたものである。
This invention is an EPROM-E" having a floating gate structure.
In semiconductor nonvolatile memories such as PROM, a voltage higher than the voltage applied during normal operation is applied once to the interlayer insulating film surrounding the floating gate electrode to charge up the traps of electrons and holes in the interlayer insulating film. However, by reducing the current flowing through the interlayer insulating film, the volatilization of electrons from the floating gate electrode is reduced, thereby increasing the reliability of the semiconductor nonvolatile memory.

〔従来の技術〕[Conventional technology]

従来の半導体不揮発性メモリの断面図を第2図に示す。 FIG. 2 shows a cross-sectional view of a conventional semiconductor nonvolatile memory.

P型半導体基板1の表面にN型のソース領域2とドレイ
ン領域3.及び基板を熱酸化して形成するゲート絶縁膜
4を設け、ゲート絶縁膜4の上には通常リン等の不純物
を含むポリシリコンよりなる浮遊ゲート電極5を形成す
る。さらに、浮遊ゲート電極5の表面を熱酸化して層間
絶縁膜16を形成し、この上に制御ゲート電極7を設け
である。層間絶縁膜16にはCVD (化学的気相成長
)法により形成される二酸化シリコン膜も用いられこの
半導体不揮発性メモリの動作は浮遊ゲート電極5内の電
荷によって決定される。浮遊ゲート電極5内に電子が多
数ある時は、制御ゲート電極7から見たしきい値は高く
なり、反対に浮遊ゲート電極5内に電子がほとんど無い
時は、制御ゲート電極7から見たしきい値は低くなる。
An N-type source region 2 and an N-type drain region 3 are formed on the surface of a P-type semiconductor substrate 1. A gate insulating film 4 is formed by thermally oxidizing the substrate, and a floating gate electrode 5 usually made of polysilicon containing impurities such as phosphorus is formed on the gate insulating film 4. Furthermore, the surface of the floating gate electrode 5 is thermally oxidized to form an interlayer insulating film 16, and the control gate electrode 7 is provided thereon. A silicon dioxide film formed by CVD (chemical vapor deposition) is also used as the interlayer insulating film 16, and the operation of this semiconductor nonvolatile memory is determined by the charge in the floating gate electrode 5. When there are many electrons in the floating gate electrode 5, the threshold value as seen from the control gate electrode 7 becomes high, and on the other hand, when there are few electrons in the floating gate electrode 5, the threshold value as seen from the control gate electrode 7 becomes high. The threshold will be lower.

この2つの状態のうちのいずれか一方を電源が切れてい
る時でも保持することで半導体不揮発性メモリとしての
機能を果たしている。
By maintaining one of these two states even when the power is turned off, it functions as a semiconductor nonvolatile memory.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

半導体不揮発性メモリが長期間にわたって前記2つの状
態のうちの一方を保持する即ち、浮遊ゲート電極5内に
電子を長期間保持するために、層間絶縁膜16には高い
絶縁性が要求される。しかし、眉間wA緑膜16には、
通常リンなどの不純物を多量に含むポリシリコンを熱酸
化して形成される酸化膜が用いられるので単結晶シリコ
ン上の熱酸化膜に比べてトラップ等の欠陥が生じやすく
、良好な特性の酸化膜を得るために、1000〜110
0℃の高温な雰囲気中で酸化を行っていた。一方、半導
体集積回路の高集積化に伴い、半導体製造プロセスの低
温化が必須の条件となってきた。しかし、850〜95
0℃程度の温度で形成したポリシリコン上の酸化膜は、
十分な絶縁耐圧を存していない。第3図に異なる温度で
形成したポリシリコン上の酸化膜の電流密度と酸化膜に
かかる電界強度との関係を示す、酸化温度が下がるにつ
れて電流密度−電界強度の曲線は左にシフトし、同じ電
界強度に対して電流は多くなる。
In order for the semiconductor nonvolatile memory to maintain one of the two states for a long period of time, that is, to maintain electrons in the floating gate electrode 5 for a long period of time, the interlayer insulating film 16 is required to have high insulation properties. However, in the glabellar wA green membrane 16,
Usually, an oxide film formed by thermally oxidizing polysilicon containing a large amount of impurities such as phosphorus is used, so it is more prone to defects such as traps than a thermal oxide film on single crystal silicon, and has good characteristics. 1000-110 to get
Oxidation was carried out in a high temperature atmosphere of 0°C. On the other hand, as semiconductor integrated circuits become more highly integrated, lowering the temperature of the semiconductor manufacturing process has become an essential condition. However, 850-95
The oxide film on polysilicon formed at a temperature of about 0°C is
Does not have sufficient dielectric strength. Figure 3 shows the relationship between current density and electric field strength applied to the oxide film on polysilicon formed at different temperatures.As the oxidation temperature decreases, the current density-field strength curve shifts to the left and remains the same. The current increases relative to the electric field strength.

即ち、酸化温度の低はど酸化膜の膜質が悪くなり、半導
体不揮発性メモリの信鎖性を低下させる。
That is, the lower the oxidation temperature, the worse the film quality of the oxide film, which lowers the reliability of the semiconductor nonvolatile memory.

また、半導体集積回路の高集積化では、各素子の平面的
な大きさの縮小だけでなく厚み方向の縮小も要求される
。従って、電源電圧が一定(例えば5V)であれば、絶
8!膜にかかる電界強度は膜厚に反比例して増していく
ことになる。即ち、従来の要求を満たしてきた絶縁膜も
、高集積化に伴う要求には対処できなくなる可能性が大
きいと言える。
Further, in order to increase the degree of integration of semiconductor integrated circuits, it is required not only to reduce the planar size of each element but also to reduce the thickness thereof. Therefore, if the power supply voltage is constant (for example, 5V), it is absolutely 8! The electric field strength applied to the film increases in inverse proportion to the film thickness. That is, it can be said that there is a strong possibility that an insulating film that has met conventional requirements will no longer be able to meet the requirements associated with higher integration.

上記の例の他、層間絶縁膜16にCVD法により形成さ
れる二酸化シリコン膜を用いることも可能である。特に
ジクロルシランと亜酸化窒素とから5iHzc l z
 + 2NgO→5iOz + 2Hc j! +2N
zなる反応を利用して、800〜950℃で形成される
CVD二酸化シリコン膜は、ポリシリコン上に堆積され
ても優れた絶縁性を示す。しかし、CVD二酸化シリコ
ン膜の優れた特性も、下地のポリシリコンが平坦な場合
にしか発揮されず、下地のポリシリコンが平坦でなく凹
凸を有していたり、エツチングされた端部を有するよう
な場合には、CVD二酸化シリコン膜の電気的特性は著
しく劣化してしまう。第4図は平坦なポリシリコン上と
段差部を有するポリシリコン上とに堆積したCVD二酸
化シリコン膜の電流密度と電界強度の比較を示す、明ら
かに段差部を有するポリシリコン上の特性曲線aは平坦
なポリシリコン上の特性曲線すに比べ劣っている。従っ
て、半導体不揮発性メモリにおいて、浮遊ゲート電極5
と制御ゲート電極7との間の層間絶縁膜16が浮遊ゲー
ト電極5上の段差部を含む場合、層間絶縁膜16の特性
は十分でなく、浮遊ゲート電極5内の電子は層間絶縁膜
16を通り抜は制御ゲート電極7へと揮発してしまう。
In addition to the above example, it is also possible to use a silicon dioxide film formed by a CVD method as the interlayer insulating film 16. Especially from dichlorosilane and nitrous oxide.
+ 2NgO→5iOz + 2Hc j! +2N
A CVD silicon dioxide film formed at 800 to 950° C. using the z reaction exhibits excellent insulating properties even when deposited on polysilicon. However, the excellent properties of the CVD silicon dioxide film are only exhibited when the underlying polysilicon is flat, and if the underlying polysilicon is not flat, has irregularities, or has etched edges. In some cases, the electrical properties of the CVD silicon dioxide film deteriorate significantly. FIG. 4 shows a comparison of the current density and electric field strength of CVD silicon dioxide films deposited on flat polysilicon and polysilicon with steps. It is clear that the characteristic curve a on polysilicon with steps is The characteristic curve is inferior to that of flat polysilicon. Therefore, in a semiconductor nonvolatile memory, the floating gate electrode 5
If the interlayer insulating film 16 between the floating gate electrode 5 and the control gate electrode 7 includes a stepped portion on the floating gate electrode 5, the characteristics of the interlayer insulating film 16 are not sufficient, and the electrons in the floating gate electrode 5 will pass through the interlayer insulating film 16. If it passes through, it will volatilize to the control gate electrode 7.

通常、集積化された半導体不揮発性メモリでは制御ゲー
ト電極7はいくつものメモリセルに渡って形成されるた
め、ソース・ドレイン領域2および3を結ぶ方向に対し
て、垂直な方向では、制御ゲート電極7は、必ず浮遊ゲ
ート電極5の端の段差部を有することになり、信頼性上
問題がある。
Normally, in an integrated semiconductor nonvolatile memory, the control gate electrode 7 is formed across a number of memory cells. 7 necessarily has a stepped portion at the end of the floating gate electrode 5, which poses a problem in terms of reliability.

そこで、この発明は従来のこのような欠点を解決し、製
造工程を増すこと無しに、高集積化可能でしかも信頼性
の高い半導体不揮発性メモリを提供するものである。
Therefore, the present invention solves these conventional drawbacks and provides a highly reliable semiconductor nonvolatile memory that can be highly integrated without increasing the number of manufacturing steps.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点を解決するために、この発明は、浮遊ゲート
電極周囲の層間絶縁膜として、通常の動作時に加わる電
圧よりも高い電圧を一度印加したポリシリコン上の酸化
膜あるいはCVDにより形成した二酸化シリコン膜やシ
リコン窒化膜を用いた。
In order to solve the above problems, the present invention provides an oxide film on polysilicon to which a voltage higher than that applied during normal operation is once applied, or a silicon dioxide film formed by CVD, as an interlayer insulating film around the floating gate electrode. film or silicon nitride film.

〔作用〕[Effect]

絶縁膜が静電破壊を起こさない程度の高い電圧を絶縁膜
に一度印加すると、絶縁膜中に初めから存在するトラッ
プおよび絶縁膜中を電流が流れることにより形成される
トラップは電子が満たされ(チャージアップ)、再び電
圧が印加されてもトラップに起因する電流は流れないの
で、流れる電流は極めて少なくなる。第5図は950℃
で形成したポリシリコン上の酸化膜の電流−電圧特性を
、初期特性(曲線C)とバイアス印加後の特性(曲線d
)について比較したものである。高い電圧を一度加える
ことで電流−電圧特性が改善されることが分かる。この
結果、層間絶縁膜の特性は改善され、浮遊ゲート電極か
らの電子の揮発は著しく減少するので、信頼性の高い半
導体不揮発性メモリを得ることができる。
When a high voltage that does not cause electrostatic damage to the insulating film is once applied to the insulating film, the traps that already exist in the insulating film and the traps that are formed when current flows through the insulating film are filled with electrons ( Even if the voltage is applied again (charge-up), no current due to the trap will flow, so the current flowing will be extremely small. Figure 5 is 950℃
The current-voltage characteristics of the oxide film on polysilicon formed in
). It can be seen that the current-voltage characteristics are improved by applying a high voltage once. As a result, the characteristics of the interlayer insulating film are improved and the volatilization of electrons from the floating gate electrode is significantly reduced, making it possible to obtain a highly reliable semiconductor nonvolatile memory.

〔実施例〕〔Example〕

以下、本発明の実施例を図面に基づいて説明する。第1
図は本発明による半導体不揮発性メモリの構造を概略的
に示す断面図である。P型の半導体基板lの表面にN型
のソース頷J!Ii2とドレイン領域3.および基板を
熱酸化して形成するゲート絶縁膜4を設け、ゲート絶縁
膜4の上にはリン等の不純物を含むポリシリコンよりな
る浮遊ゲート電極5が設けである。浮遊ゲート電極5の
周囲には一度バイアスを加えられた層間絶縁膜6がある
Embodiments of the present invention will be described below based on the drawings. 1st
The figure is a cross-sectional view schematically showing the structure of a semiconductor nonvolatile memory according to the present invention. An N-type source nods on the surface of a P-type semiconductor substrate l! Ii2 and drain region 3. A gate insulating film 4 is formed by thermally oxidizing the substrate, and a floating gate electrode 5 made of polysilicon containing impurities such as phosphorus is provided on the gate insulating film 4. Surrounding the floating gate electrode 5 is an interlayer insulating film 6 to which a bias is once applied.

層間絶縁膜6は浮遊ゲート電極5を熱酸化して形成して
も、CVD法によって二酸化シリコンを堆積して形成し
ても良い。層間絶縁膜6の上には制御ゲート電極7があ
り、浮遊ゲート電極5の電位を容l結合により制御する
。一度バイアスを加えられた層間絶縁膜6を形成するに
は、制御ゲート電FfA?およびその他の電極等の配線
をした後、P型半導体基板1.ソース領域2およびドレ
イン領域3をグランドレベルにしておいて、制御ゲート
電極7に層間絶縁膜6が破壊しない範囲でできるだけ高
い正の電圧を数十m5ecから数秒程度印加すれば良い
。こうすることで層間絶縁膜6の絶縁性は高まり、浮遊
ゲート電極5に一度注入された電子が層間絶縁膜6を通
って揮発してしまう割合を著しく小さくできるので、半
導体不揮発性メモリの信頼性を高くすることができる。
The interlayer insulating film 6 may be formed by thermally oxidizing the floating gate electrode 5, or may be formed by depositing silicon dioxide using the CVD method. A control gate electrode 7 is provided on the interlayer insulating film 6, and controls the potential of the floating gate electrode 5 by capacitive coupling. To form the interlayer insulating film 6 once biased, the control gate voltage FfA? After wiring other electrodes, etc., the P-type semiconductor substrate 1. With the source region 2 and drain region 3 at ground level, a positive voltage as high as possible is applied to the control gate electrode 7 within a range that does not destroy the interlayer insulating film 6 for about several tens of m5ec to several seconds. This increases the insulation properties of the interlayer insulating film 6 and significantly reduces the rate at which electrons once injected into the floating gate electrode 5 evaporate through the interlayer insulating film 6, improving the reliability of the semiconductor nonvolatile memory. can be made higher.

第6図は本発明の第2の実施例を示す半導体不揮発性メ
モリの断面図である。P型の半導体基板1の表面にN型
のソース領域2とドレイン領域3およびゲート絶縁膜4
を設け、ゲート絶縁膜4の上にはポリシリコンよりなる
浮遊ゲート電極5が設けである。浮遊ゲート電極5の周
囲には一度バイアスを加えられた眉間絶li膜6が設け
てあり、さらに眉間絶縁1f!6の上には制御ゲート電
極7および浮遊ゲート電極5と半導体基板1にまたがる
ようにして選択ゲート電極9が設けである。この構造を
有する半導体不揮発性メモリの特徴および動作について
は、特開昭58−64068号公報において詳述されて
いるのでここでは改めて述べない。
FIG. 6 is a sectional view of a semiconductor nonvolatile memory showing a second embodiment of the present invention. An N-type source region 2, a drain region 3, and a gate insulating film 4 are formed on the surface of a P-type semiconductor substrate 1.
A floating gate electrode 5 made of polysilicon is provided on the gate insulating film 4. Around the floating gate electrode 5, a glabellar insulating film 6 to which a bias is once applied is provided, and further glabellar insulation 1f! A selection gate electrode 9 is provided on the control gate electrode 6 so as to span the control gate electrode 7, the floating gate electrode 5, and the semiconductor substrate 1. The characteristics and operation of the semiconductor nonvolatile memory having this structure are detailed in Japanese Patent Application Laid-open No. 58-64068, so they will not be described again here.

本実施例において層間絶縁膜6を介して制御ゲート電極
7および選択ゲート電極9が浮遊ゲート電極5と相対し
ている。特に選択ゲート電極9は浮遊ゲート電極5の端
において段差を形成している。さらにこの半導体不揮発
性メモリの情報を読み出す時は、制御ゲート電極7はグ
ランドレヘルであるが、選択ゲート電極9は通常5Vに
バイアスされる。そこで、浮遊ゲート電極5に電子が注
入されて負に帯電している時、選択ゲート電極9への電
子の揮発が心配されるわけであるが、層間絶縁膜6とし
て、一度バイアスを加えられた絶縁膜を用いているので
十分な信頼性が得られる。第7図はメモリのしきい値電
圧の選択ゲートバイアス印加時間への依存性を示してい
る。この図は通常よりも高い電圧を選択ゲート電極9に
加え、浮遊ゲート電極5に注入された電子が時間ととも
に選択ゲート電極9へと揮発する様子を表している。
In this embodiment, a control gate electrode 7 and a selection gate electrode 9 are opposed to a floating gate electrode 5 with an interlayer insulating film 6 interposed therebetween. In particular, the selection gate electrode 9 forms a step at the end of the floating gate electrode 5. Furthermore, when reading information from this semiconductor nonvolatile memory, the control gate electrode 7 is at ground level, but the selection gate electrode 9 is normally biased to 5V. Therefore, when electrons are injected into the floating gate electrode 5 and it becomes negatively charged, there is a concern that the electrons will volatilize to the selection gate electrode 9. Since an insulating film is used, sufficient reliability can be obtained. FIG. 7 shows the dependence of the threshold voltage of the memory on the selection gate bias application time. This figure shows how a higher voltage than usual is applied to the selection gate electrode 9, and the electrons injected into the floating gate electrode 5 volatilize to the selection gate electrode 9 over time.

一度バイアスを印加された酸化膜を層間絶縁膜に用いた
メモリの特性(曲線e)は、通常の酸化膜を用いたメモ
リの特性(曲線f)に比べ、しきい値の下がる割合が小
さく、保持特性の向上していることが分かる。
The characteristics of a memory that uses an oxide film as an interlayer insulating film once a bias is applied (curve e) has a smaller rate of decrease in threshold value than the characteristics of a memory that uses a normal oxide film (curve f). It can be seen that the retention characteristics are improved.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明は浮遊ゲート電極と制御ゲー
ト電極および選択ゲート電極との間の層間絶縁膜として
一度高い電圧を加え、膜中のトラップがチャージアップ
されている酸化膜等の絶縁膜を用いることで、浮遊ゲー
ト電極からの電子の揮発の著しく少ない、保持特性に優
れた、信頼性の高い半導体不揮発性メモリを提供できる
ものである。
As described above, the present invention uses an insulating film such as an oxide film to which a high voltage is once applied as an interlayer insulating film between a floating gate electrode, a control gate electrode, and a selection gate electrode, and traps in the film are charged up. By using this, it is possible to provide a highly reliable semiconductor nonvolatile memory with extremely low volatilization of electrons from the floating gate electrode and excellent retention characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による半導体不揮発性メモリの一実施例
の構造を示す断面図、第2図は従来の半導体不揮発性メ
モリの構造を示す断面図、第3図は異なる温度で形成し
た酸化膜における電流密度の電界強度への依存特性を示
す図、第4図は段差上あるいは平坦上に形成された酸化
膜における電流密度の電界強度への依存特性を示す図、
第5図は酸化膜の初期特性とバイアス印加後の特性を比
べるためにそれぞれの酸化膜における電流密度の電界強
度への依存性を示す図、第6図は本発明による半導体不
揮発性メモリの他の実施例の構造を示す断面図、第7図
は半導体不揮発性メモリのしきい値電圧の選択ゲートバ
イアス印加時間への依存性を示す図である。 l・・・半導体基板 2・・・ソース領域 3・・・ドレイン領域 4・・・ゲート絶縁膜 5・・・浮遊ゲート電極 6・・・一度バイアスを加えられた層間絶縁膜16・・
・層間絶縁膜 9・・・選択ゲート電極 以上 出願人 セイコー電子工業株式会社 代理人 弁理士 最 上  務(他1名) パすH’5
2図 頓外良り劇の雷濁り弧度への(衣5肚兄示す間第3図 第4図 第6図 速l(ゲ’−ト/<:イア又1乍加日寺関 (矛り叉モ
ーリΩしご、\引℃唱2匠−o直りパ−沙\イア又f鼎
Q吟唄7依尽桂に示■凋 第7図 手続補正書帽釦 昭和62年特 許 願 第148249号2、発明の名
称 半導体不揮発性メモリ 3、補正をする者 4、代理人 ■104  東京都中央区京橋2丁目6番21号株式会
社 側部セイコー内 最上特許事務所5、補正の対象 しき・・(直電凰(V、) セ氏誤脱〈470辺り
FIG. 1 is a sectional view showing the structure of an embodiment of a semiconductor nonvolatile memory according to the present invention, FIG. 2 is a sectional view showing the structure of a conventional semiconductor nonvolatile memory, and FIG. 3 is an oxide film formed at different temperatures. Figure 4 is a diagram showing the dependence of current density on electric field strength in an oxide film formed on a step or flat surface.
FIG. 5 is a diagram showing the dependence of the current density on the electric field strength in each oxide film in order to compare the initial characteristics of the oxide film and the characteristics after bias application, and FIG. FIG. 7 is a cross-sectional view showing the structure of an embodiment of the present invention, and FIG. 7 is a diagram showing the dependence of the threshold voltage of the semiconductor nonvolatile memory on the selection gate bias application time. l... Semiconductor substrate 2... Source region 3... Drain region 4... Gate insulating film 5... Floating gate electrode 6... Interlayer insulating film 16 once biased...
・Interlayer insulating film 9...selection gate electrode and above Applicant: Seiko Electronic Industries Co., Ltd. Agent: Patent attorney Tsutomu Mogami (1 other person) Pass H'5
2. The thunder and cloudy arc of the 2nd picture of the drama was different from the previous one. Figure 7 Procedural amendment cap button 1986 Patent application No. 148249 No. 2, Name of the invention Semiconductor non-volatile memory 3, Person making the amendment 4, Agent ■ 104 2-6-21 Kyobashi, Chuo-ku, Tokyo, Seiko Seiko Co., Ltd. Mogami Patent Office 5, Subject of the amendment・(Direct Denou (V) Mr. Se mistakenly omitted (around 470)

Claims (2)

【特許請求の範囲】[Claims] (1)第1導電型の半導体基板表面部分に互いに間隔を
置いて設けられた第1導電型と異なる第2導電型のソー
ス・ドレイン領域と、前記ソース・ドレイン領域間の半
導体基板表面に設けられたゲート絶縁膜と、前記ゲート
絶縁膜上に設けられた浮遊ゲート電極と、前記浮遊ゲー
ト電極の周囲に設けられた層間絶縁膜と、前記層間絶縁
膜の上に設けられた制御ゲート電極とからなる半導体不
揮発性メモリにおいて、前記層間絶縁膜は、膜中の電子
及び正孔のトラップが通常の動作時に加わる電圧よりも
高い電圧を加えることでチャージアップされていること
を特徴とする半導体不揮発性メモリ。
(1) Source/drain regions of a second conductivity type different from the first conductivity type provided at intervals on the surface portion of the semiconductor substrate of the first conductivity type, and source/drain regions provided on the surface of the semiconductor substrate between the source/drain regions. a floating gate electrode provided on the gate insulating film, an interlayer insulating film provided around the floating gate electrode, and a control gate electrode provided on the interlayer insulating film. A semiconductor non-volatile memory comprising: a semiconductor non-volatile memory characterized in that the interlayer insulating film is charged up by applying a voltage higher than the voltage applied during normal operation to trap electrons and holes in the film; sexual memory.
(2)第1導電型の半導体基板表面部分に互いに間隔を
おいて設けられた第1導電型と異なる第2導電型のソー
ス・ドレイン領域と、前記ソース・ドレイン領域間の半
導体基板表面に設けられたゲート絶縁膜と、前記ゲート
絶縁膜上のドレイン側に設けられた浮遊ゲート電極と、
前記浮遊ゲート電極の周囲に設けられた層間絶縁膜と、
前記ゲート絶縁膜上のソース側から前記浮遊ゲート電極
上の前記層間絶縁膜にまたがり設けられた選択ゲート電
極と、前記浮遊ゲート電極上に前記層間絶縁膜を介して
設けられた制御ゲート電極とからなる半導体不揮発性メ
モリにおいて、前記層間絶縁膜は、膜中の電子及び正孔
のトラップが通常の動作時に加わる電圧よりも高い電圧
を加えることでチャージアップされていることを特徴と
する半導体不揮発性メモリ。
(2) source/drain regions of a second conductivity type different from the first conductivity type provided at intervals on the surface portion of the semiconductor substrate of the first conductivity type; and source/drain regions of a second conductivity type different from the first conductivity type provided on the surface of the semiconductor substrate between the source/drain regions; a floating gate electrode provided on the drain side on the gate insulating film;
an interlayer insulating film provided around the floating gate electrode;
A selection gate electrode provided across the interlayer insulating film on the floating gate electrode from the source side on the gate insulating film, and a control gate electrode provided on the floating gate electrode via the interlayer insulating film. A semiconductor nonvolatile memory characterized in that the interlayer insulating film is charged up by applying a voltage higher than the voltage applied during normal operation to trap electrons and holes in the film. memory.
JP14824987A 1987-06-15 1987-06-15 Semiconductor nonvolatile memory Pending JPS63311767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14824987A JPS63311767A (en) 1987-06-15 1987-06-15 Semiconductor nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14824987A JPS63311767A (en) 1987-06-15 1987-06-15 Semiconductor nonvolatile memory

Publications (1)

Publication Number Publication Date
JPS63311767A true JPS63311767A (en) 1988-12-20

Family

ID=15448567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14824987A Pending JPS63311767A (en) 1987-06-15 1987-06-15 Semiconductor nonvolatile memory

Country Status (1)

Country Link
JP (1) JPS63311767A (en)

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