JPS63308422A - Buffer device for pcm audio signal - Google Patents

Abstract

PURPOSE:To perform conversion to a PCM audio signal of different clock signal frequency and to reduce signal deterioration by extracting or inserting a write clock signal or read clock signal at such timing that the level of write- side PCM audio signal is large if the write clock signal and read clock signal shift are out of phase with each other as specified. CONSTITUTION:A signal level comparing circuit 3 is provided as a circuit which is connected to an audio serial signal input terminal 1 and a clock signal input terminal 2 and compares the level of an 8-bit PCM audio serial signal with a prescribed level, and a means for extracting or inserting the clock signal is so constituted as to performs the extraction or insertion at large-audio-level timing according to the output of the detection circuit. Namely, the detection circuit detects the level of the write-side PCM audio signal. The extraction or insertion is performed at the large-audio-level timing according to the output of the circuit detected by the means for extracting or inserting the clock signal. Thus, the conversion to the PCM audio signal of different clock signal frequency is performed and the signal deteriorations reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides PCM control between two points with different clock signal frequencies.
The present invention relates to an audio signal buffer device.

〔overview〕

The present invention provides a buffer device for PCM audio signals between two points having different clock signal frequencies, when a predetermined phase shift occurs between the write clock signal and the read clock signal.
By extracting or inserting the write clock signal or read clock signal at the timing when the level of the PCM audio signal on the writing side is high, it is possible to convert the clock signal to a PCM audio signal with a different clock signal frequency, and to prevent signal deterioration. It was designed to be as small as possible.

[Conventional technology]

FIG. 2 is a block diagram of a conventional PCM audio signal buffer device.

Conventionally, a PCM audio signal buffer device, as shown in FIG. and output an analog signal. This analog signal is connected to one of the analog/digital converters 32, and a clock signal having a frequency different from the clock signal connected to the clock signal input terminal 2 of the digital/analog converter 31 is input to the clock signal input terminal 20. Connect to the other's human power via.

As a result of the above, the speed-converted PCM audio signal was taken out from the audio serial signal output terminal 33.

[Problem that the invention seeks to solve]

However, in such conventional PCM audio signal buffer devices, the digital signal is first converted into an analog signal,
Furthermore, since the analog signal is converted into a digital signal, there is a drawback that signal deterioration that occurs when converting an analog signal into a digital signal cannot be avoided.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and aims to provide a buffer device for PCM audio signals that can be converted into PCM audio signals having different clock signal frequencies and that exhibits less signal deterioration.

[Failure to solve the problem]

The present invention provides an elastic store, a writing means for writing a PCM audio signal into the elastic store in synchronization with a write clock, and a PCM audio signal from the elastic store in synchronization with a read clock signal asynchronous to the write clock signal.
reading means for reading an audio signal; and means for comparing the phases of the write clock signal and the read clock signal and extracting or inserting the write clock signal or the read clock signal when a predetermined deviation occurs. In the PCM audio signal buffer device, a circuit for detecting the level of the PCM audio signal is provided on the writing side, and the means for extracting or inserting the clock signal detects the audio level according to the output of the detecting circuit. It is characterized by a configuration in which extraction or insertion is performed at a large timing.

[Effect]

A detection circuit detects the level of the PCM audio signal on the writing side. The means for extracting or inserting the clock signal executes the extraction or insertion at a timing when the audio level is high according to the output of the circuit detected.

By the above operation, it is possible to convert the clock signal into a PCM audio signal having a different frequency, and to reduce signal deterioration.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block configuration diagram of a PCM audio signal buffer device according to an embodiment of the present invention. In Figure 1, the buffer device for the PCM audio signal consists of 8 bits from MSB to LSB (not shown).
audio serial signal input terminal 1 to which the audio serial signals of P and CM are manually input, a clock signal input terminal 2 to which the first clock signal from outside the figure is manually input, audio serial signal input terminal 1 and clock signal input terminal 2 (8 pins) PCM
The apparatus includes a serial-to-parallel conversion circuit 4 that converts audio signals into parallel signals, and eight elastic stores 5 to 12 that manually input the outputs of the serial-to-parallel conversion circuit 4.

In addition, the clock signal input terminal 20 for inputting a second clock signal from outside the figure and the outputs of the elastic stores 5 to 12 are manually input, and the second clock signal is input from the clock signal input terminal 20 to generate an audio serial signal. A parallel-to-serial conversion circuit 18 to output, an audio serial signal output terminal 19 to output the output of the parallel-to-serial conversion circuit 18 outside the figure, and an elastic store by manually inputting a write clock signal obtained by dividing the first clock signal by N. A write counter 14, which is a writing means, generates a timing pulse to write to elastic stores 5 to 12, and a read clock signal obtained by dividing the second clock signal by N, and a timing pulse to read from elastic stores 5 to 12 is generated manually. A read counter 15 is provided as a read means for generating the data.

Here, the feature of the present invention is that the circuit is connected to the audio serial signal input terminal 1 and the clock signal input terminal 2, and is a signal level detecting circuit that compares the level of the PCM audio serial signal with a predetermined level value. A comparison circuit 3 is provided, and
The output of the write counter 14, the output of the read output rank 15, and the output of the signal level comparison circuit 3, which are means for extracting the clock signal, are manually input, and the output of the write counter 14 is higher than the output of the read counter 15. When the phase of the audio serial signal advances by approximately 1 bit, the first control signal is output when the level of the audio serial signal is equal to or higher than the specified level value, and the output of the write counter 14 lags the output of the read counter 15 by approximately 1 bit in phase. A phase comparator 17 outputs a second control signal when the signal level is equal to or higher than a predetermined level value, and a write clock signal obtained by dividing the first clock signal by N from the serial/parallel conversion circuit 4 is inputted and written. A clock 1-bit extraction circuit 13 extracts one bit from the write clock signal when the first control signal is input to the write counter 14 manually, and a successive clock obtained by dividing the second clock signal from the parallel-to-serial conversion circuit 18 by N. A clock 1 bit extraction circuit 16 is provided which inputs a signal and applies it to the read counter 15, and extracts 1 bit from the read clock signal when a second control signal is input.

The operation of the PCM audio signal buffer device having such a configuration will be explained. In FIG. 1, an 8-pin PCM audio serial signal is input to an audio serial signal input terminal 1.

A first clock signal of the data input to the audio serial signal input terminal 1 is input to the clock signal input terminal 2 . The 8-bit serial signal is converted into an 8-bit parallel signal by the serial-parallel conversion circuit 4, and a write clock signal corresponding to this 8-bit parallel signal is generated. This write clock signal passes through a clock 1 bit sampling circuit 13 and is inputted to a write counter 14. The write counter 14 generates a timing pulse to write the parallelized 8-bit parallel signal into the stick stores 5 to 12, and with this timing pulse, the 8-bit parallel signal output from the serial-parallel conversion circuit 4 becomes Written to each elastic store 5-12.

A second clock signal having a slightly different frequency from the first clock signal input to the clock signal input terminal 2 is input to the other clock signal input terminal 20, and this second clock signal is input to the parallel-to-serial conversion circuit. A circuit 16 divides the clock frequency by N by 18 and extracts one bit of the clock as a read clock signal.
The data is manually inputted to the read counter 15 through the .

Due to the timing pulse generated by the read counter 5,
An 8-bit parallel signal is read from elastic stores 5 to 12, and this 8-bit parallel signal is sent to the parallel-to-serial conversion circuit 18.
and converted into an 8-bit audio serial signal.

The output of the write counter 4 and the output of the read counter 5 are compared by the phase comparator 17, and the output phase of the write counter 4 is approximately 1 bit ahead of the output phase of the successive counter 5, and the signal level comparison circuit 3 Immediately at the timing when a high level higher than a prescribed level value is detected, a clock 1 bit extraction circuit 13 extracts 1 bit of the write clock signal inputted to the write counter 4.

On the other hand, the output phase of the write counter 14 is the same as that of the read counter 15.
When the level comparator circuit 3 detects a high level that is nearly 1 bit behind the output phase of the clock and is higher than the specified level value, the successive clock signal is immediately inputted to the readout counter 15 by the clock 1 bit sampling circuit 16. Extract 1 bit from the signal.

In this embodiment, one sample is extracted from a high-level portion of the serial audio signal, but the previous sample may be inserted again.

〔Effect of the invention〕

As explained above, the present invention has the advantage that it can be converted into a PCM audio signal with a different clock signal frequency, and since the extraction or insertion of one sample is performed at a portion where the audio level is high, it is difficult to detect as distortion. It has a positive effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PCM audio signal buffer device according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional PCM audio signal buffer device. 1...Audio serial signal input terminal, 2.20...Clock signal input terminal, 3...Signal level comparison circuit, 4...
・Serial parallel conversion circuit, 5 to 12... Elastic store, 13... Clock 1 bit extraction circuit, 14...
Write counter, 15... Read counter, 16... Clock 1 bit sampling circuit, 17... Phase comparator, 18
...Parallel-serial conversion circuit, 19.33...Audio serial signal output terminal, 31...Digital-to-analog converter,
32...Analog-digital converter.

Claims (1)

[Claims] (1) An elastic store and a PC that writes to this elastic store in synchronization with the clock.
writing means for writing an M audio signal; reading means for reading a PCM audio signal from the elastic store in synchronization with a read clock signal asynchronous with the write clock signal; and the write clock signal and the read clock signal. In a PCM audio signal buffer device, the PCM audio signal buffer device is provided with a means for extracting or inserting a write clock signal or a read clock signal when a predetermined shift occurs by comparing the phase with the PCM audio signal on the writing side. A PCM characterized in that a level detecting circuit is provided, and the means for extracting or inserting the clock signal is configured to execute the extracting or inserting at a timing when the audio level is high according to the output of the detecting circuit. Audio signal buffer device.