JPH0479513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to speed conversion means for pulse-modulated image digital signals.

〔overview〕

In the method of converting the speed of a parallel image signal to a slightly lower speed, the present invention converts one bit of the clock input to the writing means and reading means of an elastic store that temporarily stores the image signal into the output of this means. It is possible to change the pulse width of the synchronization pulse or equalization pulse of the image signal by extracting it based on the phase difference between the two.

[Conventional technology]

In the conventional speed conversion of a pulse-modulated image digital signal, as shown in FIG. Convert analog signal using output terminal 6
1 and connect this analog signal to the conversion input terminal 62 of the analog-to-digital converter 63,
A method has been used in which a clock having a different frequency from the clock connected to the clock input terminal 59 of the analog-to-digital converter 60 is connected to the clock input terminal 72 and data signals are extracted from the data output terminals 64-71.

[Problems to be solved by the invention] In such conventional image digital speed conversion methods, the digital signal is converted back to an analog signal and then this analog signal is further encoded into a digital signal, so the image quality deteriorates. There are drawbacks to doing so.

The present invention aims to eliminate such drawbacks and to provide an image signal speed conversion device that does not cause deterioration in image quality.

[Means for solving problems]

The present invention provides N clocks with one clock frequency.
An image signal speed conversion device that inputs a parallel bit (N is an integer of 2 or more) image signal, converts the clock frequency of this image signal to another frequency slightly lower than this one frequency, and outputs the clock frequency. A detection means for detecting a synchronization pulse of an image signal, N elastic stores, a write counter for generating a write timing signal to the elastic store based on the one clock, and the other clock. a read counter that generates a read timing signal to the elastic store based on the above; a phase comparison means that compares the phase of the output of the write counter with the phase of the output of the read counter; The present invention is characterized by comprising a clock extracting means for extracting one bit of the clock input to the write counter or the read counter based on the output.

Further, the synchronization pulse may be a horizontal synchronization pulse of the image signal.

Further, the synchronization pulse may be a vertical synchronization pulse of the image signal.

[Effect]

The phase comparison means compares the phase of the output of the write counter and the phase of the output of the read counter, and detects that the phase of the output of the write counter is nearly one bit ahead of the phase of the output of the read counter. ,
When a horizontal synchronization pulse or a vertical synchronization pulse is detected by the image signal synchronization pulse detection section, one bit of the clock input to the write counter is immediately extracted, and the phase of the output of the write counter matches that of the read counter. When it is detected that the output phase is delayed by nearly 1 bit, and the horizontal synchronization pulse or vertical synchronization pulse is detected by the synchronization pulse detection section of the image signal, the clock input to the read counter immediately changes to 1 bit. It is extracted. Thereby, the pulse width of the synchronization pulse of the image signal is changed to convert the speed of the image signal.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit connection diagram showing the configuration of an embodiment of the present invention. This example uses 8-bit parallel
The case of an interface between two points whose clock frequencies of PCM image signals are slightly different is shown. An 8-bit parallel PCM image data signal is input to data input terminals 1 to 8 of this interface circuit. Clock input terminal 9 has data input terminal 1.
The clock of the data input to 8 is input. The clock input to this clock input terminal 9 passes through a clock extraction circuit 28 and is input to a write counter 29. The write counter 29 generates a timing pulse for writing the data signals input to the data input terminals 1 to 8 into the elastic stores 10 to 17, and in response to this timing pulse, the data signals input to the data input terminals 1 to 8 are written. are written to elastic stores 10-17, respectively. A clock whose frequency is slightly different from the clock frequency inputted from the clock input terminal 9 is inputted to the other clock input terminal 26, and the inputted clock signal is inputted to the read counter 31 through the clock extraction circuit 32. Data signals are read from the elastic stores 10-17 in accordance with timing pulses generated by the read counter 31 and output to data output terminals 18-25, respectively.

The output of the write counter 29 and the output of the read counter 31 are compared by a phase comparator 30, and the output of the write counter 29 is compared with the output of the read counter 31.
9 leads the output phase of the read counter 31 by nearly 1 bit, the synchronization pulse detection circuit 2
When a synchronization pulse or equalization pulse of the image signal is detected at step 7, the clock extraction circuit 28 extracts one of the clocks input to the write counter 29 from the 8-bit PCM image parallel signal input to the data input terminals 1 to 8. Remove the bit. In this case, when the 8-bit PCM image parallel signal appearing at the data output terminals 18-25 is demodulated into an analog signal, the pulse width of the synchronization pulse or equalization pulse from which one bit is extracted is shortened by one clock period.

The output phase of the write counter 29 is the same as that of the read counter 3.
When an image signal synchronization pulse or an equalization pulse is detected, the clock extraction circuit 32 extracts the clock from the 8-bit PCM image parallel signal input to the clock data input terminals 1 to 8. One bit of the clock input to the read counter 31 is extracted. In this case, when the 8-bit PCM image parallel signal appearing at the data output terminals 18-25 is demodulated into an analog signal, the pulse width of the synchronization pulse or equalization pulse from which one bit is extracted is lengthened by one clock period.

〔Effect of the invention〕

As explained above, the present invention has N bits (N
is an arbitrary integer) For the parallel PCM image signal, extract one clock of the N-bit parallel PCM image signal of the synchronization pulse or equalization pulse part of the image signal, or repeat the previous parallel PCM image signal again. Since it is inserted and converted into a data signal with a different clock frequency, there is no deterioration in image quality due to this conversion, compared to the conventional method of demodulating to an analog signal and converting it to PCM again. .

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of a conventional example. 1-8, 51-58...Data input terminals. 9,
26, 59, 72...Clock input terminal, 10~
17...Elastic store, 18-25,64
~71... Data output terminal, 27... Synchronous pulse detection circuit, 28... Clock extraction circuit, 29...
Write counter, 30... Phase comparator, 31... Read counter, 60... Digital analog converter,
61...Conversion output terminal, 62...Conversion input terminal,
63...Analog-digital converter.

Claims (1)

[Claims] 1. Input N-bit (N is an integer of 2 or more) parallel image signals having one clock frequency,
An image signal speed conversion device that converts the clock frequency of this image signal to another frequency slightly lower than this one frequency and outputs the same, includes a detection means for detecting a synchronization pulse of an input image signal, and N elastics. a write counter that generates a write timing signal to the elastic store based on the one clock; and a read counter that generates a read timing signal to the elastic store based on the other clock. a counter; a phase comparison means for comparing the phase of the output of the write counter with the phase of the output of the read counter; and input to the write counter or the read counter based on the output of the phase comparison means. 1. An image signal speed conversion device comprising: clock extraction means for extracting one bit from a clock. 2. The image signal speed conversion device according to claim 1, wherein the synchronization pulse is a horizontal synchronization pulse of the image signal. 3. The image signal speed conversion device according to claim 1, wherein the synchronization pulse is a vertical synchronization pulse of the image signal.