JPS63308369A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance and to make it possible to obtain larger capacitance in the same area by a method wherein the control region of a semiconductor element and one electrode of a capacitor are shielded with a conductive layer. CONSTITUTION:An aluminum conductive layer 26 is formed on the gate 5 of a load transistor Q2 and the upper part of one electrode 7 of the capacitor C connected to the gate 5. Said conductive layer 26 is connected to the impurity diffusion region 6, which becomes the source of the load transistor Q2 and the impurity diffusion region 8a of the capacitor C. As one electrode 7 of the capacitor C and the gate electrode 5 of the load transistor Q2 are shielded from the outside by the conductive layer 26, parasitic capacitance can be reduced. Also, a new capacitor Ca is formed between the conductive layer 26 and the one electrode 7 of the capacitor C, and also between conductive layer 26 and the gate electrode 5 of the transistor Q2. In other words, as the capacitor Ca is connected in parallel with the capacitor C, a large capacitor value can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of a circuit device including a feedback capacitor.

[Prior Art] FIG. 6 is a diagram showing a pattern layout of a conventional semiconductor integrated circuit device constituted by a MOS transistor and a capacitive element, and FIG. 7A is a cross-sectional view of FIG.
FIG. 8A is a sectional view taken along the line ■--■ in FIG. 6. Also, the seventh
Figure B is an equivalent circuit diagram corresponding to Figure 7A, and Figure 8B is an equivalent circuit diagram corresponding to Figure 8.
FIG. 3 is an equivalent circuit diagram corresponding to FIG. FIG. 4 is a diagram showing the circuit configuration of the semiconductor integrated circuit IAW1 of FIG. 6.

This semiconductor integrated circuit device functions as a driver circuit.

In FIGS. 4 and 6, MOS transistor Q1
The drain 1 of is connected to the input terminal 12, and the gate 2 of ?
! It is connected to the i'i1 terminal 15. The source 3 of this transistor Q1 is connected to the gate 5 of a MOS transistor Q2 which serves as a load transistor, and
It is connected to one electrode 7 of a capacitive element C that serves as a bootstrap capacitor.

The drain 4 of the transistor Q2 is 1! It is connected to the source terminal 15. Further, the source 6 of the transistor Q2 is connected to the other electrode 8 of the capacitive element C, and the source 6 of the transistor Q2 is connected to the other electrode 8 of the capacitor C.
It is connected to the drain 9 of the S transistor Q3, and further connected to the output terminal 14. Transistor Q3
The gate 10 of is connected to the input terminal 13, and the source 11 is grounded. Input terminal 12 receives input signal 'J
in, and the input terminal 13 receives an input signal viI
'1□ is given, and the output terminal 14 outputs the output signal you
t is derived. The N source terminal 15 has a power supply potential ■
CC will be given.

The configuration of capacitive element C will be explained using FIG. 7A.

Impurity diffusion regions 8a, 8a are formed at a predetermined interval on the surface of the semiconductor substrate 21, and these impurity diffusion regions w
One electrode 7 is formed on the region between the fourth regions Ba and 8a with an insulation n18 interposed therebetween. And these surfaces are absolutely 1&
It is covered with mold resin 25 via m23 and m24. In this capacitive element C, when the potential of one electrode 7 with respect to the semiconductor substrate 21 becomes equal to or higher than a predetermined potential, a channel 8 is formed in a region of the semiconductor substrate 21 below this negative charging electrode 7, and this becomes the other electrode.

As shown in FIG. 7B, a capacitor 1c is formed between the -charging electrode 7 and the other 'R1@8, and a parasitic capacitor 1cs is formed between the -charging wA7 and the molding resin 25.

Next, the configuration of transistor Q2 will be explained using FIG. 8A.

An impurity diffusion region 4 serving as a drain and an impurity diffusion region 6 serving as a source are formed at a predetermined interval on the surface of the semiconductor substrate 21, and these impurity diffusion regions 1*4, 6
A gate bridge 5 is formed on the Ii region in between with an insulating film 18 interposed therebetween. And these surfaces are insulated 123.24
It is covered with mold resin 25 through. The configurations of transistors Q1 and Q3 are also substantially similar to the configuration of transistor Q2.

As shown in FIG. 8B, a parasitic capacitance Ics is formed between the gate electrode 5 of the transistor Q2 and the mold tree W125.

Next, the operation of this semiconductor integrated circuit will be explained using the timing chart of FIG.

Time t. In the case of odor, the input signal V in, is at a low potential (0
level), the input signal Vin2 is at a high potential (VCC level), and the output signal yot+t is at a low potential (O level).

When the input signal Vin becomes a high potential at time t1,
The parasitic capacitance 1cs is charged, and the potential of one electrode 7 of the capacitive element C increases. Then, the - charging electrode 7 and the semiconductor substrate 2
When the voltage between 1 and 1 becomes higher than the voltage VTN, -
A channel 8 is formed at the bottom of the charging electrode 7, which is a container! l
This becomes the other electrode of element C.

When the capacitive element C is charged and the potential of one electrode 7 with respect to the semiconductor substrate 21, that is, the potential of the gate electrode 5 of the h-load transistor Q2 becomes equal to or higher than the threshold voltage vTH, the load transistor Q2 is turned on.

However, since the input signal Vin2 is at a high potential, the source current of the transistor Q2 flows to the transistor Q3, and the output signal yout maintains a low potential state.

At time t2, when the input signal Vin2 becomes low potential, the transistor Q3 is turned off. As a result, the potential at the output terminal 14 begins to rise. As the potential of the output terminal 14 rises, the potential of the load 1 - the gate 5 of the transistor Q2 increases due to the coupling via the capacitive element C, while maintaining the relationship of the potential of the output terminal 14 and the threshold voltage Vt1. do.

And eventually it will rise to . Here, C is the capacitance value of capacitive element C, C8
is the capacitance value of the parasitic capacitance cs.

Thereafter, the process returns to the initial state at time t3. That is, the input signal V in becomes a low potential, the input signal Vin2 becomes an old potential, and the output signal @V out becomes a low potential. ,
After this, this operation is repeated.

[Problems to be solved by the invention 1) In the conventional semiconductor integrated circuit device described above, when the gate potential of the load transistor Q2 is low, the on-resistance of the transistor Q2 increases and its drive ability decreases. However, the operating speed of the circuit becomes slower.

In order to make the gate potential V of the load transistor Q2 sufficiently high, as can be seen from equation (1), the parasitic capacitance lC
The capacitance value of the capacitive element C must be made sufficiently larger than the capacitance value of the capacitive element C, which requires a large area in terms of pattern layout.

However, there was a problem in that when the capacitance value of the capacitive element C was increased, the parasitic capacitance C8 also increased accordingly.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device having a small parasitic capacitance and a larger capacitance in the same area.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes a semiconductor element including a first impurity diffusion region, a second impurity diffusion region, and a control region, and one electrode and an R pole. a capacitor comprising: formed on a semiconductor substrate, one Nl electrode of the capacitor connected to a control region of the semiconductor element, and the other electrode of the capacitor connected to a second impurity diffusion region of the semiconductor element. It is something.

In particular, in the present invention, the III* region of the semiconductor element and the upper part of one electrode of the capacitor connected thereto are covered with a conductive layer, and this conductive layer is further connected to the second impurity diffusion region of the semiconductor element.

In the semiconductor integrated circuit device according to the present invention.

The conductive N layer shields the control region of the semiconductor element and one electrode of the capacitor connected thereto from the outside, thereby reducing parasitic capacitance existing around the control region of the semiconductor element and the one electrode of the capacitor.

Further, since this S conductive layer is connected to the second impurity diffusion region of the semiconductor element, that is, connected to the other electrode of the capacitor, the conductive layer is connected to the control region of the semiconductor element and the conductive layer is A new capacitor is formed between the layer and one electrode of the element.

The new capacitor formed by this conductive layer is connected in parallel to the capacitor composed of the negative charging electrode and the other electrode, and functions in the same way as the aforementioned capacitor.

Therefore, a larger capacitance is formed in the same area.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a pattern layout of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2A is a diagram showing the pattern layout of a semiconductor integrated circuit device according to an embodiment of the invention.
-I line sectional view and FIG. 3A are sectional views taken along ■--■ in FIG.

The configuration of this embodiment is similar to that shown in Figs. 6 to 6 except for the following points.
The structure is similar to that of the conventional example shown in FIG. 8B, and corresponding parts are given the same reference numerals and their explanations will be omitted.

Further, the circuit configuration and operation of this embodiment are substantially the same as those shown in FIGS. 4 and 5.

1, 2A and 3A, the gate 5 of the load transistor Q2 and the capacitive element C connected thereto.
A conductive layer 26 made of aluminum is formed on top of one electrode 7 with an insulating layer 123 interposed therebetween. This conductive layer 26 is in contact with the impurity diffusion region 6 serving as the source of the load transistor Q2 and the impurity diffusion region 8a of the capacitive element C.

This conductive layer 26 shields one electrode 7 of the capacitive element C and the gate electrode 5 of the load transistor Q2 from the outside.
The parasitic capacitance flcs existing between the gate electrode 5 and the mold resin 25 is reduced.

Also, guide! A new capacitance Ca is formed between 1i126 and one electrode 7 of capacitive element C and between conductive 1m26 and gate electrode 5 of transistor Q2 (see FIGS. 2B and 3B). Since the conductive layer 26 is connected to the impurity diffusion region 6 which becomes the source of the transistor Q2,
The capacitor Ca is connected in parallel to the capacitor C, and functions similarly to the capacitor C. As a result, a larger capacitance value than before can be obtained with the same area.

In this way, according to the above actual travel example, it is possible to reduce the parasitic capacitance C5 and obtain a larger capacity with the same area.

Therefore, in FIG. 4, the gate potential Vs of the load transistor Q2 can be made sufficiently high, so that the drive ability of the load transistor Q2 is increased and the operating speed of the circuit is increased.

In the above embodiments, the present invention is applied to a drive circuit, but the present invention can also be applied to other circuits equipped with feedback capacitance.

[Effects of the Invention] As described above, according to the present invention, since the control region of the semiconductor element and one electrode of the capacitor are shielded by the conductive layer, the parasitic capacitance is reduced, and the control region of the conductive layer and the semiconductor element are shielded. Since a new capacitor that functions in the same way as the above-mentioned capacitor is formed between the conductive layer and one electrode of the capacitive element, a large capacitance can be obtained with the same area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a pattern layout of a semiconductor integrated circuit device according to a practical example of the present invention, and FIG.
-I line screen diagram, Figure 2B is an equivalent circuit diagram corresponding to Figure 2A, Figure 3A is a sectional view taken along ■-m line of Figure 1, and Figure 3B is an equivalent circuit diagram corresponding to Figure 3A. . FIG. 4 is a diagram showing the circuit configurations of a semiconductor integrated circuit device according to an embodiment of the present invention and a conventional semiconductor integrated circuit device, and FIG. 5 is a timing chart for explaining the operation of the circuit of FIG. 4. FIG. 6 is a diagram showing a pattern layout of a conventional semiconductor integrated circuit device, FIG. 7A is a cross-sectional view along m-mIa in FIG.
7B is an equivalent circuit diagram corresponding to FIG. 7A, FIG. 8A is a sectional view taken along IV-IVIjl in FIG. 6, and FIG. 8B is an equivalent circuit diagram corresponding to FIG. 8A. In the figure, 01 to Q3 are MOS transistors, 1.4
．． 9 is the impurity diffusion region II which becomes the drain, 2°5.10
is a gate electrode, 3, 6.11 is an impurity diffusion region that becomes a source, C is a capacitor, 7 is one electrode, 8 is a channel that becomes the other electrode, 8a is an impurity diffusion region, 12.13 is an input terminal, 14 is a Output terminal, 15 is 1! Source terminal, 26 is conductor W
This is the i layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A semiconductor substrate, a first impurity diffusion region formed in a predetermined region of the semiconductor substrate and comprising a first impurity diffusion region, a second impurity diffusion region, and a control region for controlling a current flowing between these impurity diffusion regions. a semiconductor element; a capacitor formed in another predetermined region of the semiconductor substrate and comprising one electrode connected to the control region and the other electrode connected to the second impurity diffusion region; and the first semiconductor element. and a second electrode of the first semiconductor element.
A semiconductor integrated circuit device comprising a conductive layer connected to an impurity diffusion region. (2) controlling the first impurity diffusion region connected to the second impurity diffusion region of the first semiconductor element, the grounded second impurity diffusion region, and the current flowing between these impurity diffusion regions; a second semiconductor element comprising: a control region for controlling the first impurity diffusion region; further comprising: means for applying a predetermined potential to a first impurity diffusion region of the first semiconductor element; and means for charging one terminal of the capacitor; An input signal is applied to a control region of a semiconductor element, and an output signal is derived from a connection point between a second impurity diffusion region of the first semiconductor element and a first impurity diffusion region of the second semiconductor element. A semiconductor integrated circuit device according to claim 1, characterized in that: (3) The first and second semiconductor elements are MOS transistors, the first impurity diffusion region is a drain region, the second impurity diffusion region is a source region, and the control region is a gate electrode and a gate insulating film. Claim 1 or 2 is a gate region comprising:
The semiconductor integrated circuit device described in . (4) The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the capacitance is a bootstrap capacitance.