JPS62150597A - Boosting circuit - Google Patents

Abstract

PURPOSE:To reduce the chip cost by forming a diode by a p-n junction of polycrystal silicon deposited on the major plane of a semiconductor substrate. CONSTITUTION:Diodes D1-D4 are formed by the polycrystal silicon layer deposited on the major plane of the semiconductor substrate 5, boosting capacitors C1-C3 are formed by using part of the polycrystal silicon layer and p-wells 6a-6c formed in the semiconductor substrate 5 and the boosting circuit is formed as one chip together with other MOSIC memory or the like. The boosted voltage of a pre-stage is charged sequentially to the capacitor of each stage superimposingly through the conduction control of the diodes D1-D4, the potential of nodes 4a-4c rises, and a boosted voltage Vout boosted to the required value is outputted from an output terminal 2. The boosted loss is built-in potential Vbin of the diodes D1-D4 and suppressed to a value lower than the threshold voltage. Thus, the chip area and the cost are reduced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a booster circuit that generates a voltage for reading, for example, an E2 ROM (electrically rewritable non-volatile memory), and particularly relates to a booster circuit that can be easily reduced to one depth. This is to improve back pressure efficiency.

[Technical Preface of the Invention and its Problems] The back pressure circuit is used as a circuit for generating E2 ROM f7) l-included voltage or voltage for driving liquid crystal display panels of watches, etc., and is generally used together with the ICs that constitute these circuits. Manufactured in one piece.

As such conventional booster circuits, there are known charge pump type booster circuits based on a Kotscroft-Walton circuit as shown in FIGS. 3 and 4, for example.
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In Fig. 3, reference numeral 1 is an input terminal for the power supply voltage Vin, and 2 is an output terminal for the boosted voltage Vout. Capacitors 21a to 21e are arranged in parallel. The capacitors 21a to 21e are formed as MOS capacitors on a part of the main surface of a semiconductor substrate (not shown) in which an MNOS IC or the like is incorporated.

Diodes 22a to 22f are connected between one end of each of the capacitors 21a to 21e, and to the input and output stages, respectively, in a forward direction from the input terminal 1 side to the output terminal 2 side.

The diodes 22a to 22f are connected to the capacitors 21a to 22f.
If it is built into a semiconductor substrate like 21e, the electric charge charged in the capacitor will leak to the semiconductor substrate side during boost control using a clock signal (drive signal) described later, so it is externally attached.

Further, the other end of each capacitor 21b121d in an even stage is commonly connected to the input terminal 3a of the φ clock signal in the two-phase clock φ, φ with opposite phases, and the other end of each capacitor 21b121d in an odd stage
The other ends of 1a, 21c, and 21e are commonly connected to the φ clock signal input terminal 3b.

First, the capacitor 21a is charged to the power supply voltage Vin to J:Vin-Vbin (Vbin is the built-in voltage of the diode 22a). When the clock signal T rises (φ falls), the voltage at the node 4a connected by the capacitor 21a is boosted, and at the same time, the diode 22b is controlled to be conductive, and the boosted voltage is transferred to the next capacitor 21b. It will be charged. Next, the voltage at the node 4b is boosted at the rise of the clock signal φ (φ falls), and at the same time, the diode 22 Ch is controlled to be conductive, and the boosted voltage is charged to the next capacitor 21c.

In this way, each of the capacitors 21a to 21e is charged with the boosted voltage of the previous stage in a superimposed manner, and the potential of each node 4a to 4e rises, and the boosted voltage from the output terminal 2 is raised to a required voltage value. Vout is output.

However, in the booster circuit described above, the diode 2
2a to 22f are externally connected, so each node 4a
Parallel capacitances 23a to 23e are generated in the portions 4e to 4e, and are connected in parallel to the boosting capacitors 21a to 21e, respectively. Therefore, if the capacitance of each capacitor 21a to 218 is C1 and each parasitic capacitance 23a to 238 is Cs, the boosted voltage ΔV at each node 4a to 4e becomes ΔV=V inXC/(C+Cs), and the parasitic capacitance C8 decreases due to the influence of

Therefore, in order to compensate for this effect and boost the voltage to the required value, it is necessary to increase the capacity of the boost capacitor or increase the number of stages of capacitors, etc., which increases the chip area and requires assembly for mounting the diode. There were problems in that the number of man-hours increased, leading to an increase in cost, and furthermore, the rate of boosting the pressure decreased.

Further, in addition to the booster circuit shown in FIG. 3, the literature also discloses another booster circuit as shown in FIG. 5.

In this booster circuit, MOSFETs 24a to 24f are used in place of the diodes in the booster circuit shown in FIG. ing.

Each MO3FET 24a to 24f has its gate and drain connected and operates as a diode.

By the way, a reverse bias is applied between the MOSFET fabricated in the semiconductor substrate and the substrate, and the threshold voltage for switching the MO8F'ET increases due to this substrate bias effect. This threshold voltage acts as a loss in the operation of the booster circuit, resulting in a decrease in boosting efficiency.

Therefore, even in a booster circuit that uses diode-connected MOSFETs, in order to boost the voltage to the required voltage value, the number of backpressure stages must be increased to compensate for the above losses, resulting in an increase in chip area. However, the same problems as mentioned above arise, such as an increase in cost and a decrease in the rate of pressure increase.

[Purpose of the Invention] The present invention has been made based on the above-mentioned circumstances, and it is possible to reduce the loss of boost efficiency, obtain the required boost voltage output with a small number of boost stages, and reduce chip cost. It is an object of the present invention to provide a booster circuit that can increase the boosting speed.

[Summary of the Invention 1] In order to achieve the above object, the present invention forms a diode for voltage boost control by a junction between a ρ shadow region and an n shadow region of polycrystalline silicon deposited on the main surface of a semiconductor substrate. This avoids charge leakage when a diode is built into a semiconductor substrate, and also prevents leakage of charge when a diode is built into a semiconductor substrate.
This improves the boost efficiency by avoiding the increase in loss caused by the rise in threshold value due to the substrate bias effect when using ET, and also reduces the number of back pressure stages to boost the voltage to the required voltage value (by reducing the boost speed). It is designed to be enhanced.

[Embodiments of the Invention] Examples of the present invention will be described below based on FIGS. 1 and 2.

In FIGS. 1 and 2, parts that are the same as or equivalent to those in FIGS. 3 to 5 are designated by the same reference numerals and redundant explanations will be omitted.

First, to explain the structure, tube number 5 in FIG.
a, 6b, and 6c are formed at appropriate intervals.

Polycrystalline silicon electrodes (p+
Territory regions 8b and 8C18d are formed, and these p wells 6
With the MOS capacitor structure consisting of dielectric layers 7a, 7b, 7C1 and polycrystalline silicon electrodes 8b, 8c, 8d, back pressure capacitors C+, C2, C3 as shown in FIG. It is formed.

Reference numeral 9 denotes a field oxide film made of a LOCO8 oxide film, and on this field oxide film 9, polycrystalline oxides are formed which are paired with the p+ regions 8a, 8b, 8c, and 8d of polycrystalline silicon that constitute the electrodes, etc. Silicon n+ region 11a
111b, 11c.

11d is formed. These polycrystalline silicon p”
fJ regions 8a, 8b, 8C18d and n1 regions 11a, 1
The respective junctions with 1b, 11c, and 11d form respective diodes D1, D2, D3, and D4 for voltage boost control.

12 is PSGII! At the required positions of the PSG film 12,
Contact holes are formed by photoetching, and the diodes D1 to D4 are connected in series through an An wiring layer 13 to form portions corresponding to nodes 4a, 4b, and 4C in FIG. 2.

CV
The p+ regions 8a to 8d and n+ regions 11a to 11d, which are deposited by the D method, are simultaneously exposed to impurities during impurity diffusion into source and drain regions in the manufacturing process of other MOS ICs formed on the semiconductor substrate 5. is diffused and formed.

In this embodiment, the diodes D1 to D4 are formed from a polycrystalline silicon layer deposited on the main surface of the semiconductor substrate 5, and the boosting capacitors C1 to C3 are formed from a portion of this polycrystalline silicon layer. The booster circuit is formed using the p-wells 6a to 6c formed in the semiconductor substrate 5, and the booster circuit is integrated into one chip along with other MO8IC memories and the like.

Next, the action will be explained.

First, the first stage capacitor C1 is set to V due to the power supply voltage Vin.
Charged to in-Vbin. When the clock signal φ rises, the voltage of the linode 4a is boosted by the coupling of the capacitor C+, and at the same time, the conduction of the second stage diode D2 is controlled and the back voltage is transferred to the second stage capacitor C2.
is charged to.

Next, when the clock signal φ rises, the voltage at the node 4b is boosted, and at the same time, the third stage diode D3 is controlled to be conductive, and the back-pressure voltage is charged to the third stage capacitor C3.

In this way, the capacitors C1 to C3 in each stage are sequentially charged with the back-pressure voltage of the previous stage in a superimposed manner by the conduction control of the diodes 01 to 04, and the nodes 4a, 4b,
The potential of 4C rises, and the boosted voltage Vout boosted to a required voltage value is output from the output terminal 2.

The voltage vbSvC1 and the final boosted voltage Vout of each back-voltage node 4b, 4c ignore the reverse leakage current of each diode D1 to D4, and
Letting the built-in potential of 4 be Vbin, it is given by the following equation.

Vb=2・Vin-3・Vbin Vc=4・Vin-7・Vbin Vout=8-Vin-15-Vbin Therefore, in this embodiment, the boost loss is equal to the built-in potential Vbin of diodes D1 to D4. In minutes, this built-in potential Vbin is equal to that of a conventional diode-connected MOSF
A phenomenon such as an increase in the threshold voltage due to the substrate bias effect when ET is used does not exist, and the threshold voltage can be suppressed to a value lower than this threshold voltage. Furthermore, there is no loss caused by parasitic interference when a diode is externally attached. Therefore, boosting efficiency can be improved.

[Effects of the Invention] As explained above, according to the present invention, the diode for voltage boost control is formed by the pn junction of polycrystalline silicon deposited on the main surface of the semiconductor substrate, so it is not necessary to use the diode as in the conventional example. When built into a semiconductor substrate, leakage of charge into the substrate can be avoided, and diode-connected M
An increase in loss due to an increase in threshold voltage due to the body bias effect when using an OSFET is avoided, boosting efficiency is increased, and a required boosted voltage output can be obtained with a small number of boosting stages. Therefore, since the chip area can be reduced, there is an advantage that the chip cost can be reduced. Furthermore, since the number of boosting stages can be reduced, the boosting speed can be increased, which has the advantage of widening the range of applications, such as being able to be used as a voltage source for driving switching circuits such as power MOS transistors.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view showing an embodiment of a booster circuit according to the present invention, FIG. 2 is a circuit diagram showing a similar circuit of the same embodiment, and FIG.
FIG. 4 is a circuit diagram showing a conventional booster circuit, FIG. 4 is a signal waveform diagram showing a clock signal applied to the booster circuit, and FIG. 5 is a circuit diagram showing another conventional example. 1: Input terminal for power supply voltage, 2: Output terminal, 3a, 3b: Input terminal for clock signal (drive signal), 5: Semiconductor substrate, 88-8d: P+ regions 11a-11 of polycrystalline silicon
d: n+ region of polycrystalline silicon C1 to C3: capacitor, D1 to D4: diode.

Claims (1)

[Claims] A plurality of step-up capacitors arranged in parallel are formed on the main surface of a semiconductor substrate, and between one end of each capacitor, a voltage boost-controlled by an external drive signal is sequentially applied to the next stage capacitor. What is claimed is: 1. A booster circuit having a diode connected thereto, wherein the diode is formed by a pn junction of polycrystalline silicon deposited on the main surface of the semiconductor substrate.