JPS63306594A - Cmos integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the rise of substrate potential and the occurrence of latch-up phenomenon by supplying the substrate voltage from a second substrate voltage generation circuit at a transition time immediately after power source is supplied. CONSTITUTION:When the power source VCC is supplied to a C MOS DRAM, transient current Icj caused by junction capacitance Cj flows and the VBB of a (p) formed substrate 1 rises. When the VBB rises over the threshold voltage of a MOS transistor 25, the output of a first C MOS inverter becomes an 'L' level and the output of a second C MOS inverter becomes an 'H' level. As the result of that, a MOS transistor 28 becomes a conductive state. Therefore the VBB is short-circuited by VSS and returned to OV. Then the output of the first C MOS inverter becomes the 'H' level and tries to return the output of the second C MOS inverter to the 'L' level. But due to the discharge of capacitor 29, it takes long time that a node N1 returns to the level of the VSS. When the node N1 falls to the 'L' level and the MOS transistor 28 becomes in a non-conductive state, the VBB is set at the voltage of the first VBB generation circuit which already operates normally.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention includes a rounded substrate voltage generation circuit that keeps the substrate potential below a certain value immediately after power is turned on to prevent the occurrence of latch-up phenomenon. The present invention relates to integrated circuit devices.

[Conventional technology]

It is well known that various problems occur in integrated circuit devices during transient periods immediately after power is turned on, and the generation of excessive transient currents is of great importance.

Especially C! In the case of MO8 integrated circuit device, structurally,
pnp Ml and npn inside! Ef! The thyristor is generated parasitically and combines to form a pnpn type thyristor structure, so once this thyristor is turned on, an excessive current will flow between the power supply voltage (hereinafter referred to as VOO) and ground. This is even more important since it may lead to the so-called latch-up phenomenon, which may lead to leakage and destruction of the device. In integrated circuit devices, it is possible to prevent memory malfunction by injecting electrons into the substrate, increase the speed of circuits by reducing the pn junction capacitance, and increase the speed of operating circuits by reducing the substrate effect on the threshold voltage of transistors. In order to stabilize the circuit, a substrate voltage generation circuit (hereinafter referred to as the V1 generation circuit) is formed to apply a negative voltage to the substrate, but immediately after the power is turned on, this circuit is not yet operating normally. Therefore, the displacement current flowing through the capacitive coupling between Vaa and the substrate may trigger the parasitic thyristor, leading to a latch-up phenomenon.

Since the pn junction capacitance increases with higher integration of memory,
The V
Improvements in the BB generation circuit were required.

Figure 3 shows the conventional OMOS dynamic memory (hereinafter referred to as OMOS).
1 is a schematic diagram of the main part configuration of a MOS DRAM (referred to as MOS DRAM). In addition, in the figure, V! Although the IB generation circuit is shown as a circuit diagram outside the substrate, it is generally formed within the same substrate.

Figure 4 shows the latch-up phenomenon in the configuration shown in Figure 3 above! 5a is an equivalent circuit diagram for clarity.

In the figure, +11 is a pH 1 silicon semiconductor substrate (hereinafter referred to as pm substrate), (21) 1 n-well, (3)
is a p-type Draci region, (41 is a p-type Draci region, +5+
) n-type drain region, (61 is n-type source region, (7
) is an n-type substrate contact region, +81 is a p-type substrate contact region, +91 is another n-type substrate contact region (hereinafter all are referred to as regions (31 to [91)), the curve is a gate electrode, αυ is a capacitor electrode, In reality, each electrode Q(1, (lυ
Although there is an insulating film between the region 193 and the p-type substrate (11), it is omitted for simplicity. Note that a memory capacitor is formed between the region 193 and the capacitor electrode (11). u
A p-channel MOS transistor is formed by the gate electrode αa and the gate electrode αa in the n-well (2) and the regions 151 and 16 in the p-type substrate +11.
1 and the n-channel M formed by the gate electrode ul
OS) Run lister, I is the first VBB generation circuit formed near the main plane of the p-type substrate 111, and includes a ring oscillator (151, level shift circuit MOS transistor 1?) and rectification. for MO8
) The run lister C181 is composed of more than one. a9 is a power supply terminal (hereinafter referred to as Vaa terminal), ■ is a ground terminal (hereinafter referred to as Vss
), +21) is an input terminal (hereinafter referred to as IN terminal), ノ is an output terminal (hereinafter referred to as OUT terminal), and V! I
! 1 is a substrate voltage applied to the p-type substrate 111.

There are quite a number of diffusion regions in the semiconductor substrate where Voa is applied, such as the n-type regions (7) and (91) or the p-type region (3) shown in FIG. , A large junction capacitance Q caused by a pn junction inevitably exists between the Vao terminal (9) and the P-type substrate (1).

During normal operation of the CMOS DRAM configured as described above, the intermittent voltage oscillated by the ring oscillator QS is exchanged with a DC negative Vs+a for a second by the charging capacitor aQ and the LAoS transistor
It is supplied to the mold board +11.

[The problem that the invention attempts to solve]

In the conventional OMOS DRAM as described above, during the transition immediately after power-on, the VBB generation circuit I is not yet normally activated, and the p-type substrate (11 is electrically floating, and the junction capacitance Oj Because it is coupled to Voa through , a large transient current flows.

If this current f: xOj, it is expressed by the following equation.

IcJ＜, 0j−−v・・・・・・−song・−・song・song−
(Equation 1) That is, it can be seen that the transient current Icj becomes larger as the junction capacitance Oj becomes larger (the degree of integration of the memory is higher) and as the rise of Vao becomes steeper.

Immediately after the power is turned on, the transient current shown in equation 1 above is Vo.
When flowing between o and Vaa, a voltage drop occurs due to the resistance of the p-type substrate +11, and VBB increases to a positive value.

However, as shown by the dotted line in Figure 3, CMOS DRAM has a pnp vertical structure inside.
The transistor (TRv) and the npn-type lateral transistor (TR) are parasitic, and these two transistors (TRv) and (TRL) are combined to form the 'f' shown in the equivalent circuit diagram of Fig. 4. Since it has a pnpn type thyristor structure, now the transient current Icj
Flows through node A, first a voltage drop (1 arc·Rn) occurs in the resistor (R11) of the n-well (2) part, which exceeds the contact potential difference between the base and emitter of the transistor (TRv). And this transistor (TRv
) becomes conductive, and its collector current flows to the P-type substrate (1
) flows through the resistance (Rp). However, this resistance (Rp)
Similarly, when the voltage drop at the transistor (TR) becomes large, the collector current flows through the resistor (9), causing a voltage drop, and the transistor (TR) becomes conductive.
v) further becomes conductive.

In this way, the transistors (TRv) and (TRL) operate in a stable state while maintaining mutual conduction.
In other words, a latch-up phenomenon occurs in which an excessive current continues to flow through Voo-Via.

The present invention has been made to solve the problems of the conventional devices as described above, and an object of the present invention is to provide a CMOS integrated circuit device that can prevent the latch-up phenomenon from occurring when the power is turned on.

[Means for solving problems]

This invention provides a semiconductor substrate on which a CMOS memory is formed.
In a device in which the substrate voltage is applied from a substrate voltage generation circuit of ml, a second substrate voltage generation circuit is provided to supply the substrate voltage during a transient period immediately after power is turned on, and the substrate voltage can also be applied from this circuit. This is what I did.

[Effect]

In the cuos integrated circuit device according to the present invention, for a certain period of time immediately after the power is turned on, the substrate voltage from the $1 substrate voltage generation circuit is applied as well as the substrate voltage from the second substrate voltage generation circuit. Therefore, the semiconductor substrate does not have a high potential, and the latch-up phenomenon immediately after the power is turned on is prevented from occurring.

〔Example〕

FIG. 1 shows a CMO8DR in an embodiment of the present invention.
The second vBB generation circuit diagram of AM, FIG. 2, is a waveform diagram showing changes in voltage at each terminal and nodes No and Nl during operation.

In the figure, [Yes] indicates the second VB'B generation circuit formed near the main plane of the p-type substrate (11), and @ indicates the first amplifying p-type substrate (11).
channel MOS transistors, ■ is a first amplification n-channel MOS transistor, ■ is a second amplification P-channel MOS transistor, and is a second amplification n-channel transistor;
), (c), and (to) constitute first and second CMOS inverters, respectively. (c) is an n-channel MO8 transistor for substrate grounding, (2!lI is MO
A capacitor formed by an S-type capacitor, which allows MO
S) The non-conduction start time of the run lister ■ is determined.

The second Van generation circuit is formed together with the first vBB generation circuit I on the p-type substrate +11 on which the CMOS memory is formed, and is formed on the input side of the first CMOS inverter and ! , qOB The transistor side of the transistor 2 is connected to the p-type substrate 111, and Vaa is applied to the terminal wire, and Vas is applied to the terminal (2).

(31) to (39) in FIG. 2 correspond to each state in the operating waveform diagram.

OMOS DRAM KV configured as above
When oo is turned on, Voa first rises as shown in waveform (31). Then, the transient current I due to the junction capacitance Oj
cj flows and vBB of the p-type substrate +11 rises in the positive direction as shown by the waveform (32). However, v! When IB exceeds the threshold voltage of the 1 Jos transistor (to), the output of the first CMOS inverter (node No.)
becomes “L” level as shown in waveform (36), and the second
The output of the CMOS inverter (node N1) is waveform C3
As shown in 7'), it becomes "°H" level and the MOS
The run lister (28) becomes conductive. For this reason, Vi
+i is shorted to Via and O as shown in waveform (33)
It is pulled back to V.

Then, the output of the CMOS inverter of 9J1 (node N
o) Waveform (3B) As shown in K, the output of the second CMOS I>bark becomes °1H' level (node Nl)
I am trying to bring it back to the IIL11 level, but the capacity (total)
Due to the discharge of , VBB as shown in waveform (34)
maintains OV.

Node N1 drops to II L II ° level and MOS
When the transistor (c) becomes non-conductive, vBB is set to the voltage of the first VBB generating circuit I, which is operating normally, as shown in the waveform (35).

In the above embodiment, the first and second VB11 generation circuits are formed on the semiconductor substrate constituting the CMOS DRAM, but C! It may be formed in a MOS static type memory (CMOS SRAM), and although an example of an n-well type o LAos has been shown, it may be formed in a p-well type CMOS.

In addition, the first and 20th V@a generation circuits may be formed outside the semiconductor substrate, and it goes without saying that similar effects can be achieved.

〔Effect of the invention〕

As explained above, the present invention provides an OMO8 integrated circuit device that prevents a rise in substrate potential and does not cause latch-up by supplying substrate voltage from the second substrate voltage generation circuit during a transient period immediately after power is turned on. There are benefits to be gained.

[Brief explanation of drawings]

FIG. 1 is a diagram of a second substrate voltage generation circuit formed in an OMO8 integrated circuit device according to an embodiment of the present invention, FIG. 2 is its operating waveform diagram, and FIG. 3 is a diagram of a conventional first substrate voltage generation circuit. %4 is an equivalent circuit diagram for explaining the latch-up phenomenon in the configuration of %3. In the figure, (1) is a p-type silicon semiconductor substrate (p-type substrate>, a'a is a p-channel channel MO8) run lister, 0 is an n-channel channel MO8) lister, and I is a first substrate voltage generation circuit (first (Vow generation circuit), Q9 is a ring oscillator, μe is a capacitor for charge pump, αη is a LAOS transistor for level shift circuit, αa is MO for rectification
S transistor, 0 is the power supply terminal (Vcc terminal), @ is the ground terminal (Va8 terminal), and ノ is the second substrate voltage generation circuit (
20th VIIB generation circuit), (241 is the first amplification p-channel IJiOS transistor, 2 is the first amplification n-channel M08 transistor) ■ is the second amplification p-channel MO8) run lister, ■ is the amplification n-channel MO8) Run lister, (c) is an n-channel MoS transistor for substrate installation, and (to) is the capacitance. In addition, the same symbols in each figure indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a CMOS integrated circuit device in which a substrate voltage is applied from a first substrate voltage generation circuit to a semiconductor substrate constituting a CMOS memory, a second substrate voltage generation circuit applies the substrate voltage during a transient period immediately after power is turned on. A CMOS integrated circuit device characterized by being provided with a circuit. (2) The second substrate voltage generation circuit includes a CMOS inverter that receives the substrate voltage as its input, a MOS transistor that uses the output of the CMOS inverter as its gate input and biases between the semiconductor substrate and the ground terminal, and the MOS transistor. 2. The CMOS integrated circuit device according to claim 1, further comprising a capacitor for determining a non-conduction start time of the CMOS integrated circuit device.