JP3190501B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device capable of guaranteeing a substrate region voltage of an internal transistor.

[0002]

2. Description of the Related Art In a MOS type semiconductor integrated circuit device, a CMOS circuit is often used as an output circuit. In a semiconductor integrated circuit device provided with a substrate voltage generating circuit typified by a dynamic type storage device, an NMOS type output circuit is used. Often a circuit was used. However, in recent years, CMOS output circuits have been used as output circuits in order to increase the speed and reduce the power consumption of semiconductor integrated circuits.

FIG. 15 shows an example of an output circuit of a conventional semiconductor integrated circuit device, where 1 is a P-type MOS transistor,
2 is an N-type MOS transistor, 4 and 5 are output control signals,
6 is an output terminal. Power supply voltage Vcc is often connected to the substrate region of P-type MOS transistor 1.
In addition, the semiconductor integrated circuit device partially includes a boosted power supply circuit, and a boosted voltage Vps generated inside the semiconductor integrated circuit device.
(Generally, a voltage higher than the power supply voltage Vcc) has been proposed. (IEE Journal of Solid Circuit 23-3 (198
In the circuit of the conventional example, when the output control signal 4 and the output control signal 5 are set to high level and high level, or low level and low level, or high level and low level, respectively. , A low level or a high level or a high impedance state is obtained at the output terminal 6.

[0004]

In the conventional semiconductor integrated circuit device, the output terminal 6 of the CMOS output circuit is connected to
A voltage exceeding the voltage Vps + Vbi obtained by adding the substrate region voltage Vps of the P-type MOS transistor 1 and the built-in voltage Vbi of the PN junction of the drain (P-type region) and the substrate region (N-type region) of the P-type MOS transistor 1 is supplied from outside the circuit. When the voltage is applied, a forward current flows from the drain region (P-type region) of the P-type MOS transistor 1 to the substrate region (N-type region) of the P-type MOS transistor 1, and part of the current flows into the substrate (P
(Type region), the parasitic bipolar transistor is turned on, causing a large current to flow from the drain region to the substrate, thereby increasing the substrate voltage.

On the other hand, in a configuration in which the substrate region of the P-type MOS transistor 1 is set to a voltage higher than the power supply voltage Vcc by the boosting power supply circuit, the boosting power supply circuit is not activated simultaneously when the power is turned on. It takes time for the substrate region voltage of the P-type MOS transistor 1 to rise to Vps.
When a voltage exceeding the voltage Vps + Vbi obtained by adding the built-in voltage Vbi of the PN junction of the drain (P-type region) and the substrate region (N-type region) of the P-type MOS transistor 1 is applied from the outside of the circuit, There is a problem that a forward current flows from the drain region (P-type region) of the P-type MOS transistor 1 to the substrate region (N-type region), causing a phenomenon that a large current flows from the drain region to the substrate as described above. .

Further, in a configuration in which the substrate region of the P-type MOS transistor 1 is set to a voltage higher than the power supply voltage Vcc by the boosted power supply circuit, the boosted power supply circuit is not activated simultaneously when the power is turned on. It takes time for the substrate region voltage of the P-type MOS transistor 1 to rise to Vps, and when Vcc−Vbi> Vps, the P-type MOS
There is a problem that a forward current flows from the source region (P-type region) of the transistor 1 to the substrate region (N-type region), causing a phenomenon that a large current flows from the source region to the substrate as described above.

An object of the present invention is to provide a semiconductor integrated circuit device capable of preventing a large current from flowing into a substrate.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having a first MO connected to a constant voltage source.
An S transistor, a second MOS transistor having a source connected to the ground potential and a drain connected to the drain of the first MOS transistor, the second MOS transistor having a polarity opposite to that of the first MOS transistor, and a gate and a drain connected to the first MOS transistor; An output circuit having a first MOS transistor connected to the drain and having a source connected to the substrate region of the first MOS transistor, and a third MOS transistor having a polarity opposite to that of the first MOS transistor; Value voltage is
It is characterized in that it has a structure lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit and lower than the built-in voltage of the PN junction of the drain / substrate region of the first MOS transistor.

According to a second aspect of the present invention, in the semiconductor integrated circuit device of the first aspect, the substrate region of the first MOS transistor is connected to a boosting power supply circuit provided therein. 4. The semiconductor integrated circuit device according to claim 3, wherein the first MOS transistor has a source connected to a constant voltage source, and the first MOS transistor has a source connected to the ground potential and a drain connected to the drain of the first MOS transistor. A second MOS transistor having a polarity opposite to that of the transistor, a third MOS transistor having a gate and a drain connected to a constant voltage source, and a source connected to a substrate region of the first MOS transistor and having a polarity opposite to that of the first MOS transistor Wherein the threshold voltage of the third MOS transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit.

According to a fourth aspect of the present invention, a first MOS transistor having a source connected to a constant voltage source, a source connected to a ground potential, and a drain connected to a first MOS transistor.
A second MOS transistor having a polarity opposite to that of the first MOS transistor connected to the source of the S transistor; a gate and a drain connected to the drain of the first MOS transistor; and a source connected to the substrate region of the first MOS transistor Third M transistor having a polarity opposite to that of the first MOS transistor
An OS transistor, a fourth transistor having a gate and a drain connected to a constant voltage source, and a source connected to a substrate region of the first MOS transistor and having a polarity opposite to that of the first MOS transistor;
An output circuit including an OS transistor, wherein the threshold voltage of the third and fourth MOS transistors is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit; The third MOS transistor has a structure in which the threshold voltage is lower than the built-in voltage of the PN junction in the drain / substrate region of the first MOS transistor.

According to a fifth aspect of the present invention, a first MOS transistor having a source connected to a constant voltage source, a source connected to a ground potential, and a drain connected to a first MOS transistor.
A second MOS transistor having a polarity opposite to that of the first MOS transistor connected to the source of the S transistor; a third MOS transistor having a polarity opposite to that of the first MOS transistor having a gate and a drain connected to the drain of the first MOS transistor;
The S transistor and the gate are connected to the drain of the first MOS transistor, the drain is connected to the source of the third MOS transistor, and the source is opposite to the first MOS transistor whose source is connected to the substrate region of the first MOS transistor. An output circuit including a fourth MOS transistor having a polarity, wherein the threshold voltage of the third and fourth MOS transistors is higher than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit. Low and third MO
The voltage obtained by adding the threshold voltage of the S transistor and the threshold voltage of the fourth MOS transistor is lower than the built-in voltage of the PN junction in the drain / substrate region of the first MOS transistor. I do.

A semiconductor integrated circuit device according to a sixth aspect of the present invention is the semiconductor integrated circuit device according to the fifth aspect, wherein the first MO
The substrate region of the S transistor is connected to a boosting power supply circuit provided therein. The semiconductor integrated circuit device according to claim 7, wherein the source is connected to the constant voltage source.
An S transistor and a first transistor having a source connected to the ground potential and a drain connected to the source of the first MOS transistor.
A second MOS transistor having a polarity opposite to that of the first MOS transistor, a third MOS transistor having a gate and a drain connected to the drain of the first MOS transistor and a polarity opposite to the first MOS transistor, and a gate connected to the first MOS transistor.
A first MOS transistor connected to the drain of the S transistor, the drain connected to the source of the third MOS transistor, and the source connected to the substrate region of the first MOS transistor
A fourth MOS transistor having a polarity opposite to that of the transistor;
A first MOS transistor having a gate and a drain connected to a constant voltage source and a source connected to a substrate region of the first MOS transistor;
An output circuit comprising a transistor and a fifth MOS transistor having a reverse polarity;
The threshold voltage of the transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit, and the threshold voltage of the third MOS transistor and the threshold voltage of the fourth MOS transistor And a voltage which is lower than the built-in voltage of the PN junction in the drain / substrate region of the first MOS transistor.

In the semiconductor integrated circuit device according to the present invention, a first MOS transistor having a source connected to a constant voltage source, a booster having a source connected to a drain of the first MOS transistor, and a substrate region provided therein. A second MOS transistor connected to the power supply circuit; a third transistor having a source connected to the ground potential and a drain connected to the drain of the second MOS transistor;
And an output circuit having an OS transistor.
The second MO is controlled by the control signal of the gate of the OS transistor.
The source voltage of the S transistor is controlled.

According to a ninth aspect of the present invention, in the semiconductor integrated circuit device according to the eighth aspect, the source is connected to the substrate region of the second MOS transistor, and the gate and the drain are connected to the drain of the second MOS transistor. Fourth MOS transistor having the opposite polarity to the second MOS transistor connected to
Transistor, and the threshold voltage of the fourth MOS transistor is the same as that of another MO transistor used for the internal function circuit.
It is characterized by being lower than the threshold voltage of the S transistor and lower than the built-in voltage of the PN junction in the drain / substrate region of the second MOS transistor.

A semiconductor integrated circuit device according to claim 10 is
9. The semiconductor integrated circuit device according to claim 8, wherein a source is connected to a substrate region of the second MOS transistor, and a fourth MOS transistor having a polarity opposite to that of the second MOS transistor having a gate and a drain connected to a constant voltage source. Prepared, fourth
Is characterized in that the threshold voltage of the MOS transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit.

A semiconductor integrated circuit device according to claim 11 is
9. The semiconductor integrated circuit device according to claim 8, wherein the source is connected to the substrate region of the second MOS transistor, and the gate and the drain are connected to the fourth MOS transistor having a polarity opposite to that of the second MOS transistor. MO
A fifth transistor having an S transistor and a source connected to the substrate region of the second MOS transistor and having a gate and a drain connected to a constant voltage source and having a polarity opposite to that of the second MOS transistor;
An S transistor, wherein the threshold voltage of the fourth and fifth MOS transistors is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit, and When the threshold voltage is P in the drain / substrate region of the second MOS transistor
It is characterized by being lower than the built-in voltage of the N junction.

A semiconductor integrated circuit device according to claim 12 is
9. The semiconductor integrated circuit device according to claim 8, wherein a fourth MOS transistor having a gate and a drain connected to the drain of the second MOS transistor has a polarity opposite to that of the second MOS transistor.
The transistor and the gate are connected to the drain of the second MOS transistor, the drain is connected to the source of the fourth MOS transistor, and the source is opposite in polarity to the second MOS transistor connected to the substrate region of the second MOS transistor. A fourth MOS transistor, wherein the threshold voltages of the fourth and fifth MOS transistors are lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit, and the fourth MOS transistor A structure in which a voltage obtained by adding the threshold voltage of the transistor and the threshold voltage of the fifth MOS transistor is lower than the built-in voltage of the PN junction in the drain / substrate region of the second MOS transistor. .

A semiconductor integrated circuit device according to claim 13 is
9. The semiconductor integrated circuit device according to claim 8, wherein a fourth MOS transistor having a gate and a drain connected to the drain of the second MOS transistor has a polarity opposite to that of the second MOS transistor.
The transistor and the gate are connected to the drain of the second MOS transistor, the drain is connected to the source of the fourth MOS transistor, and the source is opposite in polarity to the second MOS transistor connected to the substrate region of the second MOS transistor. A fifth MOS transistor having a gate and a drain connected to a constant voltage source and a source connected to a substrate region of the second MOS transistor, and a sixth MOS transistor having a polarity opposite to that of the second MOS transistor; 4th, 5th
And the threshold voltage of the sixth MOS transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit, and the threshold voltage of the fourth MOS transistor and the fifth MOS transistor And the threshold voltage of the second MOS transistor is lower than the built-in voltage of the PN junction in the drain / substrate region of the second MOS transistor.

[0019]

According to the structure of the first aspect, since the third MOS transistor is provided, the substrate region voltage and the drain (P) of the first MOS transistor are supplied to the output terminal provided at the drain of the first MOS transistor. When a voltage exceeding the built-in voltage of the PN junction in the substrate region (N-type region) and the substrate region (N-type region) is applied from outside the circuit, the substrate region voltage of the first MOS transistor is increased, and the drain (P The generation of a forward current from the mold region) to the substrate region (N-type region) is prevented. That is, the voltage obtained by adding the substrate region voltage of the first MOS transistor and the built-in voltage of the PN junction of the drain (P-type region) and the substrate region (N-type region) to the output terminal provided at the drain of the first MOS transistor. If a voltage exceeding the circuit is applied from outside the circuit, the first
Before a forward current flows from the drain region of the MOS transistor to the substrate region, the third MOS transistor is turned on, and the voltage of the first MOS transistor is increased through the third MOS transistor in order to increase the substrate region voltage. 1
Current flows in the substrate region of the MOS transistor of FIG.
When a part of the current reaches the substrate (P-type region), a parasitic bipolar transistor is turned on, and a large current flows from the drain region to the substrate, thereby preventing the substrate voltage from increasing. .

According to the configuration of the second aspect, the first MO
By providing the booster power supply circuit for setting the substrate region voltage of the S transistor higher than the power supply voltage and the third MOS transistor, the withstand voltage with respect to the voltage applied to the output terminal provided at the drain of the first MOS transistor is higher than that of the conventional semiconductor. Improved over integrated circuit devices. According to the configuration of the third aspect, by providing the third MOS transistor,
When the power is turned on, the rise of the substrate region voltage of the first MOS transistor is accelerated. In other words, the first
When the substrate region voltage of the MOS transistor exceeds the threshold voltage of the third MOS transistor, the third MOS transistor is turned on and operates to keep the substrate region voltage of the first MOS transistor at a predetermined value. 3, the time from when the power is turned on to a predetermined value can be shortened, and the first M from the time when the power is turned on to when the boost power supply circuit operates can be reduced.
Since the substrate region voltage of the OS transistor can be made higher than that of the conventional semiconductor integrated circuit device, the first MO
Current injection from the output terminal provided at the drain of the S transistor to the substrate region of the first MOS transistor can be prevented.

According to the configuration of the fourth aspect, the operation of the second and third aspects is provided. According to the configuration of claim 5, when a negative voltage is applied to the output terminal provided at the drain of the first MOS transistor from the outside of the circuit, the leakage current from the source to the drain of the first MOS transistor is: It is less than the configuration according to claim 1.

According to the configuration of the sixth aspect, the first MO
3. A leakage current from the source to the drain of the first MOS transistor when a negative voltage is applied to the output terminal provided at the drain of the S transistor from outside the circuit.
Less than the described configuration. According to the configuration of claim 7, when a negative voltage is applied to the output terminal provided at the drain of the first MOS transistor from the outside of the circuit, the leakage current from the source to the drain of the first MOS transistor is: It is less than the configuration according to claim 4.

According to the configuration of claim 8, when the power is turned on, a forward current flows from the source region of the second MOS transistor to the substrate region, and a large current flows from the source region of the second MOS transistor to the substrate. This phenomenon is prevented. According to the configuration of the ninth aspect, the operation according to the configurations of the second and eighth aspects is provided.

According to the tenth aspect, the third aspect is provided.
And the operation according to the eighth aspect. Claim 11
According to the configuration described above, the operation according to the fourth and eighth aspects is provided. According to the structure of the twelfth aspect, the operation according to the structure of the sixth and eighth aspects is provided.

[0025] According to the structure of claim 13, according to claim 7,
And the operation according to the eighth aspect.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention. Similar to the conventional example, a P-type MOS transistor 1 and an N-type MOS transistor are provided. The power supply voltage Vcc is supplied to the substrate region of the P-type MOS transistor 1 of the CMOS output circuit constituted by the type MOS transistor 2. Further, in the substrate region of the P-type MOS transistor 1, a gate and a drain
The threshold voltage connected to the output terminal 6 of the S output circuit is P
The built-in voltage Vbi of the PN junction in the drain / substrate region of the type MOS transistor 1 and the source of the N-type MOS transistor 3 lower than the threshold voltage of another N-type MOS transistor used for the internal function circuit are connected. The threshold voltage of the N-type MOS transistor 3 is Vt1
And

The output terminal 6 of the CMOS output circuit has a P-type M
Substrate area voltage Vps (= Vcc) of OS transistor 1
And PN of drain (P-type region) and substrate region (N-type region)
Voltage Vcc + Vb obtained by adding built-in voltage Vbi of junction
When a voltage exceeding i is applied from outside the circuit, the P-type MO
Before a forward current flows from the drain of the S transistor 1 to the substrate region, the N-type MOS transistor 3 is turned on, and
A current flows from the output terminal 6 of the MOS output circuit to the substrate region of the P-type MOS transistor 1 via the N-type MOS transistor 3, and the substrate region voltage of the P-type MOS transistor 1 is raised to Vcc + Vbi-Vt1. as a result,
The potential difference between the drain of the P-type MOS transistor 1 and the substrate region becomes Vt1 (<Vbi), so that current injection from the drain to the substrate region can be prevented, and the phenomenon of increasing the substrate voltage can be prevented.

[Second Embodiment: Corresponding to Claim 2] FIG. 2 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention, wherein a P-type MOS transistor 1, an N-type M
The configurations of the OS transistor 2 and the N-type MOS transistor 3 are the same as those of the first embodiment. The boost power supply circuit 7 inside the semiconductor integrated circuit device is provided in the substrate region of the P-type MOS transistor 1 in the circuit diagram of FIG. Power supply voltage Vcc generated at
A higher boosted voltage Vps is supplied.

Since the booster power supply circuit 7 for setting the substrate region voltage of the P-type MOS transistor 1 to a voltage Vps higher than the power supply voltage Vcc and the N-type MOS transistor 3 having a low threshold voltage are provided, the output is increased. When the voltage applied to the terminal 6 exceeds Vps + Vt1 (<Vps + Vbi), the N-type MOS transistor 3 turns on and the P-type MOS
To raise the substrate region voltage of the transistor 1, CM
The withstand voltage of the OS output circuit against an externally applied voltage is improved as compared with the conventional semiconductor integrated circuit device.

[Third Embodiment: Corresponding to Claim 3] FIG. 3 is a circuit diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention.
The structure of the MOS transistor 2 is the same as that of the first embodiment, and the substrate region of the P-type MOS transistor 1 has a boosted voltage Vps (from the power supply voltage Vcc) generated from the boosted power supply circuit 7 inside the semiconductor integrated circuit device. High voltage). Further, in the substrate region of the P-type MOS transistor 1, an N-type MOS transistor 8 having a gate and a drain connected to a constant voltage source of the power supply voltage Vcc and having a low threshold voltage like the N-type MOS transistor 3 described above. Source is connected.

FIG. 4 shows the power supply voltage at power-on and the P-type MO.
9 is a diagram showing a change in the substrate region voltage of the S transistor 1, wherein 9 is a power supply voltage, and 10 is an N-type MO having a low threshold voltage.
The substrate region voltage of the P-type MOS transistor 1 when the S transistor 8 is used, and 11 is the substrate region voltage of the P-type MOS transistor 1 when the normal N-type MOS transistor 8 is used.

When the power supply is turned on, if the power supply voltage becomes higher than the substrate region voltage of P-type MOS transistor 1 by Vt1 or more, current flows through N-type MOS transistor 8 to the substrate region of P-type MOS transistor 1, and N-type By lowering the threshold voltage of MOS transistor 8, the rise time of the substrate region voltage of P-type MOS transistor 1 can be shortened.

[Fourth Embodiment; Corresponding to Claim 4] FIG. 5 is a circuit diagram showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
The structure of the MOS transistor 2 is the same as that of the first embodiment, and a boosted voltage Vps higher than the power supply voltage Vcc generated by the boosted power supply circuit 7 inside the semiconductor integrated circuit device is applied to the substrate region of the P-type MOS transistor 1. Supplied, N
The configuration is such that the second embodiment and the third embodiment are simultaneously implemented by the type MOS transistor 3 and the N type MOS transistor 8.

According to the structure of this embodiment, the output terminal 6 of the CMOS output is provided in the same manner as in the second and third embodiments.
When the voltage of Vpp + Vbi is applied from outside the circuit, and when the power is turned on, the substrate region voltage of the P-type MOS transistor 1 can be guaranteed. [Fifth Embodiment; Corresponding to Claim 5] FIG. 6 is a circuit diagram showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention. An N-type MOS transistor 12 having a gate connected to the output terminal 6 is connected between the substrate region and the N-type MOS transistor 3, and the threshold voltage of the N-type MOS transistor 3 and the N-type MOS transistor 12 Is lower than the threshold voltage of another N-type MOS transistor used for the internal function circuit, and the voltage obtained by adding the threshold voltage of the N-type MOS transistor 3 and the threshold voltage of the N-type MOS transistor 12 is P Drain of the MOS transistor 1
It is lower than the built-in voltage Vbi of the PN junction in the substrate region.

In the circuit of the first embodiment, when a negative voltage is applied to the output terminal 6 from outside the circuit, the operation is the same as when a positive substrate bias is applied to the N-type MOS transistor 3, and the N-type MOS transistor 3 A leakage current flows from the source of the transistor 3 to the drain thereof, the substrate region voltage of the P-type MOS transistor 1 decreases, and a forward current easily flows from the source of the P-type MOS transistor 1 to the substrate region.

According to the structure of this embodiment, the potential difference between the output terminal 6 and the substrate region of the P-type MOS transistor 1 is reduced to N-type M-type.
OS transistor 3 and N-type MOS transistor 12
In the case where a leak occurs between the source and the drain of the N-type MOS transistor 3, the source voltage of the N-type MOS transistor 12 is increased to prevent the leak current of the N-type MOS transistor 12 In addition, the leakage current from the output terminal 6 to the substrate region of the P-type MOS transistor 1 can be reduced to prevent the above phenomenon.

[Sixth Embodiment; Corresponding to Claim 6] FIG. 7 is a circuit diagram showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. Between the substrate region of the transistor 1 and the N-type MOS transistor 3,
An N-type MOS transistor 12 having a gate connected to the output terminal 6 is connected, and the threshold voltages of the N-type MOS transistor 3 and the N-type MOS transistor 12 are used for other N-type MOS transistors used in the internal function circuit. Is lower than the threshold voltage of the P-type MOS transistor 1 and the sum of the threshold voltage of the N-type MOS transistor 3 and the threshold voltage of the N-type MOS transistor 12
Built-in voltage Vb of PN junction in drain / substrate region
lower than i.

According to the structure of this embodiment, the leakage current from the source to the drain when a negative voltage is applied to the output terminal 6 from the outside of the circuit, as in the case of the fifth embodiment,
It can be reduced compared to the second embodiment. [Seventh Embodiment; Corresponding to Claim 7] FIG. 8 is a circuit diagram showing a semiconductor integrated circuit device according to a seventh embodiment of the present invention. An N-type MOS transistor 12 having a gate connected to the output terminal 6 is connected between the substrate region and the N-type MOS transistor 3. The N-type MOS transistor 3, the N-type MOS transistor 8, and the N-type MOS transistor 1
Other N-type MOs whose threshold voltage is 2
Lower than the threshold voltage of the S transistor and N-type M
The sum of the threshold voltage of the OS transistor 3 and the threshold voltage of the N-type MOS transistor 12 is a P-type MOS transistor.
The threshold voltage of the N-type MOS transistor 8 is lower than the built-in voltage Vbi of the PN junction in the drain-substrate region of the transistor 1 and the built-in voltage Vbi of the PN junction in the drain-substrate region of the P-type MOS transistor 1
Lower than.

According to the structure of this embodiment, the leak current from the source to the drain when a negative voltage is applied to the output terminal 6 from the outside of the circuit, as in the fifth embodiment,
It can be reduced compared to the fourth embodiment. [Eighth Embodiment: Corresponding to Claim 8] FIG. 9 is a circuit diagram of an eighth embodiment of the present invention, which comprises a P-type MOS transistor 1 and an N-type MOS transistor 2 as in the conventional example. A P-type MOS transistor 13 whose substrate region is connected to a constant voltage source is connected between the P-type MOS transistor 1 of the CMOS output circuit and the constant voltage source of the power supply voltage Vcc. Control signal 14 controls the gate voltage of the P-type MOS transistor 13. Further, a boosted voltage Vps higher than the power supply voltage Vcc generated by the boosted power supply circuit 7 inside the semiconductor integrated circuit device is supplied to the substrate region of the P-type MOS transistor 1.

In the configuration of this embodiment, the P-type MOS transistor 13 is turned off by the control signal 14 until the substrate region voltage of the P-type MOS transistor 1 rises to at least Vcc-Vbi from the time of power-on. No voltage is applied to the source of the MOS transistor 1, a forward current flows from the source region (P-type region) of the P-type MOS transistor 1 to the substrate region (N-type region), and a large current flows from the source region to the substrate. The phenomenon can be prevented.

[Ninth Embodiment: Corresponding to Claim 9] FIG. 10 is a circuit diagram of a ninth embodiment of the present invention.
P-type MOS transistor 1 and power supply voltage Vcc
And a P-type MOS transistor 13 whose substrate region is connected to a constant voltage source.
According to the configuration of this embodiment, the phenomenon that a large current flows from the source region to the substrate when the power is turned on in the second embodiment can be prevented as in the eighth embodiment.

[Tenth Embodiment: Corresponding to Claim 10] FIG. 11 is a circuit diagram of a tenth embodiment of the present invention. The P-type MOS transistor 1 and the power supply voltage Vcc of the third embodiment are shown in FIG. And a P-type MOS transistor 13 whose substrate region is connected to a constant voltage source. According to the configuration of this embodiment, the phenomenon that a large current flows from the source region to the substrate when the power is turned on in the third embodiment can be prevented as in the eighth embodiment.

[Eleventh Embodiment; Corresponding to Claim 11] FIG. 12 is a circuit diagram of an eleventh embodiment of the present invention, in which a P-type MOS transistor 1 and a power supply voltage Vcc of a fourth embodiment are shown. And a P-type MOS transistor 13 whose substrate region is connected to a constant voltage source. According to the configuration of this embodiment, the phenomenon that a large current flows from the source region to the substrate when the power is turned on in the fourth embodiment can be prevented as in the eighth embodiment.

FIG. 13 is a circuit diagram of a twelfth embodiment of the present invention, in which a P-type MOS transistor 1 and a power supply voltage Vcc of a sixth embodiment are shown. And a P-type MOS transistor 13 whose substrate region is connected to a constant voltage source. According to the configuration of this embodiment, the phenomenon that a large current flows from the source region to the substrate when the power is turned on in the sixth embodiment can be prevented as in the eighth embodiment.

FIG. 14 is a circuit diagram of a thirteenth embodiment of the present invention, in which a P-type MOS transistor 1 and a power supply voltage Vcc of a seventh embodiment are shown. And a P-type MOS transistor 13 whose substrate region is connected to a constant voltage source. According to the configuration of this embodiment, the phenomenon that a large current flows from the source region to the substrate when the power is turned on in the seventh embodiment can be prevented as in the eighth embodiment.

[0046]

According to the semiconductor integrated circuit device of the first aspect, since the third MOS transistor is provided,
When a voltage exceeding the sum of the substrate region voltage of the first MOS transistor and the built-in voltage of the PN junction of the drain / substrate region is applied to the output terminal provided at the drain of the first MOS transistor from outside the circuit, MO of 1
By increasing the substrate region voltage of the S transistor, the generation of a forward current from the drain region to the substrate region can be prevented.

According to the semiconductor integrated circuit device of the second aspect, the booster power supply circuit for setting the substrate region voltage of the first MOS transistor higher than the power supply voltage and the third MOS transistor are provided. The breakdown voltage with respect to the voltage applied to the output terminal provided at the drain of the MOS transistor is improved as compared with the conventional semiconductor integrated circuit device. Claim 3
According to the semiconductor integrated circuit device described above, since the third MOS transistor is provided, the first MO at power-on is provided.
The rise of the substrate region voltage of the S transistor can be accelerated.

According to the semiconductor integrated circuit device of the fourth aspect, the effects of the semiconductor integrated circuit devices of the second and third aspects can be simultaneously obtained. According to the semiconductor integrated circuit device of the fifth aspect, leakage from the source to the drain of the first MOS transistor when a negative voltage is applied to the output terminal provided at the drain of the first MOS transistor from outside the circuit. The current can be reduced as compared with the semiconductor integrated circuit device according to the first aspect.

According to the semiconductor integrated circuit device of the sixth aspect, when a negative voltage is applied to the output terminal provided at the drain of the first MOS transistor from outside the circuit, the source to the drain of the first MOS transistor Leakage current to the semiconductor integrated circuit device can be reduced. According to the semiconductor integrated circuit device of the seventh aspect, the first
The leak current from the source to the drain of the first MOS transistor when a negative voltage is applied to the output terminal provided at the drain of the MOS transistor from outside the circuit can be reduced as compared with the semiconductor integrated circuit device according to claim 4. .

According to the semiconductor integrated circuit device of the present invention, when the power is turned on, a forward current flows from the source region of the second MOS transistor to the substrate region, and a large current flows from the source region of the second MOS transistor to the substrate. The phenomenon that current flows can be prevented. According to the semiconductor integrated circuit device of the ninth aspect, the effects of the semiconductor integrated circuit devices of the second and eighth aspects can be simultaneously obtained.

According to the semiconductor integrated circuit device of the tenth aspect, the effects of the semiconductor integrated circuit devices of the third and eighth aspects can be simultaneously obtained. According to the semiconductor integrated circuit device of the eleventh aspect, the effects of the semiconductor integrated circuit devices of the fourth and eighth aspects can be simultaneously obtained. According to the semiconductor integrated circuit device of the twelfth aspect, the effects of the semiconductor integrated circuit devices of the sixth and eighth aspects can be simultaneously obtained.

According to the semiconductor integrated circuit device of the thirteenth aspect, the effects of the semiconductor integrated circuit devices of the seventh and eighth aspects can be simultaneously obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing changes in the power supply and the substrate region voltage of the P-type MOS transistor when the power is turned on.

FIG. 5 is a circuit diagram of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram of a semiconductor integrated circuit device according to a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram of a semiconductor integrated circuit device according to a tenth embodiment of the present invention.

FIG. 12 is a circuit diagram of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 13 is a circuit diagram of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 14 is a circuit diagram of a semiconductor integrated circuit device according to a thirteenth embodiment of the present invention.

FIG. 15 is a circuit diagram of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 Reference Signs List 1 P-type MOS transistor 2 N-type MOS transistor 3 N-type MOS transistor 4 Output control signal of CMOS output circuit 5 Output control signal of CMOS output circuit 6 Output terminal of CMOS inverter circuit 7 Boost power supply circuit 8 N-type MOS transistor 12 N-type MOS transistor 13 P-type MOS transistor 14 Control signal

Claims (13)

(57) [Claims] 1. A first MO having a source connected to a constant voltage source.
An S transistor, a source connected to the ground potential, and a drain connected to the first MO.
The first MOS connected to the drain of the S transistor;
A second MOS transistor having a polarity opposite to that of the transistor, a gate and a drain connected to the drain of the first MOS transistor, and a source connected to the substrate region of the first MOS transistor, opposite to the first MOS transistor. An output circuit comprising a third MOS transistor having a polarity, wherein a threshold voltage of the third MOS transistor is lower than a threshold voltage of another MOS transistor of the same polarity used for the internal function circuit. A semiconductor integrated circuit device having a structure lower than a built-in voltage of a PN junction in a drain / substrate region of the first MOS transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein the substrate region of the first MOS transistor is connected to a boosting power supply circuit provided inside. 3. A first MO having a source connected to a constant voltage source.
An S transistor, a source connected to the ground potential, and a drain connected to the first MO.
The first MOS connected to the drain of the S transistor;
A second MOS transistor having a polarity opposite to that of the transistor, a third gate having a gate and a drain connected to the constant voltage source, and a source connected to a substrate region of the first MOS transistor, the third MOS transistor having a polarity opposite to that of the first MOS transistor; And a third MOS transistor having a structure in which the threshold voltage of the third MOS transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit. A semiconductor integrated circuit device characterized by the above-mentioned. 4. A first MO having a source connected to a constant voltage source.
An S transistor, a source connected to the ground potential, and a drain connected to the first MO.
A second MOS transistor having a polarity opposite to that of the first MOS transistor connected to the source of the S transistor; a gate and a drain connected to the drain of the first MOS transistor; and a source connected to the substrate of the first MOS transistor. A third MOS transistor having a polarity opposite to that of the first MOS transistor connected to a region, a gate and a drain connected to the constant voltage source, and a source connected to a substrate region of the first MOS transistor; And an output circuit including a fourth MOS transistor having a reverse polarity, and a threshold voltage of the third and fourth MOS transistors being equal to that of another MOS transistor of the same polarity used for an internal function circuit. Lower than the threshold voltage and the third MO
A semiconductor integrated circuit device having a structure in which a threshold voltage of an S transistor is lower than a built-in voltage of a PN junction in a drain-substrate region of the first MOS transistor. 5. A first MO having a source connected to a constant voltage source.
An S transistor, a source connected to the ground potential, and a drain connected to the first MO.
A second MOS transistor having a polarity opposite to that of the first MOS transistor connected to the source of the S transistor; a second MOS transistor having a gate and a drain connected to the drain of the first MOS transistor; And a third MOS transistor having a gate connected to a drain of the first MOS transistor, a drain connected to a source of the third MOS transistor, and a source connected to a substrate region of the first MOS transistor. An output circuit comprising one MOS transistor and a fourth MOS transistor having a reverse polarity, wherein the threshold voltages of the third and fourth MOS transistors have the same polarity and are used for an internal function circuit. Is lower than the threshold voltage of the third MO
The sum of the threshold voltage of the S transistor and the threshold voltage of the fourth MOS transistor is equal to the first M
A semiconductor integrated circuit device having a structure lower than a built-in voltage of a PN junction in a drain / substrate region of an OS transistor. 6. The semiconductor integrated circuit device according to claim 5, wherein the substrate region of the first MOS transistor is connected to a boosting power supply circuit provided inside. 7. A first MO having a source connected to a constant voltage source.
An S transistor, a source connected to the ground potential, and a drain connected to the first MO.
A second MOS transistor having a polarity opposite to that of the first MOS transistor connected to the source of the S transistor; a second MOS transistor having a gate and a drain connected to the drain of the first MOS transistor; And a third MOS transistor having a gate connected to a drain of the first MOS transistor, a drain connected to a source of the third MOS transistor, and a source connected to a substrate region of the first MOS transistor. A fourth MOS transistor having a polarity opposite to that of the first MOS transistor, a gate and a drain connected to the constant voltage source, and a source connected to the substrate region of the first MOS transistor, the polarity being opposite to that of the first MOS transistor. And an output circuit having a fifth MOS transistor of the third, fourth and fourth MOS transistors. And another MOS transistor having the same polarity as the threshold voltage of the fifth MOS transistor used for the internal function circuit.
Lower than the threshold voltage of the transistor;
Threshold voltage of the MOS transistor and the fourth MO
A semiconductor integrated circuit device having a structure in which a voltage obtained by adding a threshold voltage of an S transistor is lower than a built-in voltage of a PN junction in a drain-substrate region of the first MOS transistor. 8. A first MO having a source connected to a constant voltage source.
An S transistor, a source connected to the drain of the first MOS transistor, a second MOS transistor connected to a booster power supply circuit having a substrate region provided therein, a source connected to ground potential, and a drain connected to the first MOS transistor. MO of 2
The second MOS connected to the drain of the S transistor
An output circuit including a transistor and a third MOS transistor having a reverse polarity, wherein a source voltage of the second MOS transistor is controlled by a control signal of a gate of the first MOS transistor. Semiconductor integrated circuit device. 9. A transistor having a source connected to a substrate region of a second MOS transistor, and a gate and a drain connected to the second MOS transistor.
A fourth MOS transistor having a polarity opposite to that of the second MOS transistor connected to a drain of the transistor, wherein a threshold voltage of the fourth MOS transistor is equal to that of another MOS transistor of the same polarity used for an internal function circuit. 9. The semiconductor integrated circuit device according to claim 8, wherein the voltage is lower than a threshold voltage and lower than a built-in voltage of a PN junction in a drain / substrate region of the second MOS transistor. 10. A fourth transistor having a polarity opposite to that of the second MOS transistor having a source connected to the substrate region of the second MOS transistor and a gate and a drain connected to a constant voltage source.
9. The semiconductor integrated circuit according to claim 8, further comprising an OS transistor, wherein a threshold voltage of the fourth MOS transistor is lower than a threshold voltage of another MOS transistor of the same polarity used for the internal function circuit. Circuit device. 11. A source connected to a substrate region of a second MOS transistor, and a gate and a drain connected to the second MOS transistor.
The second MOS connected to the drain of the S transistor
A fourth MOS transistor having a polarity opposite to that of the transistor;
A fifth MOS transistor having a polarity opposite to that of the second MOS transistor having a source connected to a substrate region of the second MOS transistor and a gate and a drain connected to a constant voltage source; The threshold voltage of the MOS transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit, and
9. The semiconductor integrated circuit device according to claim 8, wherein a threshold voltage of the S transistor is lower than a built-in voltage of a PN junction in a drain-substrate region of the second MOS transistor. 12. A fourth MOS transistor having a gate and a drain connected to the drain of the second MOS transistor and having a polarity opposite to that of the second MOS transistor, and a gate connected to the drain of the second MOS transistor. A fifth MOS transistor having a reverse polarity to the second MOS transistor having a drain connected to a source of the fourth MOS transistor and a source connected to a substrate region of the second MOS transistor; And the threshold voltage of the fifth MOS transistor is lower than the threshold voltage of another MOS transistor of the same polarity used for the internal function circuit, and
The sum of the threshold voltage of the S transistor and the threshold voltage of the fifth MOS transistor is equal to the voltage of the second M transistor.
9. The semiconductor integrated circuit device according to claim 8, wherein the structure is lower than a built-in voltage of a PN junction in a drain / substrate region of the OS transistor. 13. A fourth MOS transistor having a gate and a drain connected to the drain of the second MOS transistor and having a polarity opposite to that of the second MOS transistor, and a gate connected to the drain of the second MOS transistor. A fifth MOS transistor having a drain connected to a source of the fourth MOS transistor, a source connected to a substrate region of the second MOS transistor, and a fifth MOS transistor having a polarity opposite to that of the second MOS transistor; A sixth MOS transistor having a polarity opposite to that of the second MOS transistor connected to a constant voltage source and having a source connected to a substrate region of the second MOS transistor; Another MOS transistor of the same polarity used for the internal function circuit when the threshold voltage of the MOS transistor is used
Lower than the threshold voltage of the transistor;
And the fifth MO transistor.
9. The semiconductor integrated circuit device according to claim 8, wherein a voltage obtained by adding a threshold voltage of the S transistor is lower than a built-in voltage of a PN junction in a drain / substrate region of the second MOS transistor. .