JPS63306402A - Method for packaging optical element - Google Patents

Method for packaging optical element

Info

Publication number
JPS63306402A
JPS63306402A JP14246187A JP14246187A JPS63306402A JP S63306402 A JPS63306402 A JP S63306402A JP 14246187 A JP14246187 A JP 14246187A JP 14246187 A JP14246187 A JP 14246187A JP S63306402 A JPS63306402 A JP S63306402A
Authority
JP
Japan
Prior art keywords
substrate
fixing agent
optical device
optical element
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14246187A
Other languages
Japanese (ja)
Other versions
JP2534263B2 (en
Inventor
Yasubumi Yamada
泰文 山田
Akira Himeno
明 姫野
Morio Kobayashi
盛男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14246187A priority Critical patent/JP2534263B2/en
Publication of JPS63306402A publication Critical patent/JPS63306402A/en
Application granted granted Critical
Publication of JP2534263B2 publication Critical patent/JP2534263B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To fix a semiconductor optical element to packaging parts without generating a positional deviation by previously setting a substrate to a prescribed temp. and executing a registration stage, then supplying a fixing agent at the time of fixing the packaging parts and the substrate with the fixing agent after mounting the element to the packaging parts. CONSTITUTION:The optical element 4 is mounted on the packaging parts 24 and the packaging parts are superposed on the substrate 1 formed with 1st and 2nd conductor patterns 21, 22 insulated electrically from each other and the registration of light guides 2 and the element 4 is executed in such a manner that the element 4 comes into contact with the 1st pattern 21 and the packaging parts 24 come into contact with the 2nd pattern 22. The packaging parts 24 and the substrate 1 are fixed by using the fixing agent 25. The substrate 1, the elements 4 and the parts 24 are heated up to the temp. at which the patterns 21, 22 are melted to electrically connect the pattern 21 and the element 4 and to electrically connect the pattern 22 and the parts 24. The element 4 is thereby precisely registered to the end parts of the light guides and fixed onto the substrate 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ハイブリッド光集積回路を製作する際に重要
となる光素子の実装方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for mounting optical elements, which is important when manufacturing a hybrid optical integrated circuit.

〔従来の技術〕[Conventional technology]

光通信や光情報処理分野で必要となる各種光回路の小型
化、高信頼化及び低価格化のために、基板上に形成した
光導波路と各種素子とを複合一体化したハイブリッド光
集積回路の実現が期待される。
In order to reduce the size, reliability, and cost of various optical circuits required in the fields of optical communications and optical information processing, we are developing hybrid optical integrated circuits that combine optical waveguides formed on a substrate with various elements. It is hoped that this will be realized.

第6図は、この種のハイブリッド光集積回路のプロトタ
イプであり、S、!!根板上形成した石英軽マルヂモー
ド光導波路と半導体レーザとを一体化した例である(1
1、Terui 、 Y、YaIlada、 H,Ka
wachiand H,にobayashi  “Hy
brid Integration of aLase
r Diode and Iligh−silica 
HultimodcOptical Channel 
Waveguide on 5ilion″。
Figure 6 shows a prototype of this type of hybrid optical integrated circuit, S,! ! This is an example of integrating a quartz light multi-mode optical waveguide formed on a base plate and a semiconductor laser (1).
1. Terui, Y., YaIlada, H. Ka.
wachiand H, ni obayashi “Hy
bridge Integration of aLase
r Diode and Ilight-silica
HultimodcOptical Channel
Waveguide on 5illion''.

Nectron、Lett、、Vo121. DO64
6−648,1985) 。第6図で、1はS=基板、
2は光導波路であり、コアFfI2a、バッファFJ2
b及びクラッド層2cの3F4m造をしている。3はレ
ーザガイド、4は半導体レーデ、4aはその活性層であ
る。6は給電用ワイヤ、7はW[膜で蕊る。半導体レー
ザ4はレーザガイド3に押しあてられ、光導波路2に対
する適正位置に位置決めされる。レーザ・導波路間の許
容位置ずれ聞は多モード系では±2〜3 ta s単一
モード系では±0.5〜1.0瀾と小さく、極めて高い
位置決め精度が要求される。
Nectron, Lett,, Vo121. DO64
6-648, 1985). In Figure 6, 1 is S = substrate,
2 is an optical waveguide, which includes a core FfI2a and a buffer FJ2.
It has a 3F and 4m structure with a cladding layer 2c and a cladding layer 2c. 3 is a laser guide, 4 is a semiconductor radar, and 4a is its active layer. 6 is a power supply wire, and 7 is a W film. The semiconductor laser 4 is pressed against the laser guide 3 and positioned at an appropriate position relative to the optical waveguide 2. The allowable positional deviation between the laser and the waveguide is as small as ±2 to 3 tas in a multimode system and ±0.5 to 1.0 in a single mode system, and extremely high positioning accuracy is required.

上述のような精密位置合せは、例えば、第7図のように
して行なう。同図において、8はマニピュレータ、9は
ステージ、10はファイバである。
Precise alignment as described above is performed, for example, as shown in FIG. In the figure, 8 is a manipulator, 9 is a stage, and 10 is a fiber.

高さ方向については、光導波路2のコア1I2a中心の
高さが、半導体レーザ4の活性層4aの高さと一致する
ように、あらかじめ設計・製作しであるので、半導体レ
ーザ4を基板1上に搭載するだけで位置合せが実現でき
る。一方、横方向については、マニピューレータ8に半
導体レーザ4を保持して、基板1上で半導体レーザ4の
位置を動がしながら、半導体レーザ4と光導波路2との
光結合効率をモニタすることにより最大効率が得られる
位置を求めることにより実現する(特願昭62−473
67号、山田、小林、回内「ハイブリッド光集積回路組
立て装置J)。なお、第7図において、ステージ9は、
基板1の湿度′F¥温のためのヒータも兼ねる。
Regarding the height direction, since the height of the center of the core 1I2a of the optical waveguide 2 is designed and manufactured in advance to match the height of the active layer 4a of the semiconductor laser 4, the semiconductor laser 4 is placed on the substrate 1. Alignment can be achieved just by installing it. On the other hand, in the lateral direction, the semiconductor laser 4 is held by the manipulator 8 and the position of the semiconductor laser 4 is moved on the substrate 1 while the optical coupling efficiency between the semiconductor laser 4 and the optical waveguide 2 is monitored. This can be achieved by finding the position where maximum efficiency can be obtained (Patent Application 1986-473)
No. 67, Yamada, Kobayashi, Pronation "Hybrid optical integrated circuit assembly device J). In addition, in Fig. 7, stage 9 is
It also serves as a heater for controlling the humidity and temperature of the substrate 1.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、従来、基板上への半導体光素子の固定には、
(D低融点金属による熱圧着、または(ii)半田、接
着剤等の固定剤による接着、が一般的に用いられている
。熱圧着法においては、素子固定時に、基板湿度を低融
点金属の融点以上の湿度(例えば、Au−3n合金では
320℃以上)までMWする必要がある。位置合せに先
立ち、基板湿度を融点以上に上げておくと、上述の横方
向の位置合わせができなくなる。何故ならば、一度、半
導体光素子を基板上にnくと、その場所に固定されてし
まうので、半導体光素子を基板上で移動し、結合効率最
大となる位置を児い出すことができなくなるからである
。また、逆に、位置合わせの後に、基板を昇温して固定
する場合には、昇温過程で半導体光素子を保持したマニ
ピュレータ8の熱膨張、あるいは基板を載せたステージ
9の熱膨張のために、半導体光素子と光導波路間の位置
ずれが生じてしまう。第7図の装置でこの位置ずれ山は
、100℃の湿度差に対して約10mであった。したが
って、熱圧着法での素子固定は困難である。一方、(U
)の固定剤による固定を行なう場合、既述の理由により
、あらかじめ基板上に固定剤を供給しておくことはでき
ない。また、位置合わせ後は固定剤を基板と半導体光素
子との間に供給することはできない。したがって、位置
合わせ後は半導体光素子の側面に固定剤をつけることに
なり、このように固定剤を供給した場合に、半導体光素
子の活性層面、あるいは光導波路側面に固定剤が回り込
む恐れがある。
By the way, conventionally, to fix a semiconductor optical device on a substrate,
(D) Thermocompression bonding with a low melting point metal, or (ii) bonding with a fixing agent such as solder or adhesive, is generally used. In the thermocompression bonding method, when fixing the element, the humidity of the substrate is controlled by the low melting point metal. It is necessary to perform MW to a humidity higher than the melting point (for example, 320° C. or higher for Au-3n alloy).If the substrate humidity is raised to higher than the melting point prior to alignment, the above-mentioned lateral alignment will not be possible. This is because once a semiconductor optical device is placed on a substrate, it is fixed in place, making it impossible to move the semiconductor optical device on the substrate and find the position where the coupling efficiency is maximized. Conversely, when the substrate is heated and fixed after alignment, thermal expansion of the manipulator 8 holding the semiconductor optical device or stage 9 on which the substrate is placed may occur during the heating process. Due to thermal expansion, a positional shift occurs between the semiconductor optical device and the optical waveguide.In the device shown in Fig. 7, this positional shift peak was approximately 10 m for a humidity difference of 100°C. It is difficult to fix the element using the crimping method.On the other hand, (U
) When fixing with a fixing agent, it is not possible to supply the fixing agent onto the substrate in advance for the reasons mentioned above. Further, after alignment, a fixing agent cannot be supplied between the substrate and the semiconductor optical device. Therefore, after alignment, a fixing agent must be applied to the side surface of the semiconductor optical device, and if the fixing agent is supplied in this way, there is a risk that the fixing agent will wrap around the active layer surface of the semiconductor optical device or the side surface of the optical waveguide. .

したがって、上記従来の方法では、光導波路端部に半導
体光素子を精密に位置合わせして基板上に固定すること
が困難である等の問題があった。
Therefore, the conventional method described above has problems such as difficulty in precisely positioning the semiconductor optical device at the end of the optical waveguide and fixing it on the substrate.

本発明の目的は、上記の問題点を解決した光素子の実装
方法を提供することにある。
An object of the present invention is to provide a method for mounting an optical device that solves the above problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、実装部品に光素子を搭載し、互いに電気的に
絶縁された第1及び第2の導体パタンを形成した基板上
に、前記光素子が前記第1の導体パタンに接し、前記実
装部品が前記第2の導体パタンに接するように前記光素
子を搭載した前記実装部品を重ね、前記基板上に形成さ
れた光導波路と前記光素子との位置合せを行ない、前記
実装部品と前記基板とを固定剤を用いて固定し、前記基
板と前記光素子と前記実装部品を前記第1及び第2の導
体パタンを融かす湿度にまで上昇させることにより、前
記第1の導体パタンと前記光素子とを電気的に接続させ
、前記第2の導体パタンと前記実装部品とを電気的に接
続させることを特徴としている。
The present invention includes an optical element mounted on a mounting component, a substrate on which first and second conductive patterns electrically insulated from each other are formed, the optical element is in contact with the first conductive pattern, and the optical element is mounted on the substrate. The mounted component carrying the optical element is stacked so that the component is in contact with the second conductor pattern, the optical waveguide formed on the substrate is aligned with the optical element, and the mounted component and the substrate are aligned. By fixing the substrate, the optical element, and the mounting component using a fixing agent, and increasing the humidity of the substrate, the optical element, and the mounting component to a level that melts the first and second conductive patterns, the first conductive pattern and the optical The device is characterized in that the second conductive pattern and the mounted component are electrically connected to each other.

本発明では、実装部品と基板とを固定剤を用いて固定す
るようにしているが、この固定剤を使用する部分が光素
子から離間した位置となるように配慮しており、固定剤
が光素子の活性層面等に回り込まないように配慮してい
る。
In the present invention, the mounted component and the board are fixed using a fixing agent, but care is taken so that the part where the fixing agent is used is located away from the optical element, so that the fixing agent does not light up. Care is taken to prevent it from wrapping around the active layer surface of the device.

〔実施例〕〔Example〕

[実施例1] 第1図(a)、(b)は、本発明の第1の実施例を説明
16図であって、1は基板(例えば、SL基板)、1b
はバッファ層、2は光導波路(例えば、石英系光導波路
)、21は第1の導体パタン、22は第2の導体パタン
、23はチップキャリア用導体パタン、24はチップキ
ャリア(実装部品)、24aはチップキャリア凸部であ
る。また、4は半導体光素子であり、例えば、半導体レ
ーザ、光増幅器、フォトディテクタ、光ゲート等各秒素
子がこれに相当する。また、25は固定剤である。
[Example 1] FIGS. 1(a) and 1(b) are 16 diagrams explaining the first example of the present invention, in which 1 is a substrate (for example, an SL substrate), 1b is a
2 is a buffer layer, 2 is an optical waveguide (for example, a quartz optical waveguide), 21 is a first conductor pattern, 22 is a second conductor pattern, 23 is a conductor pattern for a chip carrier, 24 is a chip carrier (mounted component), 24a is a chip carrier convex portion. Moreover, 4 is a semiconductor optical device, and each second device such as a semiconductor laser, an optical amplifier, a photodetector, and an optical gate corresponds to this. Further, 25 is a fixing agent.

本実施例では、接着剤を用いる。第1図(a)はチップ
キャリア部分を示したものであり、半導体光素子4は活
性14aを上向きにしてチップキャリア24表面に固定
されている。半導体光素子4の表面には導電1!26が
形成されている。チップキャリア24の表面には導体パ
タン23が形成されているので、半導体光素子4のn極
側電極は、チップキャリア24の表面からとることがで
きる。
In this embodiment, an adhesive is used. FIG. 1(a) shows the chip carrier portion, and the semiconductor optical device 4 is fixed on the surface of the chip carrier 24 with the active layer 14a facing upward. A conductive layer 1!26 is formed on the surface of the semiconductor optical device 4. Since the conductive pattern 23 is formed on the surface of the chip carrier 24, the n-electrode of the semiconductor optical device 4 can be taken from the surface of the chip carrier 24.

また、チップキャリア凸部24aの高さJ2は、半導体
光素子4の高さJ3とほぼ等しくなるように設定しであ
る。チップキャリア24は、半導体光素子4のヒートシ
ンクを兼ねるために、熱伝導度の良い材料、例えばSi
あるいはCuを用いる。第1図(b)はチップキャリア
24に搭載した半導体光素子4を活性J44aを下向き
にしたアップサイド・ダウンの構成で搭載した図である
。搭載にあたっては、第7図に示したのと同様の装置を
用いて、最適位置に半導体光素子4を位置合わせした後
、固定剤25をチップキャリア凸部24aのまわりに供
給し、硬化させることにより固定した。
Further, the height J2 of the chip carrier convex portion 24a is set to be approximately equal to the height J3 of the semiconductor optical device 4. The chip carrier 24 is made of a material with good thermal conductivity, such as Si, in order to serve as a heat sink for the semiconductor optical device 4.
Alternatively, Cu is used. FIG. 1(b) shows the semiconductor optical device 4 mounted on the chip carrier 24 in an upside-down configuration with the active J44a facing downward. For mounting, after aligning the semiconductor optical device 4 to the optimum position using a device similar to that shown in FIG. 7, the fixing agent 25 is supplied around the chip carrier convex portion 24a and cured. It was fixed by

この時、固定剤としては導体パタン21及び22に用い
た金属の融点より低い湿度で固まる接着剤を用いる。な
お、接着剤の硬化湿度と導体パタン金属の融点との差は
小さい方が望ましい。また、接着剤の滴下1は、チップ
キャリア凸部24aを固定するのに十分で、かつ半導体
光素子4への回り込みのない量に設定する。位置合せに
先立ち、基板湿度を接着剤の硬化湿度以上で、かつ導体
パタン21.22の融点より低い湿度に設定しておき、
この状態で光導波路2と半導体光素子4との精密位置合
せ工程を行い、ひきつづき接着剤を供給することにより
、位置ずれなしに半導体光素子4を基板1上に固定する
ことができる。何故ならば、位置合せ→接着剤供給→囚
定の一連の工程を基板湿度を変化させることなく行なう
ことができるので、Iff変化に伴う組立て治具の熱膨
張による半導体光素子の位置ずれがおこらないからであ
る。この結果、半導体光素子4のpin′R極(導電w
!26)と導体パタン21とが接触するので、第1の導
体パタン21からpHg極が取り出せる。
At this time, an adhesive that hardens at a humidity lower than the melting point of the metal used for the conductor patterns 21 and 22 is used as the fixing agent. Note that it is desirable that the difference between the curing humidity of the adhesive and the melting point of the conductive pattern metal be small. Further, the amount of adhesive dripped 1 is set to be sufficient to fix the chip carrier convex portion 24a and to prevent it from flowing around to the semiconductor optical device 4. Prior to alignment, the humidity of the substrate is set to be higher than the curing humidity of the adhesive and lower than the melting point of the conductor patterns 21 and 22,
In this state, the optical waveguide 2 and the semiconductor optical device 4 are precisely aligned, and by continuing to supply adhesive, the semiconductor optical device 4 can be fixed on the substrate 1 without any positional shift. This is because the series of steps of alignment → adhesive supply → fixing can be performed without changing the substrate humidity, which prevents misalignment of the semiconductor optical device due to thermal expansion of the assembly jig due to changes in Iff. That's because there isn't. As a result, the pin'R pole (conductive w
! 26) and the conductor pattern 21, the pHg electrode can be taken out from the first conductor pattern 21.

同様に、nll電極は、チップキャリア24の表面に形
成した導体パタン23を通り、チップキャリア凸部24
aを通して第2の導体パタン22と接続する。接着剤が
十分に硬化した後、基板湿度を上昇し、導体パタン21
.22の融点以上に昇温する。この結果、半導体光素子
のp側電極と導体パタン21及びチップキャリア凸部2
4a(すなわち、n1llllffi極)と導体パタン
22との電気的接続が完了する。なお、チップキャリア
24は固定剤25により固定されているので、この昇温
過程における半導体光素子4に位置ずれは抑制できる。
Similarly, the nll electrode passes through the conductor pattern 23 formed on the surface of the chip carrier 24, and passes through the chip carrier convex portion 24.
It is connected to the second conductor pattern 22 through a. After the adhesive has sufficiently hardened, the substrate humidity is increased and the conductor pattern 21
.. The temperature is raised above the melting point of 22. As a result, the p-side electrode of the semiconductor optical device, the conductor pattern 21 and the chip carrier convex portion 2
4a (that is, the n1llllffi pole) and the conductor pattern 22 are electrically connected. Note that since the chip carrier 24 is fixed by the fixing agent 25, the positional shift of the semiconductor optical device 4 during this temperature rising process can be suppressed.

このように、本実施例によれば、光導波路端部に半導体
光素子を精密位置合せをした状態で固定することができ
る。しかも、同時に電気配線も完了するのでワイヤボン
ディング工程が不要となる。
In this way, according to this embodiment, the semiconductor optical device can be fixed to the end of the optical waveguide in a precisely aligned state. Moreover, since the electrical wiring is completed at the same time, a wire bonding process is not necessary.

[実施例2] 第2図は、本発明の第2実施例を示す図であり、光導波
路2と同時に形成された凸状パタンで囲まれた液溜め3
0を用いた固定法を示している。第2図(a)において
、導波路2の#部近傍には液溜め30が形成されており
、この両側に導体パタン21及び22が形成されている
。第2図(b)は、この液溜め30を用いた固定法を示
している。
[Example 2] FIG. 2 is a diagram showing a second example of the present invention, in which a liquid reservoir 3 surrounded by a convex pattern formed at the same time as the optical waveguide 2 is shown.
A fixation method using 0 is shown. In FIG. 2(a), a liquid reservoir 30 is formed near the # section of the waveguide 2, and conductor patterns 21 and 22 are formed on both sides of this reservoir. FIG. 2(b) shows a fixing method using this liquid reservoir 30.

第1図(a)のように、チップキャリア24」−に半導
体素子4を搭載した後に、実施例1と同様にアップサイ
ド・ダウン状態で導波路2との位置合せを行なった。次
いで、液溜め30の中に、固定剤25を流し込んでチッ
プキャリア24を固定する。この方法は、固定剤25が
半導体素子4側へ流れる恐れがないので、実施例1より
も容易な固定法である。
After the semiconductor element 4 was mounted on the chip carrier 24'' as shown in FIG. 1(a), it was aligned with the waveguide 2 in the upside-down state as in Example 1. Next, the fixing agent 25 is poured into the liquid reservoir 30 to fix the chip carrier 24. This method is an easier fixing method than Example 1 because there is no fear that the fixing agent 25 will flow toward the semiconductor element 4 side.

[実施例3コ 第3図は、本発明の第3の実施例を説明する図である。[Example 3 FIG. 3 is a diagram illustrating a third embodiment of the present invention.

第3図(a)のように、液溜め30を導波路2の近傍に
形成し、導波路2と液溜め30との間に、第1の導体パ
タン21を形成した。第2の導体パタン22は液溜め3
0上に形成しである。
As shown in FIG. 3(a), a liquid reservoir 30 was formed near the waveguide 2, and a first conductor pattern 21 was formed between the waveguide 2 and the liquid reservoir 30. The second conductor pattern 22 is the liquid reservoir 3
It is formed on 0.

半導体光素子4は第3図(b)に示すチップキャリア2
4上に搭載する。この時、液溜め30の高さJ+、チッ
プキャリア24の凸部24aの高さJ2及び半導体光素
子4の高さJ3との間には、J3ヱJI+42の関係が
ある(第3図C)。したがって、半導体光素子4をアッ
プサイド・ダウンで基板上に搭載し、位置合せの後に液
溜め30内に固定剤を供給することによりチップキャリ
アの固定ができる。固定の後、実施例1と同様に基板を
MAL、電気的接続を完了する。
The semiconductor optical device 4 is mounted on a chip carrier 2 shown in FIG. 3(b).
4 to be installed on top. At this time, the relationship between the height J+ of the liquid reservoir 30, the height J2 of the convex portion 24a of the chip carrier 24, and the height J3 of the semiconductor optical device 4 is J3ヾJI+42 (FIG. 3C). . Therefore, the chip carrier can be fixed by mounting the semiconductor optical device 4 upside down on the substrate and supplying a fixing agent into the liquid reservoir 30 after alignment. After fixing, the substrate is MALed and electrical connections are completed in the same manner as in Example 1.

[実施例4] 第4図は、液溜め30が、バッファ層1bを凹状に彫り
込んで形成された例である。第3図の実施例と同様に、
第2の導体パタン22は、液溜め30上に形成しである
。チップキャリア24の凸部24aの高さJ2と半導体
光素子4の高さJ3とがほぼ等しくなるように設定する
。実施例1と同様の方法で位置合ぜをした後、液溜め3
0中に固定剤25を供給してチップキャリア24の固定
ができる。
[Example 4] FIG. 4 shows an example in which the liquid reservoir 30 is formed by carving the buffer layer 1b into a concave shape. Similar to the embodiment of FIG.
The second conductor pattern 22 is formed on the liquid reservoir 30. The height J2 of the convex portion 24a of the chip carrier 24 and the height J3 of the semiconductor optical device 4 are set to be approximately equal. After alignment in the same manner as in Example 1, the liquid reservoir 3
The chip carrier 24 can be fixed by supplying a fixing agent 25 into the container.

[実施例5] 第5図は、本発明の第5の実施例を示す図である。同図
において、光導波路2は石英系光導波路であり、凹凸を
有するSt基板1上に形成されている。SL基板1の凹
部31には、バッファ層1bが形成されており、その上
に、光導波路2が形成されている。SL基板凸部32の
表面はSi而が露出している(特願昭61−27705
8号、山田、回内、小林「ハイブリッド光集積回路J)
a第1の導体パタン21は、石英系光導波路バッファ1
1bの上にパタン化されており、第2の導体パタン22
は、SL基板凸部32の表面上にパタン化されている。
[Embodiment 5] FIG. 5 is a diagram showing a fifth embodiment of the present invention. In the figure, the optical waveguide 2 is a quartz-based optical waveguide, and is formed on the St substrate 1 having irregularities. A buffer layer 1b is formed in the recess 31 of the SL substrate 1, and an optical waveguide 2 is formed thereon. Si is exposed on the surface of the SL substrate convex portion 32 (Japanese Patent Application No. 61-27705)
No. 8, Yamada, Yonai, Kobayashi "Hybrid Optical Integrated Circuit J)
a The first conductor pattern 21 is a silica-based optical waveguide buffer 1
1b, and a second conductor pattern 22
is patterned on the surface of the SL substrate convex portion 32.

第1の導体パタン21と第2の導体パタン22との間に
、実施例2と同様の液溜め30が形成されている。チッ
プキャリア24に搭載された半導体素子4をアップサイ
ド・ダウンで位置合せした後、液溜め30中に固定剤2
5を供給すればチップキャリア24を基板上に固定でき
る。本実施例では、上述の実施例と同様、半導体光素子
4を位置ずれを起こすことなく、光導波路端部に固定す
ることができる。それに加えて、本実施例においては、
ヒートシンクを兼ねたチップキャリア24の凸部24a
が導体パタン22を介してSL基板表面に接している。
A liquid reservoir 30 similar to that in the second embodiment is formed between the first conductor pattern 21 and the second conductor pattern 22. After aligning the semiconductor element 4 mounted on the chip carrier 24 upside down, the fixing agent 2 is poured into the liquid reservoir 30.
5, the chip carrier 24 can be fixed on the substrate. In this embodiment, as in the above-described embodiments, the semiconductor optical device 4 can be fixed to the end of the optical waveguide without causing any positional shift. In addition, in this example,
Convex portion 24a of chip carrier 24 that also serves as a heat sink
is in contact with the surface of the SL substrate via the conductor pattern 22.

したがって、半導体光素子4で発生した熱は、チップキ
ャリア24を経て、SL基板1に逃げるので、冷却効果
に優れるという特徴がある。
Therefore, the heat generated in the semiconductor optical device 4 escapes to the SL substrate 1 via the chip carrier 24, so that the cooling effect is excellent.

なお、上記実施例では、半導体光素子を基板上にアップ
サイド・ダウンで搭載する例を取り上げたが、アップサ
イド・アップの場合にも本発明は適用できる。
In the above embodiments, the semiconductor optical device is mounted upside down on the substrate, but the present invention can also be applied to the case where the semiconductor optical device is mounted upside down.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明では、精密位置合せが要求
される光導波路と光半導体光素子の集積にあたって、半
導体光素子を実装部品に搭載した後、実装部品と基板と
を固定剤で固定するようにしたので、あらかじめ所定の
湿度に基板を設定した上で位置合せ工程を行なった後に
固定剤を供給することにより、位置ずれを起こさずに固
定することが可能となった。またこの発明は、固定剤を
使用する部分が光素子から離間した位置となるように配
慮しているため、固定剤が光素子の活性面等に回り込む
のを防止することができる。さらに、この発明は、基板
上に形成した2つの導体パタンの一方に半導体光素子の
一方の電極を接触させ、倍力の電極は実装部品を通して
他方の導体パタンと接触させるようにした。この結果、
半導体光素子を基板上に搭載しただけで、ワイヤボンデ
ィング工程ない電気配線が取れるので、プロセスが簡略
になるという利点がある。
As explained above, in the present invention, when integrating an optical waveguide and an optical semiconductor optical device that require precise alignment, the semiconductor optical device is mounted on a mounting component, and then the mounting component and the substrate are fixed with a fixing agent. As a result, by setting the substrate at a predetermined humidity in advance and performing the positioning process, and then supplying the fixing agent, it is possible to fix the substrate without causing any displacement. Further, in the present invention, since the part where the fixing agent is used is located at a position separated from the optical element, it is possible to prevent the fixing agent from getting around to the active surface of the optical element. Further, in the present invention, one electrode of the semiconductor optical device is brought into contact with one of the two conductor patterns formed on the substrate, and the booster electrode is brought into contact with the other conductor pattern through the mounting component. As a result,
This method has the advantage of simplifying the process because electrical wiring can be established by simply mounting the semiconductor optical device on the substrate without requiring a wire bonding process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)は本発明の第1実施例の説明図、
第2図(a)、(b)は液溜めを右した本発明の第2実
施例の説明図、第3図(a)〜゛(C)は本発明の第3
実施例の説明図、第4図(a)、(−t))は本発明の
第4実施例の説明図、第5図は本発明の15実施例の説
明図である。第6図は従来の半導体光素子の実装方法を
示す説明図、第7図は半導体光素子の実装工程を説明す
る図である。 1・・・基板、2・・・光導波路、4・・・光素子(半
導体光素子)、21・・・第1のη体パタン、22・・
・第2の導体パタン、24・・・実装部品(チップキャ
リア)、25・・・固定剤。
FIGS. 1(a) and 1(b) are explanatory diagrams of the first embodiment of the present invention,
FIGS. 2(a) and (b) are explanatory views of the second embodiment of the present invention with the liquid reservoir on the right, and FIGS. 3(a) to 3(C) are explanatory diagrams of the third embodiment of the present invention.
FIGS. 4(a) and 4(-t) are explanatory diagrams of the fourth embodiment of the present invention, and FIG. 5 is an explanatory diagram of the 15th embodiment of the present invention. FIG. 6 is an explanatory diagram showing a conventional method for mounting a semiconductor optical device, and FIG. 7 is a diagram explaining a mounting process of a semiconductor optical device. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Optical waveguide, 4... Optical device (semiconductor optical device), 21... First η-body pattern, 22...
- Second conductor pattern, 24... Mounted component (chip carrier), 25... Fixing agent.

Claims (1)

【特許請求の範囲】[Claims] 実装部品に光素子を搭載し、互いに電気的に絶縁された
第1及び第2の導体パタンを形成した基板上に、前記光
素子が前記第1の導体パタンに接し、前記実装部品が前
記第2の導体パタンに接するように前記光素子を搭載し
た前記実装部品を重ね、前記基板上に形成された光導波
路と前記光素子との位置合せを行ない、前記実装部品と
前記基板とを固定剤を用いて固定し、前記基板と前記光
素子と前記実装部品を前記第1及び第2の導体パタンを
融かす湿度にまで上昇させることにより、前記第1の導
体パタンと前記光素子とを電気的に接続させ、前記第2
の導体パタンと前記実装部品とを電気的に接続させるこ
とを特徴とする光素子の実装方法。
An optical element is mounted on a mounted component, on a substrate on which first and second conductive patterns electrically insulated from each other are formed, the optical element is in contact with the first conductive pattern, and the mounted component is in contact with the first conductive pattern. The mounted component carrying the optical element is stacked so as to be in contact with the conductor pattern No. 2, the optical waveguide formed on the substrate and the optical element are aligned, and the mounted component and the substrate are bonded with a fixing agent. By fixing the substrate, the optical element, and the mounted component to a humidity that melts the first and second conductive patterns, the first conductive pattern and the optical element are connected to each other by electricity. and the second
A method for mounting an optical device, comprising electrically connecting a conductor pattern and the mounted component.
JP14246187A 1987-06-08 1987-06-08 Optical element mounting method Expired - Lifetime JP2534263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14246187A JP2534263B2 (en) 1987-06-08 1987-06-08 Optical element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14246187A JP2534263B2 (en) 1987-06-08 1987-06-08 Optical element mounting method

Publications (2)

Publication Number Publication Date
JPS63306402A true JPS63306402A (en) 1988-12-14
JP2534263B2 JP2534263B2 (en) 1996-09-11

Family

ID=15315855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14246187A Expired - Lifetime JP2534263B2 (en) 1987-06-08 1987-06-08 Optical element mounting method

Country Status (1)

Country Link
JP (1) JP2534263B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH024204A (en) * 1988-06-21 1990-01-09 Hitachi Ltd Mounting method for opto-electronic circuits
US5074630A (en) * 1990-10-09 1991-12-24 Rodino Vincent D Integrated optics device mounting for thermal and high g-shock isolation
JPH0411206A (en) * 1990-04-27 1992-01-16 Teiji Uchida Photoelectronic integrated device
JPH0411205A (en) * 1990-04-27 1992-01-16 Teiji Uchida Optical surface packaging circuit and its optical component
JP2001111156A (en) * 1999-10-08 2001-04-20 Nippon Telegr & Teleph Corp <Ntt> Optical module
JP2015170701A (en) * 2014-03-06 2015-09-28 技術研究組合光電子融合基盤技術研究所 optical integrated circuit device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH024204A (en) * 1988-06-21 1990-01-09 Hitachi Ltd Mounting method for opto-electronic circuits
JPH0411206A (en) * 1990-04-27 1992-01-16 Teiji Uchida Photoelectronic integrated device
JPH0411205A (en) * 1990-04-27 1992-01-16 Teiji Uchida Optical surface packaging circuit and its optical component
US5074630A (en) * 1990-10-09 1991-12-24 Rodino Vincent D Integrated optics device mounting for thermal and high g-shock isolation
JP2001111156A (en) * 1999-10-08 2001-04-20 Nippon Telegr & Teleph Corp <Ntt> Optical module
JP2015170701A (en) * 2014-03-06 2015-09-28 技術研究組合光電子融合基盤技術研究所 optical integrated circuit device

Also Published As

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