JPS63305616A - Signal level conversion circuit - Google Patents
Signal level conversion circuitInfo
- Publication number
- JPS63305616A JPS63305616A JP62142447A JP14244787A JPS63305616A JP S63305616 A JPS63305616 A JP S63305616A JP 62142447 A JP62142447 A JP 62142447A JP 14244787 A JP14244787 A JP 14244787A JP S63305616 A JPS63305616 A JP S63305616A
- Authority
- JP
- Japan
- Prior art keywords
- level signal
- voltage
- power supply
- ttl
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 14
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＴＴＬ（）ランジスタ・トランジスタロジック
）より成る制御回路等よりの制御信号、アドレス信号、
データ信号等即ちＴＴＬレベル信号を例えばＭＯＳ Ｌ
ＳＩにより構成されたメモリ等に供給する為にＣＭＯＳ
レベル信号に変換する信号レベル変換回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides control signals, address signals,
Data signals, etc., ie TTL level signals, for example, MOS L
CMOS to supply memory etc. configured by SI
The present invention relates to a signal level conversion circuit that converts into a level signal.
本発明はＴＴＬより成る制御回路等よりの制御信号、ア
ドレス信号、−データ信号等のＴＴＬレベル信号を例え
ばＭＯＳ ＬＳＩにより構成されたメモリ等に供給する
為にＣＭＯＳレベル信号に変換する信号レベル変換回路
に於いて、このＴＴＬレベル信号が供給される初段回路
を外部電源電圧を電圧降圧回路にて降圧した定電圧で動
作させる様にすることにより、外部電源電圧の変動やＭ
ＯＳ ＬＳＩのチップ内部の接地線の電圧上昇に係りな
く、ＴＴＬレベル信号をＣＭＯＳレベル信号に良好に変
換することができる様にしたものである。The present invention is a signal level conversion circuit that converts TTL level signals such as control signals, address signals, -data signals, etc. from a TTL control circuit into CMOS level signals in order to supply them to a memory configured by MOS LSI, etc. By operating the first stage circuit to which this TTL level signal is supplied with a constant voltage obtained by lowering the external power supply voltage using a voltage step-down circuit, fluctuations in the external power supply voltage and M
This allows a TTL level signal to be converted into a CMOS level signal without regard to the voltage rise of the ground line inside the OS LSI chip.
一般にＭＯＳ ＬＳＩはＴＴＬコンパチフ゛ルであるの
で、ＴＴＬより成る制御回路等よりの制御信号、アドレ
ス信号、データ信号即ちＴＴＬレベル信号をＭＯＳ Ｌ
ＳＩにより構成されたメモリ等に供給するに、このＴＴ
Ｌレベル信号をＣＭＯＳレベル信号にレベル変換する必
要がある。ここで°ＴＴＬレベル信号のハイレベル信号
“１”は２．４ｖ以上であり、このローレベル信号“０
°は０．８ｖ以下で、ＣＭＯＳレベル信号のハイレベル
信号“ｌ”は電源電圧であり、このローレベル信号“０
”は接地電位である。Generally, MOS LSI is TTL compatible, so control signals, address signals, data signals, that is, TTL level signals from a control circuit made of TTL, etc. are transferred to MOS LSI.
This TT is used to supply memory etc. configured by SI.
It is necessary to convert the level of the L level signal into a CMOS level signal. Here, the high level signal “1” of the TTL level signal is 2.4V or more, and this low level signal “0”
° is 0.8V or less, the high level signal “l” of the CMOS level signal is the power supply voltage, and this low level signal “0
” is the ground potential.
従来このＴＴＬレベル信号をＣＭＯＳレベル信号に変換
する信号レベル変換回路として第５図に示す如きインバ
ータ回路が使用されていた。叩ち第５図に於いて、ｆｉ
ｌはＴＴＬレベル信号が供給されるＴＴＬレベル信号入
力端子を示し、このＴＴＬレベル信号入力端子＋１１を
ＰチャンネルＭＯ５電界効果トランジスタ（ＭＯＳ Ｆ
ＥＴ ） ｆ２）及びＮチャンネルＭＯＳ電界効果トラ
ンジスタ（ＭＯＳ ＦＥＥＴ ） （３１の夫々のゲー
トに接続し、このＭＯＳ ＦＥＴ ＋２１のソースを正
の直流電圧例えば６Ｖが供給される電源端子（４）に接
続し、ＭＯＳ ＦＥＴ ＋３１のソースを接地し、この
ＭＯＳ ＦＥＴ （２１及び（３）の夫々のドレインを
互いに接続し、このドレインの互いの接続点よりＣＭＯ
Ｓレベル信号を出力するＣＭＯＳレベル信号出力端子（
５）を導出する。斯る第５図に於いてＰチャンネルＭＯ
５ＦＥＴ ＋２１のチャンネル幅を６μｍ、チャンネル
長を １．４μ−とし、ＮチャンネルＭＯＳ ＦＥＴ
（３１のチャンネル幅を１８μｍ、チャンネル長を１．
２μｍとしたとき、電源端子（４）に供給される電源電
圧ＶＣＣと論理しきい値との関係は第６図に示す如く、
例えば電源電圧Ｖｃｃが６■のときは論理しきい値は１
．７５Ｖとなり電源電圧Ｖｃｃが５■のときは論理しき
い値は１．５５Ｖである。Conventionally, an inverter circuit as shown in FIG. 5 has been used as a signal level conversion circuit for converting this TTL level signal into a CMOS level signal. In Figure 5, fi
l indicates a TTL level signal input terminal to which a TTL level signal is supplied, and this TTL level signal input terminal +11 is connected to a P-channel MO5 field effect transistor (MOSF
ET) f2) and an N-channel MOS field effect transistor (MOS FEET) (31), and the source of this MOS FET +21 is connected to a power supply terminal (4) to which a positive DC voltage, for example 6V, is supplied. , the source of MOS FET +31 is grounded, the respective drains of this MOS FET (21 and (3)) are connected to each other, and the CMO
CMOS level signal output terminal that outputs an S level signal (
5) is derived. In such FIG. 5, P channel MO
5FET +21 channel width is 6μm, channel length is 1.4μ-, N channel MOS FET
(The channel width of 31 is 18 μm, the channel length is 1.
When it is 2 μm, the relationship between the power supply voltage VCC supplied to the power supply terminal (4) and the logic threshold is as shown in FIG.
For example, when the power supply voltage Vcc is 6■, the logic threshold is 1
．． 75V, and when the power supply voltage Vcc is 5.5V, the logic threshold value is 1.55V.
従って電源電圧Ｖｃｃが６■のときにＴＴＬレベル信号
入力端子（１１に供給されるＴＴＬレベル信号が２．４
ｖ以上のハイレベル信号“１”のときはＭＯＳ ＦＥＴ
（２）はオフとなりＭＯＳ ＦＥＴ （３）はオンとな
るのでＣＭＯＳレベル信号出力端子（５）には接地電位
のＣＭＯＳレベル信号のローレベル信号″０″が得られ
、ＴＴＬレベル信号が０．８Ｖ以下のローレベル信号“
０”のときはＭＯＳ ＰＥＴ （２１はオンとなり、Ｍ
ＯＳ ＦＥＴ （３１はオフとなるのでこのＣＭＯＳレ
ベル信号出力端子（５）には６Ｖの電源電圧Ｖｃｃが得
られ、ＣＭＯＳレベル信号のハイレベル信号“１”が得
られる。Therefore, when the power supply voltage Vcc is 6cm, the TTL level signal supplied to the TTL level signal input terminal (11) is 2.4cm.
When the high level signal “1” is higher than v, the MOS FET
(2) is turned off and MOS FET (3) is turned on, so the low level signal "0" of the CMOS level signal at the ground potential is obtained at the CMOS level signal output terminal (5), and the TTL level signal is 0.8V. The following low level signal “
0”, MOS PET (21 is on, M
Since the OS FET (31) is turned off, a power supply voltage Vcc of 6V is obtained at this CMOS level signal output terminal (5), and a high level signal "1" of the CMOS level signal is obtained.
斯る第５図に示す如き信号レベル変換回路を使用したＭ
ＯＳ ＬＳＩに於いてＤＲＡＭのセンスアンプ動作や多
ビツト構成のＳＲＡＭ、 ＲＯＭのローレベル信号“０
”の出力時に接地線に大きな電流が流れ込みリードフレ
ームのインダクタンスにより逆起電力が生じチップ内に
接地レベルが上昇することがあり、例えば電源電圧Ｖｃ
ｃが６■で動作中にチップ内接地レベルがＩＶ上昇した
ときは、このチップ内の電源電圧は５Ｖになるので、こ
のときのこの信号レベル変換回路の論理しきい値は第６
図に示す如＜ １．５５Ｖとなるが、このチップの外部
から見ると接地レベルがＩＶ上昇しているので、この論
理しきい値は２．５５Ｖとなり、ＴＴＬレベル信号のハ
イレベル信号“１”の電圧２．４ｖ以上より高くなるこ
ととなり、正確なＴＴＬレベル信号−ＣＭＯＳレベル信
号の信号レベル変換ができな（なる不都合があった。ま
た第５図従来例に於いては電源電圧Ｖｃｃの変動により
ＴＴＬレベル信号とのマージンが変動し、小さくなる方
向に変動したときにはこのマージンが５区ケする不都合
があった。M using a signal level conversion circuit as shown in FIG.
In OS LSI, DRAM sense amplifier operation, multi-bit SRAM, ROM low level signal “0”
When outputting ", a large current flows into the ground wire and a back electromotive force is generated due to the inductance of the lead frame, which may increase the ground level within the chip. For example, when the power supply voltage Vc
When c is 6■ and the internal ground level of the chip rises by IV during operation, the power supply voltage within this chip becomes 5V, so the logic threshold of this signal level conversion circuit at this time is the 6th
As shown in the figure, < 1.55V, but as seen from the outside of this chip, the ground level has risen by IV, so this logical threshold becomes 2.55V, and the high level signal "1" of the TTL level signal The voltage becomes higher than 2.4V, making it impossible to accurately convert the signal level between the TTL level signal and the CMOS level signal.Also, in the conventional example shown in FIG. As a result, the margin with respect to the TTL level signal fluctuates, and when it fluctuates in the direction of decreasing, there is a problem that this margin becomes five sections.
本発明は斯る点に鑑み外部電源電圧の変動やＭＯＳ Ｌ
ＳＩのチップ内部の接地線の電圧上昇に係りなく、ＴＴ
Ｌレベル信号をＣＭＯＳレベル信号に良好に変換するこ
とができるようにすることを目的とする。In view of this, the present invention has been developed to reduce fluctuations in external power supply voltage and MOS L
Regardless of the voltage rise of the ground wire inside the SI chip, TT
It is an object of the present invention to enable good conversion of an L level signal to a CMOS level signal.
（問題点を解決するための手段〕
本発明信号レベル変換回路は例えば第１図に示す如＜
ＴＴＬレベル信号をＣＭＯＳレベル信号に変換する信号
レベル変換回路に於いて、このＴＴＬレベル信号が供給
される初段回路（６１（７１を外部電源電圧Ｖｃｃを電
圧降圧回路（８）にて降圧した定電圧で動作させる様に
したものである。(Means for Solving the Problems) The signal level conversion circuit of the present invention is, for example, as shown in FIG.
In the signal level conversion circuit that converts a TTL level signal into a CMOS level signal, the first stage circuit (61 (71) to which this TTL level signal is supplied is a constant voltage obtained by lowering the external power supply voltage Vcc by a voltage step-down circuit (8) This is how it works.
本発明に依れば初段回路（６１（７］を電圧降下回路（
８）にて降圧した定電圧例えば３ｖで動作させるので、
外部電源電圧Ｖｃｃの変動に関係なく論理しきい値は例
えば１．５Ｖで一定であり、ＴＴＬレベル信号とのマー
ジンは常に一定となる。According to the present invention, the first stage circuit (61(7)) is replaced by the voltage drop circuit (61(7)).
Since it is operated at a constant voltage, for example 3V, which is stepped down in step 8),
The logic threshold is constant at 1.5V, for example, regardless of fluctuations in the external power supply voltage Vcc, and the margin with the TTL level signal is always constant.
また本発明に於いては外部電源電圧Ｖｃｃを例えば６■
とし、この電圧降圧回路（８）の降圧定電圧を例えば３
■としたときに於いてチップ内の接地レベルが例えば１
■上昇したときは、初段回路（６１（７）の電源電圧は
２Ｖとなり、従ってチップ内部からみた論理しきい値は
第４図に示す如＜ＩＶとなり、外部から見たこの論理し
きい値は接地レベルの上昇分の１ｖが加算された２ｖと
なるがこれはＴＴＬレベル信号のハイレベル信号“１″
の２．４ｖ以上とローレベル信号“０゛の０．８ｖ以下
とを正確に判別することができ、このときの初段回路の
出力信号は接地レベルか、２ｖとなるかこの２段目を例
えば第５図に示す如きインバータ回路で構成したときは
このときは電源電圧Ｖｃｃが５ｖとなったことになるが
、このときのこの論理しきい値は第６図に示す如＜ １
．５５Ｖであり、良好なｃｎｏｓレベル信号を得ること
ができる。Further, in the present invention, the external power supply voltage Vcc is set to 6.
For example, the step-down constant voltage of this voltage step-down circuit (8) is 3
■When the ground level inside the chip is, for example, 1
■When the voltage rises, the power supply voltage of the first stage circuit (61 (7)) becomes 2V, so the logic threshold value seen from inside the chip becomes <IV as shown in Figure 4, and this logic threshold value seen from the outside becomes The 1v increase in the ground level is added to give 2v, which is the high level signal “1” of the TTL level signal.
It is possible to accurately distinguish between 2.4V or more of ``0'' and 0.8V or less of low level signal ``0'', and in this case, the output signal of the first stage circuit is either ground level or 2V. When configured with an inverter circuit as shown in FIG. 5, the power supply voltage Vcc becomes 5V, but the logical threshold value at this time is < 1 as shown in FIG.
．． The voltage is 55V, and a good CNOS level signal can be obtained.
以下第１図を参照しながら本発明信号レベル変換回路の
一実施例につき説明しよう、この第１図に於いて第５図
に対応する部分には同一符号を付しその詳細説明は省略
する。An embodiment of the signal level conversion circuit of the present invention will be described below with reference to FIG. 1. In FIG. 1, parts corresponding to those in FIG. 5 are given the same reference numerals, and detailed explanation thereof will be omitted.
第１１！１例に於いてはＴＴＬより成る制御回路等より
の制御信号、アドレス信号、データ信号等のＴＴＬレベ
ル信号をＴＴＬレベル信号入力端子（１）に供給する様
にしこのＴＴＬレベル信号入力端子（１）をインバータ
回路を構成するＰチャンネルＭＯＳ ＦＢＴ （６）及
びＮチャンネルＭＯＳ ＦＥＴ （７１の夫々のゲート
に接続し、このＭＯＳ ＦＥＴ （６）のソースを電圧
降圧回路（８）の出力側に接続する。この電圧降圧回路
（８）は電源端子（４）に供給される外部電源電圧Ｖｃ
ｃ例えば６ｖを降圧して例えば３ｖの定電圧を出力する
如く構成したものである。この電圧降圧回路（８）の例
としては第２図に示す如きものがある。Ｆ！ｐち第２図
に於いて、（８ａ）及び（８ｂ）は夫々ＰチャンネルＭ
ＯＳ ＰＥＴを示し、このＭＯＳ ＰＥＴ ＜８８＞
及び（８ｂ）の夫々のソースを互いに接続し、この接続
点を例えば６■の外部電源電圧Ｖｃｃが供給される電源
端子（４）に接続し、このＭＯＳ ＦＥＴ （８ａ）
及び（８ｂ）の夫々のドレインをＮチャンネル？ＩＯＳ
ＦＥＴ （８ｃ）及び（８ｄ）の夫々のドレインに
接続し、このＭＯＳ ＦＩＥＴ （８ｃ）及び（８ｄ
）の夫々のソースを互いに接続し、この接続点を接地し
、このＭＯＳ ＦＥＴ （８ｃ）及び（８ｄ）の夫々
のゲートを互いに接続し、このゲートの接続点ヲＭＯ５
ＰＥＴ （８ｄ）のドレインに接続し、またＭＯＳ
ＦＩＥＴ （８ａ）のゲートに例えば３Ｖの基準電圧
が得られる基準電圧源（９）を接続し、ＭＯＳ ＰＥＴ
（８ａ）及び（８ｃ）の夫々のドレインの接続点を
ｐチャンネルＭＯＳ ＦＩＥＴ （８ｅ）のゲートに
接続し、このＭＯＳＦＥＴ （８ｅ）のソースを電源
端子（４）に接続し、このＭＯＳ ＦＩＥＴ （８ｂ
）のゲートとＭＯＳ ＰＥＴ （８ｅ）のドレインと
の接続点より出力端子（８ｆ）を導出する。In the 11th!1 example, TTL level signals such as control signals, address signals, data signals, etc. from a control circuit made of TTL are supplied to the TTL level signal input terminal (1). (1) is connected to the respective gates of the P-channel MOS FBT (6) and N-channel MOS FET (71) that constitute the inverter circuit, and the source of this MOS FET (6) is connected to the output side of the voltage step-down circuit (8). This voltage step-down circuit (8) is connected to the external power supply voltage Vc supplied to the power supply terminal (4).
c It is configured to step down the voltage of, for example, 6V and output a constant voltage of, for example, 3V. An example of this voltage step-down circuit (8) is shown in FIG. F! In Fig. 2, (8a) and (8b) are respectively P channel M.
Indicates OS PET, and this MOS PET <88>
and (8b) are connected to each other, and this connection point is connected to a power supply terminal (4) to which an external power supply voltage Vcc of, for example, 6■ is supplied, and this MOS FET (8a)
And (8b) each drain is N channel? IOS
Connected to the respective drains of FETs (8c) and (8d), and connected to the drains of these MOS FIETs (8c) and (8d).
) are connected to each other, this connection point is grounded, each gate of this MOS FET (8c) and (8d) is connected to each other, and the connection point of this gate is connected to MO5.
Connected to the drain of PET (8d) and also connected to the MOS
A reference voltage source (9) from which a reference voltage of 3V can be obtained, for example, is connected to the gate of the FIET (8a), and the MOS PET
The connection point of each drain of (8a) and (8c) is connected to the gate of p channel MOS FIET (8e), the source of this MOSFET (8e) is connected to the power supply terminal (4), and the connection point of this MOS FIET (8b) is connected to the gate of p-channel MOS FIET (8e).
) and the drain of the MOS PET (8e) lead out the output terminal (8f).
断る第２図回路に於いては出力端子（８ｆ）に得られる
出力電圧は第３図に示す如（基準電圧源（９）の基準電
圧例えば３ｖに依存し、接地レベルや電源電圧には左右
されない外部電源電圧Ｖｃｃが降圧された例えば３ｖの
定電圧が得られる。In the circuit shown in Figure 2, the output voltage obtained at the output terminal (8f) depends on the reference voltage of the reference voltage source (9), for example 3V, as shown in Figure 3, and is independent of the ground level and power supply voltage. A constant voltage of, for example, 3V is obtained by stepping down the external power supply voltage Vcc that is not used.
また本例に於いてはＭＯＳ Ｆ［！？（７）のソースを
接地し、このＭＯＳ ＦＥＴ １６＞及び（７）の夫々
のドレインを互いに接続し、このドレインの接続点を第
５図と同様の構成のインバータ回路を構成するＰチャン
ネル１、ＭＯＳ ＰＥＴ （１０）及びＮチャ７ネ７
１．ＭＯＳ ＦＩＴ （１１）の夫々のゲートに接続
する。この場合Ｐチャンネル８０ＳＰｆ！Ｔ （６）の
チャンネル幅を１２μｍ、チャンネル長を１．４μ−と
し、ＮチャンネルＭＯＳ ＦＢＴ（７）のチャンネル幅
を６μｍ、チャンネル長を１．２ｖ輪としたとき、この
ＭＯＳ ＩＱ！Ｔ （６）及び（７）が構成するインバ
ータ回路の電源電圧と論理しきい値との関係は第４図に
示す如く例えば電源電圧が３ｖのときは論理しきい値は
１．５ｖであり、電源電圧が２ｖのときは論理しきい値
は１ｖである。Also, in this example, MOS F[! ? The source of (7) is grounded, the respective drains of this MOS FET 16> and (7) are connected to each other, and the connection point of these drains is connected to the P channel 1, which constitutes an inverter circuit having the same configuration as that shown in FIG. MOS PET (10) and N channel 7
1. Connect to each gate of MOS FIT (11). In this case, P channel 80SPf! When the channel width of T (6) is 12 μm and the channel length is 1.4 μ-, and the channel width of N-channel MOS FBT (7) is 6 μm and the channel length is 1.2 V, this MOS IQ! The relationship between the power supply voltage and the logic threshold of the inverter circuit constituted by T (6) and (7) is shown in FIG. 4. For example, when the power supply voltage is 3V, the logic threshold is 1.5V. When the power supply voltage is 2V, the logic threshold is 1V.
このｔｆＯ５ＰＥＴ （１０）のソースを例えば６ｖ
の外部電源電圧が供給される電源端子（４）に接続し、
こノＭＯ５ＦＩＥＴ （１１） （７）’／−２を接
地し、このＭＯＳ ＰＥＴ（１０）及び（１１）の夫々
のドレインの互いの接続点よりＣＭＯＳレベル信号出力
端子（５）を導出し、このＣＭＯＳレベル信号出力端子
（５）に得られるＣＭＯＳレベル信号をＭＯＳ ＬＳＩ
のメモリ等に供給する如（する。For example, set the source of this tfO5PET (10) to 6v.
Connect to the power terminal (4) to which external power supply voltage is supplied,
This MO5FIET (11) (7)'/-2 is grounded, and the CMOS level signal output terminal (5) is derived from the connection point of the respective drains of this MOS PET (10) and (11). The CMOS level signal obtained at the CMOS level signal output terminal (5) is output to the MOS LSI.
such as supplying it to the memory, etc.
このＭＯＳ ＦＩＥＴ （１０）及び（１１）より構
成されるイ 。I is composed of these MOS FIETs (10) and (11).
ンバータ回路の電源電圧と論理しきい値との関係は第６
図に示す如くである。The relationship between the power supply voltage of the inverter circuit and the logic threshold is shown in the sixth
As shown in the figure.
本例は上述の如く初段のインバータ回路（６）（７）を
電圧降圧回路（８）にて降圧した定電圧例えば３ｖで動
作させるので、外部電源電圧Ｖｃｃの変動に関係なく、
論理しきい値は例えば１．５■で一定であり、ＴＴＬレ
ベル信号とのマージンは常に一定となる。In this example, as described above, the first-stage inverter circuits (6) and (7) are operated at a constant voltage, for example, 3V, which is stepped down by the voltage step-down circuit (8), so regardless of fluctuations in the external power supply voltage Vcc,
The logic threshold value is constant, for example, 1.5■, and the margin with respect to the TTL level signal is always constant.
従って、通常時は電源電圧の変動に関係なくこの初段の
インバータ回路（６１（７）の出力側は３■の電源電圧
か接地レベルかが得られるので２段目のインバータ回路
（１０） （１１）の出力端子であるＣＭＯＳレベル
信号出力端子（５）にはＴＴＬレベル入力端子（１）に
供給されるＴＴＬレベル信号に応じたＣ間Ｓレベル信号
が得られる。Therefore, under normal conditions, the output side of the first stage inverter circuit (61 (7)) can obtain either the power supply voltage of 3■ or the ground level, regardless of fluctuations in the power supply voltage, so the second stage inverter circuit (10) (11 ), a C-to-C S level signal corresponding to the TTL level signal supplied to the TTL level input terminal (1) is obtained at the CMOS level signal output terminal (5) which is the output terminal of the CMOS level signal output terminal (5).
また本例に於いては外部電源電圧Ｖｃｃを例えば６Ｖと
し、この電圧降圧回路（８）の降圧定電圧を例えば３ｖ
としたときに於いて、チップ内の接地レベルが例えば１
■上昇したときは、初段インバータ回路［６） （７１
の電源電圧は２■となり、従ってチップ内部から見た論
理しきい値は第４図に示す如く１ｖとなり、外部即ちＴ
ＴＬ側から見たこの論理しきい値は第４図に示す如くこ
の接地レベルの上昇分の１■が加算された２■となるが
、これは↑ＴＬレベル信号のハイレベル信号“１ ”
２．４Ｖ以上とローレベル信号“０” ０．８ｖ以下
とを正確に判別することができる。このときこのインバ
ータ回路（６１（７１の出力側には接地レベルか２Ｖの
電源電圧が得られ、これが２段目のインバータ回路（１
０）（１１）に供給され、このときは、二のインバータ
回路（１０） （１１）の電源電圧Ｖｃｃは５ｖとな
ったことになるが、このときのこの論理しきい値は第６
図に示す如＜ １．５５Ｖであり、この接地レベルの上
昇に係りなく ＴＴＬレベル信号入力端子（１）に供給
されるＴＴＬレベル信号に対応したＣＭＯＳレベル信号
を得ることができる。Further, in this example, the external power supply voltage Vcc is set to, for example, 6V, and the step-down constant voltage of this voltage step-down circuit (8) is set to, for example, 3V.
When the ground level inside the chip is, for example, 1
■When the rise occurs, the first stage inverter circuit [6] (71
The power supply voltage of
As shown in Figure 4, this logical threshold value seen from the TL side becomes 2■, which is the sum of 1■ the increase in the ground level, but this is equal to the high level signal "1" of the ↑TL level signal.
It is possible to accurately discriminate between 2.4V or higher and a low level signal "0" of 0.8V or lower. At this time, a ground level or 2V power supply voltage is obtained on the output side of this inverter circuit (61 (71), and this is the second stage inverter circuit (1
0) (11), and at this time, the power supply voltage Vcc of the second inverter circuit (10) (11) is 5V, but this logic threshold at this time is
As shown in the figure, the CMOS level signal corresponding to the TTL level signal supplied to the TTL level signal input terminal (1) can be obtained regardless of the rise in the ground level.
また本例に於いては電圧降圧回路（８）の出力電圧を初
段のインバータ回路（６） （７１のみ供給するためこ
の電圧降圧回路（８）の電流供給能力は極く小さくてい
いので、その設計、レイアウトは困難はなく、サイズも
小さくてよくチップサイズの増大はほとんどない。In addition, in this example, since the output voltage of the voltage step-down circuit (8) is supplied only to the first-stage inverter circuit (6) (71), the current supply capacity of this voltage step-down circuit (8) may be extremely small. Design and layout are not difficult, and the size is small, with almost no increase in chip size.
向上述実施例に於いては初段回路をインバータ回路（６
１（７） トＬ タが、コノ化わりニＮＯＲ回路、ＮＡ
ＮＤ回路、クロックドインバータ回路等を同様にして用
いることができることは容易に理解できよう。In the improved embodiment, the first stage circuit is an inverter circuit (6
1 (7) NOR circuit, NA
It is easy to understand that ND circuits, clocked inverter circuits, etc. can be used in the same way.
また本発明は上述実施例に限ることなく本発明の要旨を
逸脱することなく、その他種々の構成が取り得ることは
勿論である。Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.
本発明に依れば外部電源電圧の変動やＭＯＳ ＬＳＩの
チップ内部の接地レベルの上昇に係りなく、ＴＴＬレベ
ル信号をＣＭＯＳレベル信号に良好に変換することがで
きる利益がある。According to the present invention, there is an advantage that a TTL level signal can be successfully converted into a CMOS level signal regardless of fluctuations in the external power supply voltage or increases in the ground level inside the MOS LSI chip.
第１図は本発明信号レベル変換回路の一実施例を示す構
成図、第２図は電圧降圧回路の例を示す接続図、第３図
、第４図及び第６図は本発明の説明に供する線図、第５
図は従来の信号レベル変換回路の例を示す構成図である
。
（１）はＴＴＬレベル信号入力端子、（４）は電源端子
、（５）はＣ？ＩＯＳレベル信号出力端子、（６）及び
（７）はインバータ回路を構成するＭＯＳ ＦＥＴ 、
＋８１は電圧降圧回路である。
本糞明ｊｉ９ＬｓＬ炎５（回鋒句１デ１第１因
電圧降圧−回ｋｑイ列
第２図
電涯電圧Ｖｃｃ
第３図
第４図
第５図
電環電ＪＥ Ｖｃｃ
第８図FIG. 1 is a block diagram showing an embodiment of the signal level conversion circuit of the present invention, FIG. 2 is a connection diagram showing an example of a voltage step-down circuit, and FIGS. 3, 4, and 6 are for explaining the present invention. Diagram provided, No. 5
The figure is a configuration diagram showing an example of a conventional signal level conversion circuit. (1) is TTL level signal input terminal, (4) is power supply terminal, (5) is C? IOS level signal output terminal, (6) and (7) are MOS FETs forming an inverter circuit,
+81 is a voltage step-down circuit. Main article ming ji9LsL flame 5 (circulation phrase 1 de 1 1st factor voltage drop - kq i column 2 figure 2 electric wire voltage Vcc figure 3 figure 4 figure 5 electric ring electric JE Vcc figure 8
Claims (1)
レベル変換回路に於いて、上記ＴＴＬレベル信号が供給
される初段回路を外部電源電圧を電圧降圧回路にて降圧
した定電圧で動作させる様にしたことを特徴とする信号
レベル変換回路。In a signal level conversion circuit that converts a TTL level signal into a CMOS level signal, the first stage circuit to which the TTL level signal is supplied is operated with a constant voltage obtained by lowering the external power supply voltage using a voltage step-down circuit. Features a signal level conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62142447A JPS63305616A (en) | 1987-06-08 | 1987-06-08 | Signal level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62142447A JPS63305616A (en) | 1987-06-08 | 1987-06-08 | Signal level conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63305616A true JPS63305616A (en) | 1988-12-13 |
Family
ID=15315522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62142447A Pending JPS63305616A (en) | 1987-06-08 | 1987-06-08 | Signal level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63305616A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0260160A (en) * | 1988-08-26 | 1990-02-28 | Hitachi Ltd | Complementary mos integrated circuit and electronic device, electronic computer, and memory device using the same |
| JPH04351791A (en) * | 1991-05-24 | 1992-12-07 | Samsung Electron Co Ltd | Data input buffer for semiconductor memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58116817A (en) * | 1981-12-21 | 1983-07-12 | モトロ−ラ・インコ−ポレ−テツド | Ttl-c-mos input buffer |
| JPS62142416A (en) * | 1985-09-19 | 1987-06-25 | エキシリンク，インコ−ポレイテツド | Ttl/cmos applicable input buffer |
-
1987
- 1987-06-08 JP JP62142447A patent/JPS63305616A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58116817A (en) * | 1981-12-21 | 1983-07-12 | モトロ−ラ・インコ−ポレ−テツド | Ttl-c-mos input buffer |
| JPS62142416A (en) * | 1985-09-19 | 1987-06-25 | エキシリンク，インコ−ポレイテツド | Ttl/cmos applicable input buffer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0260160A (en) * | 1988-08-26 | 1990-02-28 | Hitachi Ltd | Complementary mos integrated circuit and electronic device, electronic computer, and memory device using the same |
| JPH04351791A (en) * | 1991-05-24 | 1992-12-07 | Samsung Electron Co Ltd | Data input buffer for semiconductor memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5521547A (en) | Boost voltage generating circuit | |
| US4612462A (en) | Logic circuit having voltage booster | |
| JP2549743B2 (en) | Output circuit | |
| JP2758259B2 (en) | Buffer circuit | |
| JP3123463B2 (en) | Level conversion circuit | |
| US6977523B2 (en) | Voltage level shifting circuit | |
| US6084459A (en) | Voltage level shifting circuit | |
| JPH0436606B2 (en) | ||
| JPH0728207B2 (en) | CMOS drive circuit | |
| JP3760104B2 (en) | Boost voltage generator | |
| JPS63305616A (en) | Signal level conversion circuit | |
| US6456122B1 (en) | Input buffer circuit for transforming pseudo differential signals into full differential signals | |
| JPH04341009A (en) | Semiconductor integrated circuit device | |
| JP2654275B2 (en) | Bidirectional buffer | |
| US20070052468A1 (en) | Shift down level shifter | |
| JP3586985B2 (en) | Output circuit of semiconductor device | |
| KR960010572B1 (en) | Data output buffer using level converter circuit | |
| JP3055505B2 (en) | Level conversion circuit | |
| JP3170923B2 (en) | Semiconductor integrated circuit | |
| JP2000209056A (en) | Mos operational amplifier with differential pair protecting function | |
| JPH06197001A (en) | Level conversion circuit | |
| JPH02273393A (en) | Boosting signal generating circuit | |
| JPH07122991A (en) | Switching step | |
| JP3711075B2 (en) | Output buffer circuit and input / output buffer circuit | |
| JP2002300024A (en) | Booster circuit |