JPS63305462A - Digital signal processor - Google Patents

Abstract

PURPOSE:To easily set up an optimum signal level by sending an output signal from an overload detecting circuit and an output signal from an overflow detecting circuit to an output terminal through on OR circuit. CONSTITUTION:A signal generated from an overflow detecting circuit OVF due to an overflow of an accumulator ACC when the ACC generates overflow and sent to an output terminal (y) is also supplied to OR circuits OR1, OR2. Even if the outputs of overload detecting circuits OL1, OL2 are unfixed when the ACC generates overflow, the output signal of the OVF due to the overflow of the ACC is sent to an output terminal (x). Consequently, the optimum signal level can be easily set up.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to digital signal processors.

(Prior Art) It is well known that digital signal arithmetic devices are widely used in various devices in many technical fields. By the way, if the calculation result of a digital signal calculation device overflows, subsequent calculations become meaningless, so conventional calculation devices have traditionally stopped the calculation when the calculation result has overflowed, and also stopped the calculation from overflowing. The state is detected and the state is displayed on a display device.

(Problem to be Solved by the Invention) By the way, in the conventional arithmetic device, an overflow condition is detected and displayed only when an overflow occurs in the arithmetic result of the arithmetic device. Therefore, there were problems in that it was difficult to predict the occurrence of overflow, and it was also not easy to set the optimal signal level of the signal that was the subject of signal processing.

The above problem becomes a particularly serious problem when, for example, in signal processing in consumer digital audio equipment, it is desired to supply an input signal to the equipment at an appropriate signal level.

Therefore, an overflow warning level is set to detect whether or not the output signal data of the accumulator has entered a predetermined area set in advance for the output signal data of the accumulator (whether or not an overload state has occurred). Attempts have been made to provide detection means to prevent such problems from occurring.

By the way, the overflow warning level detection means (overload detection means) for detecting whether or not the output signal data of the accumulator is in an overload state can be obtained by multiplying the output signal data of the accumulator by a predetermined coefficient, for example. Measures may be taken to check whether the data being stored overflows.

Even in the case of an overload detection means that multiplies the output signal data of an accumulator by a predetermined coefficient and checks whether the data obtained is in an overflow state, the accumulator used therein is protected against overflow protection. If it is, the overflow warning level can be detected without any problem, but check whether the data obtained by multiplying the output signal data of the accumulator by a predetermined coefficient is in an overflow state. In the case of the overload detection means described above, if the accumulator used in it is not overflow protected, and if we consider a state in which the accumulator has overflowed, the output of the accumulator at this time is Since the data obtained by multiplying the signal data by a predetermined coefficient is random, even if the accumulator is actually in an overflow state, the state of the output of the overflow warning level detection means at this time is uncertain. The output will be unreliable.

Therefore, as accumulators without overflow protection have come to be used frequently, a solution to the above-mentioned problems has been sought.

(Means for Solving the Problems) The present invention is configured to perform digital signal processing according to instructions sequentially read out from a program memory, and includes at least a multiplication operation in which coefficient data and digital signal data are multiplied. a digital signal processor comprising: an overflow detection means for output signal data of an accumulator that accumulates output signal data from the multiplier; and means for detecting an overflow warning level of output signal data from the accumulator; The above-mentioned problems can be solved by providing a digital signal processor comprising means for obtaining an OR output of an output signal from the overflow detection means and an output signal from the overflow warning level detection means. It is resolved.

(Example) Hereinafter, with reference to the attached drawings, the digital signal and
The specific contents of the processor will be explained in detail. 1 and 2 are block diagrams of respective embodiments of the digital signal processor of the present invention.

First, in the block diagram of an embodiment of the digital signal processor (DSP) of the present invention shown in FIG. 1, a is an input terminal for a digital signal (serial data); is a digital signal to be subjected to predetermined signal processing, for example, NRZ which is a PCM signal.
A signal is provided.

In Figure 1, SDI is a serial data input circuit, IB is an input buffer sofa, N(, -RAM is a coefficient RAM,
TB is a transfer buffer, PCD is a parameter control unit, P-
RAM is a program RAM, SD○ is a serial data output circuit, SCI is a serial code interface, D-RAM is a data RAM, and FN-R
OM is constant memory ROM, MUL is multiplier, ACC
is an accumulator, REG is a register with a shifter, OB is an output buffer, OLI, ○L2 is an overload detection circuit, SFT, 5FTI is a shift circuit, OVF is an overflow detection circuit, ○R1 and OR2 are OR circuits, xi, x
2 is the output terminal of the output signal of the overload detection circuit, y
is an output terminal for the output signal of the overflow detection circuit.

The program RAM (P-RAM) described above stores in advance a program to be executed by the digital signal processor DSP, and functions as a coefficient memory by storing data such as predetermined multiplication coefficients.
C-RAM), these data are supplied to the multiplier MUL.

The serial code interface SCI is equipped with a serial code input terminal C and a serial code output terminal d, and receives clock signals and synchronization signals (LRCK, LRC) supplied from the serial code timing input terminal e.
Data (SD, SD') is input from the serial code input terminal C and data (SD, SD') is output from the serial code output terminal d by means of the serial code input terminal C (K bar).

The parameter control unit PCD described above has a serial code.
Program RA with data from interface SCI
M (P-RAM) and the transfer buffer TB for identification and sending, and the transfer buffer TB outputs control signals 'I's and Tw specifying the transfer timing and number of transfers.
g is a trigger input terminal of the parameter control unit PCD.

When a trigger (synchronization signal) input is supplied from the outside to the trigger input terminal g, the parameter control unit PCD can generate a control signal Ts whose transfer timing is determined by the trigger input. However, the parameter control unit PCD has a function that allows it to be triggered by data (SD, SD') even if no external trigger input is supplied to the terminal g. There is.

The serial data input circuit SDI converts the input data from the serial data input terminal a into serial/parallel data and supplies it to the data RAM (D-RAM) via the input buffer IB. In order to determine the timing of serial data output, the serial data input circuit SDI and the serial data output circuit SD○
This is an input terminal for the data clock signal BC:LK and the channel identification signal LRCK that are supplied to the input terminal.

When a central processing unit (CPU) (not shown) sends predetermined coefficient data for calculation from the serial code input terminal C of the digital signal processor DSP in the R8232C serial format, for example, the predetermined coefficient for the calculation is sent. Data is sent to the transfer buffer TB via the serial code interface SCI and the parameter control unit PCD.

A start signal indicating the start of serial code transfer is applied from the serial code transfer section to the input terminal of the serial code interface SCI. Further, a clock signal that determines the program instruction cycle of the digital signal processor DSP described above is supplied to the clock input terminal f.

A clock signal generated by a clock signal generation circuit (not shown) that generates a clock signal with a frequency corresponding to the transfer speed of a serial transfer unit (not shown) is connected to the serial code interface SCI of the digital signal processor DSP. The code timing signal is supplied to the input terminal e.

Predetermined arithmetic processing on digital signals in the digital signal processor DSP is carried out by the central processing unit! (
Needless to say, the digital signal processor DSP is controlled by a constant memory ROM (FN-ROM), a multiplier MUL, and an accumulator ACC.

Predetermined arithmetic processing is performed on signals in circuit components such as the shifter register REG, the shift circuit SFT, the output buffer OB, and the data RAM (D-RAM).

In the digital signal processor DSP of the embodiment shown in FIG. 1, output signal data accumulated by one multiplier MUL and accumulated by an accumulator ACC is serially transmitted via a shift circuit SFT and an output buffer OB.
The data is supplied to the data output circuit SDO, and outputted from the serial data output circuit SDO to the output terminal, and the output signal data of the accumulator ACC is supplied to the overflow detection circuit OVF. The output signal data of the accumulator ACC is supplied to the overload detection circuit ○L1.

In the block diagram shown in FIG. 1 and the block diagram shown in FIG. This is a component that is intended to have the same function as the overload detection circuit OLI indicated by a solid line frame in the block diagram shown in FIG. 2, which will be described later. This may be done by the components shown in solid lines or by the components shown in dotted lines.

As mentioned above. Overload detection circuit 0LI (or ○L
2) is a data preset function for comparing with the cumulative value of each data in the accumulator ACC described above, and a data preset function for comparing the accumulated value of each data in the accumulator ACC, and the data preset in the overload detection circuit ○Ll (or 0L2) and the above-mentioned accumulator AC.
It is configured to include a comparator for comparing the output data from the accumulator ACC and the output signal data in the accumulator ACC and the data preset in the overload detection circuit 0L1 (or 0L2). As a result of the comparison, when the accumulated value in the accumulator ACC falls within a predetermined margin area set for a true overflow state in the output signal data of the accumulator ACC, the output signal is transferred to the terminal XI.
(or x2).

As mentioned above, the comparator for comparing with the output data supplied from the accumulator ACC is designed to detect positive and negative overloads respectively when entering the margin area for overflow prevention. , the signal level of the output signal data of the accumulator ACC, that is, the absolute value data, can be compared using positive and negative data.

As mentioned above, overload detection circuit 0LI (OL2)
The signal outputted to the output terminal X1 (X2) is supplied to, for example, a display section and visually displayed on the display of one display section.

In the digital signal processor shown in FIG. 1 configured as described above, the output signal of the overload detection circuit OLI and the overflow detection circuit OV are
The output signal of F is the output terminal x1 via the OR circuit ORI.
(or the output signal of overload detection circuit OL2 and the output signal of overflow detection circuit OVF are sent to output terminal x2 via OR circuit OR2)
.

Therefore, in the digital signal processor shown in the first diagram, the accumulator ACC used therein is not overflow protected, and moreover, the overload detection circuit 0LI (OL2) used is , accumulator ACC
If the configuration is such that it is checked whether the data obtained by multiplying the output signal data of AC by a predetermined coefficient is in an overflow state, the accumulator AC
Even in the state where C has overflowed, the signal generated by the overflow detection circuit ○VF due to the overflow of the accumulator ACC and sent to the output terminal y is also supplied to the OR circuit 0RI (or 0R2). Overload detection circuit ○L when accumulator ACC has overflowed
Even if the output of 0L2 (or 0L2) is undefined, the output signal of the overflow detection circuit OVF due to the overflow of the accumulator ACC is sent to the output terminal XI (X2). The problems described above do not occur.

Next, the embodiment shown in the second figure will be described. In the digital signal processor shown in FIG.
a is a multiplier, MUX is a multiplexer, PC is a program counter, DP is a data memory page pointer, ARP is an auxiliary register pointer, ALU is an arithmetic logic unit, ACC is an accumulator, ○Ll, OL2
is an overload detection circuit, 1,5FTI is a shift circuit, OVF is an overflow detection circuit, ORI, OR2 is an OR circuit, Xi, X2 are output terminals for the output signal of the overload detection circuit, y is an output terminal for the output signal of the overflow detection circuit. It is an output terminal.

In the digital signal processor DSP of the embodiment shown in FIG. At the same time, the output signal data of the accumulator ACC is supplied to the overflow detection circuit OVF, and the output signal data of the accumulator ACC is supplied to the overload detection circuit OLI.

As mentioned above. Overload detection circuit 0LI (or 0L
2) is a data preset function for comparing with the cumulative value of each data in the accumulator ACC described above, and a data preset function for comparing the accumulated value of each data in the accumulator ACC, and the data preset in the overload detection circuit 0Ll (or ○L2) and the accumulator AC described above.
It is configured to include a comparator for comparing the output data from the accumulator ACC and the data preset in the overload detection circuit 0LI (or 0L2). According to the comparison result, when the accumulated value in the accumulator ACC falls within a predetermined margin area set for a true overflow state in the output signal data of the accumulator ACC, the output signal is sent to the terminal xi.
(or In order to detect each load, a device is used which is configured so that the signal level of the output signal data of the accumulator ACC, that is, the absolute value data, can be compared using positive and negative data.

As mentioned above, overload detection circuit 0LI (OL2)
The signal outputted to the output terminal xi (x2) is supplied to, for example, a display section to visually display it on the display of one display section.

In the digital signal processor shown in FIG. 2 configured as described above, as in the case of the digital signal processor shown in FIG. The output signal of the detection circuit OVF is sent to the output terminal Xl via the OR circuit ORI (or the output signal of the overload detection circuit OL2 and the overflow detection circuit OV
The output signal of F is the output terminal x2 via the OR circuit ○R2.
), the accumulator ACC used there is not overflow protected, and the overload detection circuit 0LI (OL2) used is
If the configuration is such that it is checked whether the data obtained by multiplying the output signal data of AC by a predetermined coefficient is in an overflow state, the accumulator AC
Even in the state where C has overflowed, the signal generated by the overflow detection circuit OVF due to the overflow of the accumulator ACC and sent to the output terminal y is output to the OR circuit 0RI (or ○OLl(OL2)R2
) is also supplied to the accumulator AC
Even if the output of the overload detection circuit 0L1 (or 0L2) is undefined in a state where C has overflowed, the output signal of the overflow detection circuit OVF due to the overflow of the accumulator ACC is output from the output terminal
Since the signal is sent to I(X2), the above-mentioned problem does not occur in the digital signal processor shown in the second diagram.

(Effects of the Invention) As is clear from the detailed explanation above, there are two digital signal processors of the present invention.

A digital signal processor configured to perform digital signal processing in response to instructions sequentially read from a program memory, and comprising at least a multiplier for multiplying coefficient data and digital signal data, Overflow detection means for output signal data of an accumulator that accumulates output signal data from the multiplier; means for detecting an overflow warning level for output signal data of the accumulator; and an output signal from the overflow detection means. Since the digital signal processor of the present invention is provided with means for obtaining an OR output with the output signal from the overflow warning level detection means, the output signal of the overload detection circuit and the overflow detection circuit are provided. Since the output signal of the circuit is sent to the output terminal is configured to check whether the data obtained by multiplying the output signal data of the accumulator ACC by a predetermined coefficient is in an overflow state, and when the accumulator ACC has overflowed, Also, the signal generated by the overflow detection circuit OVF and sent to the output terminal y due to the overflow of the accumulator ACC is also supplied to the OR circuit, so that when the accumulator ACC overflows, the overload detection circuit is Even if the output is undefined, the output signal of the overflow detection circuit OVF due to the overflow of the accumulator ACC is sent to the output terminal There is no.

[Brief explanation of drawings]

1 and 2 are block diagrams of respective embodiments of the digital signal processor of the present invention. a...digital signal input terminal, b...output terminal,
X...output terminal, MUL, MULa...multiplier, M
UX...multiplexer, SDI...serial data input circuit, IB...input buffer, NC-RA
M...Coefficient RAM, TB...Transfer buffer, PCD
...Parameter control unit, P-RAM...Program RAM, SD○...Serial data output circuit, SC
I...Serial code interface, D-RA
M...Data RAM, FN-ROM...Constant memory ROM, ACC...Accumulator, REG...
・Register with shifter, OB...output buffer, OVF
...Overflow detection circuit, PC...Program counter, DP...Data memory page pointer, ARP...Auxiliary register pointer, ALU...
・Arithmetic logic unit, OLI, OL2... Overload detection circuit, SFT, 5FTI, 1... Shift circuit, OR1°OR2... OR circuit,

Claims (1)

[Claims] The digital signal processor is configured to perform digital signal processing in response to instructions sequentially read from a program memory, and includes at least a multiplier for multiplying coefficient data and digital signal data. Overflow detection means for the output signal data of an accumulator that accumulates output signal data from the multiplier; means for detecting an overflow warning level for the output signal data of the accumulator; and an output signal from the overflow detection means and the A digital signal processor comprising means for obtaining an OR output with an output signal from an overflow warning level detection means.