JPS63302626A - Digital pll circuit - Google Patents

Abstract

PURPOSE:To suppress the adverse effect of peak shift, etc., by correcting the boundary position of a phase error detecting range corresponding to an interval from the edge of an input signal to the next edge. CONSTITUTION:For example, a signal SIN reproduced from a recording medium and waveform-equalized is supplied to a phase error detection circuit part 10 which forms a digital PLL circuit with an output clock generation circuit 20 and a periodical data detection circuit part 30, etc., and the edge of the waveform of the signal is detected at an edge detection circuit 11. And the interval from the edge of the signal SIN to the next edge is latched at a shift register via a latch circuit 13. Area selection circuits 14a and 14b are controlled corresponding to the interval, and a PLL processing is performed after the boundary position of the phase error detecting range is corrected according to statistics corresponding to the interval of the edge based on the statistical data of a position numeral conversion circuit 15. As a result, the adverse effect of the peak shift, etc., can be suppressed, and the generation of an error can be reduced.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C0 Prior art 1 Problems to be solved by the invention E1 Means for solving the problems F1 Effects G. Example G-1. Overall structure of the example ( (Fig. 1) G-2, Explanation of peak shift (Fig. 2, Fig. 3) G-3, Specific example of one cycle period calculation circuit (Fig. 4) G-4,
Specific example of edge detection circuit (Fig. 5) G-5, Operational explanation of the embodiment (Fig. 6) H9 Effect of the invention A, Industrial application field The present invention is applicable to PLL (phase locked loop) operation. Regarding digital PLL circuits,
In particular, the present invention relates to a digital PLL circuit that can perform highly accurate phase error detection even when so-called code amount interference, peak shift, etc. occur in an input signal.

B0 Summary of the Invention The present invention obtains pulse period data based on phase error detection data between the final output clock and input signal and period detection data of the output clock, and converts this pulse period data into a master clock having a constant frequency. In a digital PLL circuit that counts and generates an output clock pulse,
By correcting the phase error detection range according to the length of the interval from one edge of the input signal to the next edge, it is possible to prevent negative effects such as so-called peak shifts and reduce edge position detection errors. .

C1 Conventional technology When reading data from a signal (input signal) obtained by transmitting, recording, or reproducing a digital signal, a clock (so-called pit clock) is used to extract bits.
is required to be synchronized. In order to obtain a clock signal that is synchronized with such an input signal, the PL
An L (phase locked loop) circuit is used. In recent years, a digital PLL circuit has been proposed in which the internal operation of the PLL circuit is performed digitally. This digital PLL circuit generally counts and detects the time difference or so-called phase error between the edge (transient) of an input signal and an output clock generated inside the circuit with the precision of a high-speed mask clock, and The phase of the output clock from the input signal is controlled to synchronize it with the clock (pit clock) of the input signal.

The master clock in this case is usually the above-mentioned clock.

A frequency that is at least one order of magnitude higher than that of a standard clock is required.

D0 Problems to be Solved by the Invention Incidentally, the digital signal supplied via the transmission system including the recording/reproducing system is input to the PLL circuit after being subjected to sufficient waveform equalization. The equalization at this time is not perfect due to the limits of the equalizer's characteristics and nonlinear distortion, and the signal input to the PLL circuit contains distortion and noise that can cause various errors. There is. Waveform analysis has revealed that among the distortions contained in such human signals, the ones that are most likely to cause errors are code amount interference and peak shifts that cannot be corrected by an equalizer.
In particular, when digital magnetic recording/reproduction is performed on a magnetic recording medium, the influence of peak shift appears significantly.

This peak shift becomes noticeable when a short edge (transient) interval and a long edge interval are adjacent to each other, as shown in FIG.

In FIG. 7, when the recorded signal waveform S□ recorded on the recording medium is reproduced by a magnetic head or the like, a so-called peak shift occurs, so that, for example, the reproduced signal S□ as shown in FIG. This reproduced signal is equalized by an equalizer to produce an equalized output signal S! , is obtained. This signal s
The edges of the signal S obtained by waveform-shaping in by a limiter or the like will be deviated from the edges of the recorded waveform 5lte. Movement of signal edges due to such peak shifts is accompanied by jitter, noise, reproduction level fluctuations, etc., and is often mistakenly judged as an edge at an adjacent clock position.

In addition, in the case of a digital PLL circuit, the input signal is first
Since it is sampled by the master clock inside the LL circuit, there is a time error within the width of the mask clock cycle. That is, in FIG. 8, when the internal master clock of the PLL circuit is CK□ and its cycle is To, when input signals Sts+ and Sxwz as shown in FIG. By sampling the input signal with the master clock, the signal S■8.531P! of FIG. 8 is obtained. is assumed to have been input. This is each human input signal 5INI before sampling.
Between each edge spacing of %S+ni, approximately 2T
□Even though there is a slight difference (TPl is the above-mentioned mask cropper period), each sampled signal S
, □, sx, and 4r□ are considered to have the same edge interval, resulting in a time error of a little less than about 2T□. For this reason, there is a possibility that the error caused by the peak shift and the like will further increase, and the adverse effects of the peak shift will be further amplified.

The present invention has been made in view of these circumstances, and even when edge shifts occur in a waveform equalized signal due to code amount interference or peak shifts, the present invention prevents erroneous detection of edge positions and prevents adverse effects. The purpose of the present invention is to provide a digital PLL circuit that can perform the following functions.

Means for Solving the E1 Problem In order to solve the above-mentioned problems, the digital PLL circuit according to the present invention obtains pulse period data based on phase error detection data and output clock period data, and calculates the pulse period from this pulse period data. An output clock generation circuit generates an output clock pulse every time data is counted by a master clock of a constant frequency, and a phase error between the output clock from this output clock generation circuit and the edge detection signal of the input signal is detected. a phase error detection circuit that sends the obtained phase error detection data to the output clock generation circuit; and an output clock that obtains output clock period data from the output clock generation circuit and sends this output clock period data to the output clock generation circuit. Zhou! The phase error detection circuit has an area select circuit that selects a phase error detection range of the edge detection signal of the input signal with respect to the output clock, and the area select circuit The present invention is characterized in that the selection range is changed in accordance with the pulse interval of the edge detection signal of the input signal.

By correcting the boundary position of the phase error detection range according to the F0 action edge interval, even if edge deviation occurs due to peak shift, etc., the adverse effects of this can be minimized.

G. Embodiments Hereinafter, embodiments of the digital PLL circuit according to the present invention will be described with reference to the drawings.

G-1, Overall configuration of the example (Fig. 1) FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

In FIG. 1, a signal SIN reproduced from, for example, a recording medium and whose waveform has been equalized is supplied to an input terminal 1 of a phase error detection circuit section IO. This input signal S0 has a pit clock frequency fs of, for example, 9.4 MHz, and edges (transients) of the signal SIN are obtained at intervals of an integral multiple of the period T'st of this bit clock. This input signal 5l11 is applied to the edge detection circuit 11.
The edges of the signal waveform are detected. The output from this edge detection circuit 11 is transmitted to the shift register 12.
The phase error is detected by passing through the latch circuit 13, area select circuits 14a, 14b, position/value conversion circuit 15, and filter 16.

Input terminal 2 receives the frequency f, a frequency 1 which is an integral multiple of a.
□, for example, a high-speed master clock CK, s of 56.4 MHz (=6 fat) is supplied. This mask clock CK+*s is sent to the edge detection circuit 11 and shift register 12 of the phase error detection circuit section 10, and is also sent to the counter 21 of the output clock generation circuit section 20 that generates the final output clock CK OUT. It will be done. The count output from this counter 21 is sent to a comparator 22.
The data is sent to the comparator 22 where it is compared with the variable cycle accumulated data from the adder 23. This adder 23 adds three inputs, and is configured to perform cumulative addition by returning the addition output to one input via the launch circuit 24. The other two inputs of the three-input adder 23 are the phase error detection circuit section 10.
Phase error correction data from and period data detection circuit section 3
The output clock period data detected at 0 is supplied.

The periodic data detection circuit section 30 receives the output clock CKoo.
Period T of t. This is to detect u7, and conventionally, the pulse interval (tJX]F of the output clock CKouy
The period T is determined by counting the number of pulses of the mask clock OK and Is in the mask clock OK and Is (within J). UT is detected, but
In the embodiment of the present invention, the output clock CKou
period ΣTOIIT for a predetermined number N (N is a natural number of 2 or more) of pulses of t (to simplify the explanation, N-Tou
By counting the period (denoted as T) using the mask clock CK,s and multiplying the count value by 1/N, the period detection accuracy (or resolution) is substantially increased by N times.

That is, by sending the output clock CKOUT (frequency f.uT) from the output clock generation circuit section 20 to the periodic data detection circuit section 30 ON counter (or 1/N frequency divider) 31, the frequencies fl, L+, A count output with a frequency of 1/N times (the period is N-To, J) is obtained, and this count output is sent to the zero clear terminal (reset terminal) of the counter 32.20 Counter 32
is supplied with the master clock CKxs, and the number of pulses of the master clock CK, 4s, during the period N-Tour of the count output is counted.

The count output from this counter 32 is the period T of the output clock CKoua in units of the mask clock CK□. It is measured over a period N times longer than LIT,
By multiplying this count output value by 1/N, output clock cycle data can be obtained.

Here, by setting N of the N-adic counter 31 to a value that is a power of 2, such as 21' (n is a natural number), the calculation of 1/N times the count output value from the counter 32 is performed in bits. - All that is required is a shift operation or a change in the position of the decimal point for parallel output data.For example, if the base number N of the counter 31 is set to 16 (=2'), the count output value from the counter 32 is multiplied by l/16. In order to do this, the lower 4 bits can be regarded as the value below the decimal point.

The output clock period data (data of 1/16 of the count output value) from the counter 32 thus obtained is sent to the adder 23 of the output clock generation circuit section 20 via the launch circuit 33.

Regarding the data handled by this adder 23, for example, the upper 4 bits of 8-bit parallel data are regarded as the integer part and the lower 4 bits are regarded as the decimal part, and the data of the upper 4 bits of the integer part are sent to the comparator 22 I try to send only

Further, the area select circuits 14a and 14b in the phase error detection circuit section 10 correspond to a range of one cycle of the clock as a range in which a phase error is to be detected among the parallel data obtained from the latch circuit 13. These area select circuits 14a and 14b select data.
The output from the JK flyprop 18 is sent via an OR circuit 17. The clock input terminal of this JK flip-flop 18 is supplied with the output clock CKout, and the Q output of the JK flip-flop 18 becomes the reproduced data output.

Here, the area select circuits 14a and 14b include 1
Output data from the period arithmetic circuit 19, ie, data indicating the range for one period which is the detection range of the phase error, is supplied. This one-cycle period calculation circuit 19 basically adds or subtracts % of the output clock cycle data from the launch circuit 33 to the output of the adder 23 to obtain the one-cycle period range (phase error detection range). In the embodiment of the present invention, the detection range data is changed depending on the edge interval of the input signal. This is to prevent the adverse effects caused by the peak shift described above, and the boundary of the phase error detection range is corrected in consideration of the nature of the shift in the signal edge when the peak shift occurs.

G-2. Explanation of peak shift (Figures 2 and 3) Here, regarding the deviation of the edge (zero cross) of the signal when the above peak shift occurs, Figure 2 and 3'vI
This will be explained with reference to J. The waveforms W1, W! in these FIGS. 2 and 3 are , W3 and W4, the time interval between the edges of the original recording signal waveform is T1.2 cm, respectively.
t, 3Tit and 4Tl.

(Twy is the above-mentioned bit clock period), and the times corresponding to the edges (zero crosses) of the above-mentioned original signal are indicated by t and -t in the figure.

It is shown in

First, FIG. 2 shows a waveform that has been ideally equalized, and in this case, the time interval of edges is equal to the above-mentioned visit clock frequency! I
The above time T1 is an integer multiple of JlT□.
Each time in the interval 1. -1. Equalization is performed to obtain the zero crossing of the signal at , and the peak shift is corrected. However, in reality, a peak shift as shown in FIG. 3 occurs, so the edge interval of the equalized signal deviates from a value that is an integer multiple of the period T, a, and the zero crossing of the signal occurs at each of the times t and a. Regarding the edge deviation at this time, which deviates from ~t, the average value of the amount of deviation with respect to the original edge position shows a predetermined tendency depending on the length of the edge interval. That is, in FIG. 3, when the original edge interval is, for example, Lt, the average value Pb of the falling zero-crossing point of the reproduced signal equalized waveform W1 appears later than time t, but when the edge interval is 2 teeth, 7. 3T,? ,4T,?
As the length increases, the average of each falling zero crossing point is 4ftpc, as shown in the waveform W, ,W, ,W,
pa and p appear gradually earlier than the respective times tc, t4, and t.

Here, the detection range (or the edge interval of the input signal) for detecting the edge shift (corresponding to a phase error) between the input clock and the output clock of the PLL is generally kTst.
(k+1)Tst (k is a natural number), rather than mechanically assigning a range of S4Tmt before and after each of the above reference times ~t. The margin against false detection will be larger if the boundaries of the detection range are set while being adjusted according to the time from the previous edge until the next edge is obtained. Specifically, as will be described later, the PLL determines whether the edge interval of the input signal is T'st or 27 mA.
The boundary for distinguishing on the side is set later than the standard, and the edge interval is set to 27. A and 3Tat, or 3T1 and 4Ts
The boundary for distinguishing from t may be set earlier than the standard.

G-3. Specific example of one-cycle calculation circuit (Fig. 4) In order to realize the above operation, the one-cycle calculation circuit 19 in Fig. 1 has a specific configuration as shown in Fig. 4, for example. have.

In FIG. 4, the two-man power adder 91 is supplied with an 8-bit addition output from the adder 23 and an 8-bit starting output from the latch circuit 33 of the periodic data detection circuit section 30. , these are subjected to 8-bit digital addition and supplied to a two-man adder 92. Further, the counter 93 has a clock input terminal supplied with the output clock CKouy from the comparator 22, and a clear terminal supplied with the output from the OR circuit 17. This counter 93 detects an edge in the input signal and performs an OR operation.
The output clock CKo is cleared every time an output is obtained from the circuit 17. Since it is incremented every i, the count output is the time measured from the previous edge using the output clock CKout as a unit. The count output from this counter 93 is sent to a peak shift correction amount generation circuit 94 consisting of a ROM or a logic circuit. The peak shift correction amount generation circuit 94 outputs data for correcting the phase error detection range according to the edge interval, and the two-man power adder 92 outputs data for correcting the phase error detection range.
is supplied to the other input terminal of

This adder 92 adds the reference phase error detection range boundary position data from the adder 91 and the detection range correction data from the peak shift correction amount generation circuit 94, and outputs the addition output as follows: The area select circuit 14a is connected to the area select circuit 14a via the area select control circuit 95.
, 14b.

G-4. Specific Example of Edge Detection Circuit (FIG. 5) Next, a specific example of the edge detection circuit 11 will be described with reference to FIG.

In FIG. 5, the input signal S0 from the terminal l is level-discriminated by a comparator 111 having a predetermined dark value level (for example, 0 level) and subjected to so-called waveform shaping. .11
3'f is supplied to the 4-connection circuit. As each clock of these flip-flops 112 and 113, the terminal 2
The above-mentioned master clock CK,s (frequency rsi, period T□) from
It is obtained with a delay of T□. Therefore, each Q output of these flip-flops 112 and 113 is
By sending the signal to an OR circuit (hereinafter referred to as an ExOR circuit) 114 and performing an exclusive OR, a pulse with a width T0 (so-called edge detection pulse) is obtained at a change point of the human input signal, that is, at an edge position.

Although the output from the ExOR circuit 114 may be used as it is as an edge detection signal, in the example shown in FIG. I have to. This false edge removal circuit section 119 is for removing false edges caused by exceeding the above-mentioned 0 level when the input signal level fluctuates due to instantaneous noise pulses or the like. Such noise pulses are generally whisker-like and have an extremely narrow pulse width (considering that it is sufficiently narrower than the bit clock period Tl?, the interval between the edge detection pulses from the ExOR circuit 114 is shorter than the period Tl?). When it is sufficiently short, it is determined that this is the above-mentioned false edge and is removed.

In the 51i12I-th false edge removal circuit section 119, three flip-flops 115 to 11 are cascade-connected.
Using the 7 and 3-input AND circuit 118, for example, when an edge detection pulse is obtained continuously over two clocks of the master clock CK, it is determined to be the above-mentioned false edge and this is removed. That is, by calculating the logical sum of the inverted output of the first-stage flip-flop 115, the output of the second-stage flip-flop 116, and the inverted output of the third-stage flip-flop 117, two consecutive clocks are generated from the ExOR circuit 114. This can be removed when the edge detection pulse is applied. Here, when the presence of a pulse corresponds to "1" and the absence thereof corresponds to "0", the 2-clock continuous pulse signal from the ExOR circuit 114 can be expressed as "...ootioo...", and each of the above stage flip-flop 115
The signals supplied from ~117 to the AND circuit 118 are "...111001111..."...■"-
...000011000..."...■"...1
11110011...'' It can be expressed as ■. Therefore, regarding the two-clock continuous pulse "11" in the output signal from the second stage flip-flop 116 shown by (■) above, the first half is the inverted output of the first stage flip-flop 115, and the second half is the third stage flip-flop. The inverted output (2) of the pull-up 117 removes the signal. In the case of edge detection pulses that are independent by l clocks,
AND circuit 11 from each flip-flop 115 to 117
The signal supplied to 8 is "...11101111..."...■.

"...00001000..."...■""...
・11111011...''...■', so it will not be removed by the circuit section 119.

It should be noted that various configurations are possible for the above-mentioned false edge removal circuit section in addition to the specific example shown in FIG. It is conceivable that only the cases "rolo" and "rolllo" are judged as correct edges.

G-5. Explanation of Operation of Embodiment (FIG. 6) Next, one example of the four specific operations of the digital PLL circuit having the above configuration will be described with reference to FIG.

In the specific example shown in FIG. 6, the output clock cycle data from the counter 32 is expressed as a hexadecimal decimal point as "5.D", that is, the integer part is expressed as "°5".
", and the decimal part is "D(h)" (13 in decimal, that is, 13/16), where () indicates a hexadecimal display value.

First, when the output of the adder 23 is A,4(hl'',
Integer part data “A (c)” is supplied to the comparator 22,
A comparison with the output of counter 21 is made.

Therefore, at the timing t1 when the output from the counter 21 becomes A(h)'', a coincidence output is obtained from the comparator 22, and at the next timing t2 of the master clock CK□, the accumulation latch 24 operates and the above Since the addition output "A, 4 (c)" is supplied to the adder 23, this "°^, 4 (5)" and the output clock cycle data "5°D (c)" are added. In this case A, 4(c)+5. D(c)=10.
1 (5), but since it is an 8-bit digital addition, the lower 8 bits "0.1 (c)" become the addition output. The integer part data of the upper 4 bits of this addition output is “0”.
(C)" is sent to the comparator 22 and compared with the output of the counter 21, so the output from the counter 21 is 0.
01)'', a coincidence output is obtained from the comparator 22 at timing t4, and at the next timing 1., the current addition output is obtained.
0.1 (c)" is the periodic data "5. D (c)" is added (8-bit digital addition), and "'5. E(h
)'' is obtained.Similarly, each time the addition output from the adder 23 and the output from the counter 2.1 fail, a matching output is obtained from the comparator 22, and this is the output clock CKouv. becomes.

By the way, the phase error detection circuit 10 detects the phase error by using the edge detection pulse (
The output from the edge detection circuit 11) is input to the shift register 12 using the master clocks CK and Is as clocks, and the output from the shift register 12 is latched by the latch circuit 13 for each pulse of the output clock CKouv. , depending on which line of the parallel output lines of the latch circuit 13 the edge detection pulse is obtained. That is, when an edge detection pulse is obtained on the center line of the parallel output lines of the launch circuit 13, there is no phase shift, and as the distance from this center line increases, the amount of phase shift increases. When detecting this phase error, the output clock CKoLI
It is necessary to determine the phase error detection range of how many of the parallel output lines of the latch circuit 13 are selected in response to one pulse of T.

Here, in the case where the central output S~ of the shift register 12 of the phase error detection circuit section 10 is obtained as shown in FIG. 6, for example, this output S~ is obtained as shown in FIG.

The amount of deviation between each pulse of the output clock CKout corresponds to the phase error, and the detection range of this phase error can be expressed as a time range. This uses the amount of deviation from which pulse of each pulse of the output clock CKoui (for example, pulse P. II? I, Pootz) as the phase error for the pulse of the output S0 (for example, pulse P, 4i). It is also the range for deciding what to do. In addition, in FIG. 6, each pulse P 01lTls
P0111! The phase error detection range for each of these pulses Pouy+, p is expressed as a range on the time axis.
Outs, etc., the above outputs S existing within the respective detection ranges. The amount of time shift between the pulses is taken as the phase error.

Here, in FIG. 6, the boundary value of the phase error detection range in the one-cycle calculation circuit 19 without the above-mentioned peak shift correction is X, and the decimal part of this value In base numbers, there were 7 and 8 people)
The value is set to Y, and the respective values when the peak shift correction is performed are set to x' and y', respectively. These values X, Y or X', Y' are determined for each pulse of the output clock CKout, and are expressed by the number of counts of the master clock by the counter 21.

First, in the case without the peak shift correction, the boundary value X of the phase error detection range can be found by adding 2 of the output clock period data to the output of the adder 23 indicating the clock position. The output clock cycle data is "5.D (c)" above, and its percentage is 2. If the output of the adder 23 indicating the clock position is, for example, the above “A, 4 (b)”, the boundary value The value Y after rounding the following (hexadecimal number of 7 to the nearest 8) is “'D(
Therefore, the output from the counter 21 becomes "D" for the pulse P.ut+ of the output clock CKour.
The phase error detection range is set up to the timing t3 when "(c)" occurs, and the phase shift between the signal 5) and the pulse PMD of the signal 5)Ill obtained within this range is detected.

Similarly, each time t4, Lq, t++,
... is determined, and the detection range of the phase shift corresponding to each pulse of the output clock CKouv' is t, ~t4
, t, ~tw, t*~t0, . . . . FIG. 6 shows the presence or absence of a pulse of the central output S0 (ie, the presence or absence of an edge detection pulse of the input signal SIN) within these detection ranges.

On the other hand, in the case of the above-mentioned peak shift correction, the boundary value obtained by adding A of the above-mentioned output clock period data is calculated by considering the tendency of deviation according to the edge interval of the waveform shown in Fig. 3 above. What is the interval between X and the previous edge detection pulse? A new boundary value X is obtained by correcting it depending on whether it becomes ut.

I am getting . In other words, the edge interval is ITout or 2T
The boundary correction amount ΔXI for distinguishing between LLIT and LLIT is set to delay the boundary on the time axis. Boundary correction amount Δx2 and 3TOLl to distinguish between edge spacing 2T0° or 3Tout? The boundary correction amount ΔX, which is used to distinguish between 4ToI and T, is set to advance the boundary on the time axis, and the correction amount ΔX is larger than the correction amount ΔX2, which is 0 or more. By performing a peak shift correction such as this, the value Y' obtained by rounding off the decimal places of these values X may deviate from the value Y by about T□, and the detection range may be changed. By changing this detection range, the determination of the presence or absence of an edge may be reversed, and as a result, the presence or absence of an edge can be determined more accurately, and erroneous detection of edge positions can be reduced.

According to the digital PLL circuit as described above, when detecting the period of the output clock CKour, by counting one minute of -N pulses with the master clock CK, . It is possible to obtain period detection accuracy equivalent to increasing the master clock frequency r□ by N times to N'f,s. The period T01. of the output clock CKout detected with high accuracy. has a decimal part, and by performing the calculation in the adder 23 including the part below the decimal point, the accuracy of calculation can be increased to N times that of the conventional one. Therefore, even if the master clock is relatively low, it is resistant to fluctuations in the pit clock frequency due to input data jitter, etc., and has a wide lock range and capture range.
LL circuit can be provided.

In addition, even if a shift occurs in the signal edge due to peak shift, etc., the phase error detection range is adjusted according to the interval from the previous edge, taking into account that the direction and appearance of this shift have statistical properties depending on the edge interval. By making the correction, it is possible to reduce erroneous detection of edge positions and to significantly reduce the adverse effects of edge deviations due to peak shifts and the like.

Note that the present invention is not limited to the above-mentioned embodiments (for example, it goes without saying that the clock frequencies and the like are not limited to the above-mentioned examples). Various changes are possible.

H0 Effects of the Invention According to the digital PLL circuit according to the present invention, even when an edge shift of a waveform equalized signal occurs due to code amount interference, peak shift, etc., the boundary position of the phase error detection range can be determined according to the edge interval. By making the correction, it is possible to effectively prevent erroneous detection of edge positions and to minimize the adverse effects caused by peak shifts and the like.

[Brief explanation of the drawing]

The first flash is a block circuit diagram showing an embodiment of the digital PLL circuit according to the present invention, FIGS. 2 and 3 are waveform diagrams for explaining edge shift of a signal due to peak shift, and FIG. 4 is a one-cycle diagram. FIG. 5 is a block circuit diagram showing a specific example of the period calculation circuit, FIG. 5 is a block circuit diagram showing a specific example of the edge detection circuit, FIG. 6 is a time chart for explaining the operation of the embodiment, and FIG. 7 is a block circuit diagram showing a specific example of the period calculation circuit. 8 is a waveform diagram showing a peak shift during waveform equalization, and FIG. 8 is a time chart for explaining edge shift during sampling. 10... Phase error detection circuit section 11... Edge detection circuit 12... Shift registers 14a, 14b... Area select circuit 19... 1
Cycle period calculation circuit 20...Output clock generation circuit section 21...Counter 22...Comparator 23...Three-input adder 30...Cyclic data detection circuit section 91.92...Adder 93 ···counter

Claims (1)

[Claims:] An output clock generation circuit that obtains pulse period data based on phase error detection data and output clock period data, and generates an output clock pulse every time this pulse period data is counted by a master clock having a constant frequency. a phase error detection circuit that detects a phase error between the output clock from the output clock generation circuit and the edge detection signal of the input signal and sends the obtained phase error detection data to the output clock generation circuit; an output clock period detection circuit that obtains output clock period data from the output clock generation circuit and sends the output clock period data to the output clock generation circuit; It has an area select circuit that selects a phase error detection range of the edge detection signal of the input signal, and has a configuration that changes the selection range of the area select circuit in accordance with the pulse interval of the edge detection signal of the input signal. A digital PLL circuit featuring: