JP3122563B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit mainly used for data demodulation of a magnetic disk drive.

[0002]

2. Description of the Related Art FIG.
This will be described with reference to FIG. FIG. 10 is a diagram showing the configuration of a conventional phase-locked loop circuit shown in, for example, Shoji Takahashi, published by CQ Publishing Co., Ltd., 1989, "All About Floppy Disk Devices", page 302.

In FIG. 10, 1 is a shaping circuit, 2 is a 4-bit down counter (hereinafter, referred to as “counter”), 3
Denotes a flip-flop (hereinafter, referred to as “F / F”).

As signals on the input side, RE is a reference input and CL is a clock. As the output signal, DI
S is a discrimination window signal. Further, SA is a shaping circuit output,
SB is the most significant bit output of the counter 2 (hereinafter referred to as “counter output”).

Next, the operation of the above-described conventional phase locked loop circuit will be described with reference to FIGS. 11, 12, 13, 14 and 15.
This will be described with reference to FIG. FIG. 11 is a timing chart showing the operation of the conventional phase locked loop circuit. FIG.
2 is a timing chart showing the operation of the conventional phase locked loop circuit when the input cycle is slightly different from a natural number multiple of the free running cycle of the counter 2. 13 and FIG.
Means that the input period of the conventional phase locked loop
5 is a timing chart showing an operation when the self-running cycle is significantly different from a natural number multiple of the self-running cycle. FIG. 15 is a timing chart showing the operation of the conventional phase locked loop circuit when there is jitter in the input period.

In FIG. 11, (a) shows a clock CL,
(B) is a shaping circuit output SA, and (c) is a counter output S.
B, (d) is the discrimination window signal DIS, and (e) is the reference input RE.
Are respectively shown.

E is a discrimination unit of the discrimination window signal DIS,
F is the cycle of the counter 2 when there is no reference input RE (hereinafter referred to as “self-running cycle”), and G is the cycle of the reference input RE (hereinafter referred to as “input cycle”).

In FIGS. 12 to 15, (a) shows a reference input RE, (b) shows a counter output SB, and (c) shows a discrimination window signal DIS.

First, the operation of the conventional phase locked loop circuit will be described with reference to FIGS. As shown in FIG. 11B, the content of the counter 2 is initialized to "5" at the shaping circuit output SA, and the content is decreased by "1" from the clock CL after the rising of the shaping circuit output SA.

The counter output SB is the most significant bit of the counter 2. In this way, as shown in FIG. 11C, the counter 2 operates in synchronization with the reference input RE, so that the counter output SB is synchronized with the reference input RE.

As shown in FIG. 11, the input period G (2 μs
When ec) is a natural number multiple of the self-running period F (1 μsec) of the counter 2, the discrimination unit E becomes the same as the self-running period F of the counter 2. The run length of the input cycle G is defined by the number of discrimination units E between the discrimination units E including the reference input RE.

Next, the operation of the conventional phase locked loop circuit when the input period G is slightly different from the self-running period F of the counter 2 by a natural number will be described with reference to FIG. FIG.
This shows a case where the input cycle G (63/16 μsec) is 63 times the cycle of the clock CL. This input cycle G
Is 3 from the number of discrimination units E.

At this time, the average length of the discrimination unit E is about 0.98 when the self-running cycle F of the counter 2 is "1".
The self-running period F of the counter 2 when the frequency division number of the counter 2 is changed from “16” to “15” is “15/16 μsec”.
Considering that “c” is about 0.94, it can be said that such a phase locked loop circuit can increase the resolution of the output frequency when the offset of the data transfer frequency is small. When the resolution of the output frequency is high, the performance of the circuit is improved because it can accurately follow the fine change of the frequency fluctuation of the reference input RE.

Next, the operation of the conventional phase locked loop in the case where the input cycle G is significantly different from the self-running cycle F of the counter 2 by a natural number will be described with reference to FIGS. FIG. 13 shows the minimum value (25/16 μsec) of the input cycle G in which the run length is correctly detected as “1” in the discrimination window signal DIS. FIG. 14 shows the minimum value (57/16 μsec) of the input period G in which the run length is correctly detected as “3” in the discrimination window signal DIS.

The average length of the discrimination unit E in FIG. 13 is about 0.78 when the self-running period F of the counter 2 is "1". The average length of the discrimination unit E in FIG. 14 is about 0.89 when the self-running cycle F of the counter 2 is “1”. As described above, as the input period G becomes longer, the range of frequencies that can be synchronized (hereinafter referred to as “synchronization range”) becomes narrower. Input cycle G
Changes randomly if the data to be transferred is random. However, when the circuit is synchronized with data in which the long-period reference input RE is continuous, the synchronization range is narrowed and performance is deteriorated.

Next, the operation of the conventional phase locked loop circuit when the input period G has jitter will be described with reference to FIG. As shown in FIGS. 15A and 15C, the reference input R
The period of E is “2.13 μsec” and “1.88 μsec”
When "c" is repeated, the cycle of the discrimination window signal DIS also becomes "2.13 .mu.sec" and "1.88 .mu.sec". Therefore, when the phase locked loop is used for jitter reduction, a phase locked loop of a method of detecting the phase error between the reference input RE and the discrimination window signal DIS and outputting the signal after reducing the jitter with a filter is required.

[0017]

In the above-described conventional phase locked loop circuit, there is a problem that when there is an offset in the data transfer frequency, the synchronization range is different due to the difference in the period between the reference input and the data string. .

Another problem is that it is difficult to externally control the response speed of the circuit.

Further, there is a problem that it is difficult to use for reducing the jitter of the reference input.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. When the offset of the data transfer frequency is small, the resolution of the output frequency can be increased. It is an object of the present invention to provide a phase locked loop circuit in which the synchronization range does not change so much even if the period of the data sequence is different.

It is another object of the present invention to provide a phase locked loop circuit in which the response characteristics of the circuit can be easily controlled from outside.

It is another object of the present invention to provide a phase locked loop capable of reducing jitter.

[0023]

A phase synchronization circuit according to a first aspect of the present invention includes the following means. [1] Frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. [2] A phase comparison circuit that detects a phase error between the reference input and the discrimination signal. [3] A filter for removing a high-frequency component of the phase error. [4] A cycle counter that counts the number of cycles of the discrimination signal while the reference input is not continuously input. [5] Frequency division number determining means for determining the frequency division number based on the output of the filter and the output of the cycle counter.

A phase locked loop circuit according to a second aspect of the present invention includes the following means. [1] Frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. [2] A phase comparison circuit that detects a phase error between the reference input and the discrimination signal. [3] A filter for removing a high-frequency component of the phase error. [4] A cycle counter that counts the number of cycles of the discrimination signal while the reference input is not continuously input. [5] Frequency division number determining means for determining the frequency division number based on the output of the filter, the output of the period counter, and an external control signal.

A phase locked loop circuit according to a third aspect of the present invention includes the following means, and the frequency division number determining means includes an adder for adding the self-running cycle of the frequency dividing means to the output of the filter. [1] Frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. [2] A phase comparison circuit that detects a phase error between the reference input and the discrimination signal. [3] A filter for removing a high-frequency component of the phase error. [4] A cycle counter that counts the number of cycles of the discrimination signal while the reference input is not continuously input. [5] Frequency division number determining means for determining the frequency division number based on the output of the filter and the output of the cycle counter.

A phase locked loop circuit according to a fourth aspect of the present invention includes the following means. [1] Frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. [2] A phase comparison circuit that detects a phase error between the reference input and the discrimination signal and identifies the phase error into four types. [3] A filter for removing a high-frequency component of the phase error. [4] A cycle counter that counts the number of cycles of the discrimination signal while the reference input is not continuously input. [5] Frequency division number determining means for determining the frequency division number based on the output of the filter and the output of the cycle counter.

According to a fifth aspect of the present invention, there is provided a phase locked loop circuit comprising the following means, wherein the filter includes an up / down counter for accumulating a phase error and a gate circuit for attenuating the value of the up / down counter at an appropriate ratio. Including. [1] Frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. [2] a phase comparison circuit that detects a phase error between the reference input and the discrimination signal, [3] a filter that removes a high-frequency component of the phase error. [4] A cycle counter that counts the number of cycles of the discrimination signal while the reference input is not continuously input. [5] Frequency division number determining means for determining the frequency division number based on the output of the filter and the output of the cycle counter.

[0028]

In the phase synchronization circuit according to the first aspect of the present invention, the frequency dividing means generates a discrimination signal for discriminating the reference input based on the predetermined frequency division number by dividing the clock of the predetermined frequency. Is done. Further, a phase error between the reference input and the discrimination signal is detected by a phase comparison circuit, and a high frequency component of the phase error is removed by a filter. Further, the period counter counts the number of periods of the discrimination signal while the reference input is not continuously input. Then, the frequency dividing number is determined by the frequency dividing number determining means based on the output of the filter and the output of the period counter.

In the phase locked loop circuit according to a second aspect of the present invention, the frequency dividing means generates a discrimination signal for discriminating the reference input based on the predetermined frequency division number by dividing the clock of the predetermined frequency. Is done. Further, a phase error between the reference input and the discrimination signal is detected by a phase comparison circuit, and a high frequency component of the phase error is removed by a filter. Further, the period counter counts the number of periods of the discrimination signal while the reference input is not continuously input. Then, the frequency division number is determined by the frequency division number determining means based on the output of the filter, the output of the period counter, and an external control signal.

In the phase locked loop circuit according to a third aspect of the present invention, the frequency dividing means generates the discrimination signal for discriminating the reference input based on the predetermined frequency division number by dividing the clock of the predetermined frequency. Is done. Further, a phase error between the reference input and the discrimination signal is detected by a phase comparison circuit, and a high frequency component of the phase error is removed by a filter. Further, the period counter counts the number of periods of the discrimination signal while the reference input is not continuously input. The frequency dividing number is determined by the frequency dividing number determining means including an adder for adding the self-running cycle of the frequency dividing means to the output of the filter based on the output of the filter and the output of the period counter. .

In the phase synchronization circuit according to a fourth aspect of the present invention, the frequency division means generates a discrimination signal for discriminating the reference input based on the predetermined frequency division number by dividing the clock of the predetermined frequency. Is done. Further, a phase error between the reference input and the discrimination signal is detected by a phase comparison circuit, the phase error is identified into four types, and a high-frequency component of the phase error is removed by a filter. further,
A period counter counts the number of periods of the discrimination signal while the reference input is not continuously input. Then, the frequency dividing number is determined by the frequency dividing number determining means based on the output of the filter and the output of the period counter.

In the phase locked loop circuit according to a fifth aspect of the present invention, the frequency division means generates a discrimination signal for discriminating the reference input based on the predetermined frequency division number by dividing a clock having a predetermined frequency. Is done. Further, a phase error of the reference input and the discrimination signal is detected by a phase comparison circuit, and a filter including an up / down counter for accumulating the phase error and a gate circuit for attenuating the value of the up / down counter at an appropriate ratio is used. , The high frequency components of the phase error are removed. Further, the period counter counts the number of periods of the discrimination signal while the reference input is not continuously input. Then, the frequency dividing number is determined by the frequency dividing number determining means based on the output of the filter and the output of the period counter.

[0033]

[Embodiment 1] Hereinafter, the configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention. The F / F 3, reference input RE, clock CL, and discrimination window signal DIS are the same as those of the above-described conventional circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 1, 4 is a phase comparison circuit, 5 is a filter connected to the phase comparison circuit 4, 6 is a gate circuit connected to the filter 5, and 7 is a frequency division number setting circuit connected to the gate circuit 6. , 8 are frequency dividers connected to the frequency division number setting circuit 7, 9 is a cycle counter connected to the frequency divider 8, and 10 is a timing generation circuit.

Further, SC is a phase error, SD is a filter output, SE is a gate circuit output, SF is a frequency division number, SG is a frequency divider output, SH is a cycle counter output, and SJ is a reference input with reduced jitter. Hereinafter, referred to as “reference output”), SK,
SL, SM, and SN indicate clocks that are outputs of the timing generation circuit 10, respectively.

The frequency dividing means according to the first embodiment of the present invention corresponds to the frequency divider 8 in the first embodiment, and the phase comparing circuit according to the first embodiment of the present invention employs a phase comparator in the first embodiment. The filter according to claim 1 of the present invention corresponds to the filter 5 in the first embodiment, and the cycle counter according to the first embodiment of the present invention corresponds to the cycle counter 9 in the first embodiment. Correspondingly, the frequency division number determining means according to claim 1 of the present invention comprises a gate circuit 6 and a frequency division number setting circuit 7 in the first embodiment.

Next, the operation of the first embodiment will be described with reference to FIGS. FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.
FIGS. 3A and 3B are diagrams showing the input / output relationship of the gate circuit 6 according to the first embodiment of the present invention.

In FIG. 2, (a) shows a reference input RE,
(B) is a frequency divider output SG, (c) is a discrimination window signal DIS,
(D) is the reference output SJ, (e) is the phase error SC, (f)
Is the filter output SD, (g) is the cycle counter output SH,
(H) shows the gate circuit output SE, and (j) shows the frequency division number SF. E is a discrimination unit, and H is a self-running cycle of the frequency divider 8.

The frequency divider 8 divides the frequency of the clock CL by the input frequency division number SF. When the cycle of the frequency divider output SG is the free-running cycle H of the frequency divider 8, the first half of the cycle outputs "0" and the second half outputs "1". As shown in FIG. 2B, the free-running cycle H of the frequency divider 8 is “1”.
6 ”, and at this time, the count value of the frequency divider 8 is“ 0 ”.
The frequency divider output SG is "0" when the value is equal to or less than "7", and is "1" otherwise.

The cycle counter 9 is reset at the end of the discrimination unit E having the reference input RE, and is incremented by one at the end of the discrimination unit E whenever the discrimination unit E without the reference input RE continues. The phase comparison circuit 4 outputs a phase error SC between the reference input RE and the rising edge of the frequency divider output SG.

The filter 5 reduces the jitter of the phase error SC and outputs the result. The gate circuit 6 receives the filter output SD and the cycle counter output SH as inputs and outputs each discrimination window signal DI
The period of S is determined and output. Timing generation circuit 10
Generates operation clocks SK to SN for each component.
The cycle counter 9 outputs a reference output SJ synchronized with the discrimination unit E to which the reference input RE is input.

Next, the operation of the gate circuit 6 will be described in detail. When the reference input RE is input, a phase error SC is detected. The filter 5 receives the phase error SC as input and outputs a filter output SD after reducing jitter. Similarly, as shown in FIG. 2 (g), the period counter 9 is "0".
Is cleared.

When the cycle counter output SH is "0", the gate circuit 6 outputs the filter output SD as it is. Here, the filter output SD is set to +3 as shown in FIG. As shown in FIG. 2 (j), the frequency division number setting circuit 7 outputs the self-running cycle H of the frequency divider 8 to the gate circuit output SE.
The number “19” obtained by adding “16” is output to the frequency divider 8. The filter output SD is, as shown in FIG.
After the frequency dividing number setting circuit 7 takes in the gate circuit output SE, it is attenuated to become the number "2". In the next discrimination unit E, FIG.
As shown in (g), the cycle counter output SH becomes “1”.

As shown in FIG. 2H, the gate circuit 6 outputs "0" at the input of this combination. The frequency division number setting circuit 7 outputs “16”, which is the self-running cycle H of the frequency divider 8, to the frequency divider 8. Period counter output SH in the next discrimination unit E
Becomes “2”. As shown in FIG. 2 (h), the gate circuit 6 outputs "1" by the input of this combination. The frequency division number setting circuit 7 similarly outputs the number “17” to the frequency divider 8.

In the above operation example, when the frequency division number SF is set at the above timing when the filter output SD is +3, the synchronization range is improved when the consecutive length of the input period G is 2 or more. By preventing such compensation when the filter output SD is small, the input period when the input period G greatly fluctuates without lowering the resolution of the output frequency when the fluctuation of the input period G is small. The change in the synchronization range due to the difference in G can be reduced. FIG. 3A shows the input / output relationship of the gate circuit 6 in the above operation example, and FIG. 3B shows another more gradual input / output relationship of the gate circuit 6.

The first embodiment of the present invention, as described above,
In a phase synchronization circuit including a frequency divider 8 that generates a discrimination signal SG for discriminating the reference input RE by dividing a high-frequency clock CL, a phase error SC between the reference input RE and the discrimination signal SG is calculated. A phase comparison circuit 4 for detecting, a filter 5 for removing a high frequency component of the phase error SC, and the discrimination signal S to which the reference input RE is not continuously inputted.
A period counter 9 for counting the number of periods of G, and a division number setting for determining a division number SF of a frequency divider 8 for generating the discrimination signal SG using the filter output SD and the period counter output SH. And a circuit 7.

In the first embodiment, in particular, when the discrimination window signal DIS having no reference input RE is continuous, the cycle counter 9 counts the discrimination window signal DIS, the filter output SD of the phase error SC, and the output SH of the cycle counter 9. And a gate circuit 6 which outputs the frequency division number of the output frequency. That is, the cycle counter 9 recognizes a period in which there is no reference input RE, and determines the number of divisions of the output frequency by the gate circuit 6.
Determines the frequency division number by compensating the filter output SD of the phase error SC according to the length of the period.

As described above, according to the first embodiment, the filter output of the phase error and the number of continuous discrimination units E without the reference input RE are input to the circuit for determining the frequency division number of the output frequency. When the data transfer cycle is close to the free-running cycle H of the frequency divider 8, the resolution of the output frequency can be increased, and the data transfer cycle can be increased. When the reference input RE is longer than the self-running cycle H, the synchronization range does not become too narrow even if the cycle of the reference input RE is long .

Embodiment 2 FIG. In the first embodiment, the inputs of the gate circuit 6 for determining the frequency division number are only the filter output SD and the cycle counter output SH.
In this example, an external control input SP is added.

The configuration of the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing the configuration of the second embodiment of the present invention. The F / F 3 to the filter 5, the frequency division number setting circuit 7 to the timing generation circuit 10 are the same as those of the first embodiment.
It is similar to that of

In FIG. 4, 6A is a gate circuit, and SP is an external control input.

The frequency dividing means according to the second embodiment of the present invention corresponds to the frequency divider 8 in the second embodiment, and the phase comparing circuit according to the second embodiment of the present invention employs a phase comparator in the second embodiment. The filter according to claim 2 of the present invention corresponds to the filter 5 in the second embodiment, and the cycle counter according to the second embodiment of the present invention corresponds to the cycle counter 9 in the second embodiment. Correspondingly, the frequency division number determining means according to claim 2 of the present invention comprises a gate circuit 6A and a frequency division number setting circuit 7 in the second embodiment.

As described above, the control input SP is connected to the gate circuit 6
By adding it to the input side of A, the design of the control method becomes easy. For example, FIG. 3A and FIG.
Can be selected.

That is, according to the second embodiment, an external control signal SP is supplied to the circuit for determining the frequency division number of the output frequency.
Is input so that the method of determining the frequency division number can be controlled, so that the characteristics of the phase locked loop can be easily controlled from the outside.

Embodiment 3 FIG. The frequency division number setting circuit 7A according to the third embodiment of the present invention includes an n-bit flip-flop (F / F) and an adder.

The configuration of the third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram showing a configuration of a frequency division number setting circuit 7A according to a third embodiment of the present invention. The configuration other than the frequency division number setting circuit 7A is the same as that of the first embodiment.

In FIG. 5, reference numeral 11 denotes an n-bit F / F, 1
2 is an adder. SQ is an n-bit F / F11 reset input, and H is a free-running cycle of the frequency divider 8.

The reset input SQ initializes the n-bit F / F11. Further, the self-running cycle H is a fixed value “m”.

Since the filter output SD is obtained by reducing the jitter of the phase error SC, it is usually necessary to add the free-running period H of the frequency divider 8 to set the period of the frequency divider 8. The frequency division number setting circuit 7A fetches the gate circuit output SE with the n-bit F / F11 and adds the self-running cycle H (fixed value m) of the frequency divider 8 to output. In order to adopt this configuration, it is not necessary to hold the gate circuit output SE, which is an input, during the period of the frequency divider 8, and the n-bit F / F1
By simply resetting 1 by the reset input SQ, the frequency divider 8 can be easily operated in the free-running cycle H.

According to the third embodiment, the frequency division number setting circuit 7
Since A is composed of an n-bit F / F 11 and an adder 12,
It is not necessary to hold the filter output SD for one cycle of the frequency divider 8, and there is an effect that the operation design of the filter 5 becomes easy.

Embodiment 4 FIG. The phase comparison circuit 4A according to the fourth embodiment of the present invention identifies four types of phase errors SC.

The configuration of the fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing a configuration of a phase comparison circuit 4A according to a fourth embodiment of the present invention. The configuration other than the phase comparison circuit 4A is the same as that of the first embodiment.

In FIG. 6, 13 is a counter, 14 is a gate circuit, and 15 and 16 are F / Fs. SR is a phase comparison signal output from the gate circuit 14.

Next, the operation of the phase comparison circuit 4A according to the fourth embodiment will be described with reference to FIG. FIG.
9 is a timing chart showing the operation of the phase comparison circuit 4A according to Embodiment 4 of the present invention. 7A shows the frequency divider output SG, and FIG. 7B shows the phase comparison signal SR.

The counter 13 is initialized at the fall of the frequency divider output SG. The gate circuit 14 includes a counter 13
And outputs a phase comparison signal SR as shown in FIG. 7B. F / F15 is a reference input RE
At the rise of the frequency divider SG. Since the value of the frequency divider output SG changes approximately at the center of the discrimination unit E, the phase relationship with the rise of the frequency divider output SG can be determined from the value taken in by the F / F 15.

On the other hand, the F / F 16 takes in the phase comparison signal SR at the rise of the reference input RE. Since the phase comparison signal SR has a waveform as shown in FIG. 7B, it can be seen that the amount of deviation from the rising point of the frequency divider output SG of the reference input RE is large or small. F / F15 output (“H” level and “L” level)
Level) and the output of the F / F 16 (“H” level and “L” level).
Level), four types of phase errors SC can be identified.

According to the fourth embodiment, the phase comparison circuit 4A
With two types of phase comparison signals (SG, SR) and two F /
Since F15 and F16 are used, the phase error SC can be classified into four types and output. If the phase error SC is classified into two types, the response can be made faster when the phase error is large.

Embodiment 5 FIG. The filter 5A according to the fifth embodiment of the present invention includes an up / down counter for accumulating a phase error,
It is configured in combination with a gate circuit that attenuates the value (output) at an appropriate ratio.

The configuration of the fifth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing a configuration of a filter 5A according to a fifth embodiment of the present invention.
Except for this, the configuration is the same as that of the first embodiment.

In FIG. 8, 17 is a signal generation circuit including a delay element, 18 is an up / down counter that can be initialized,
Reference numeral 19 denotes a gate circuit which receives an output of the up / down counter 18 and outputs a set value of the up / down counter 18.

Further, SS is a clock for increasing / decreasing the up / down counter 18 at a value corresponding to the phase error SC.
T indicates the output of the gate circuit 19 as an up / down counter 18
This is a clock for setting

Next, the filter 5A of the fifth embodiment described above is used.
Will be described with reference to FIG. FIG.
13 is a timing chart showing the operation of a filter 5A according to Embodiment 5 of the present invention.

In FIG. 9, (a) shows a reference input RE,
(B) is the frequency divider output SG, (c) is the phase error SC,
(D) is the clock SS, (e) is the filter output SD,
(F) shows the frequency division number SF, and (g) shows the clock ST.

First, as shown in FIGS. 9D and 9G, the signal generation circuit 17 outputs a clock SS based on a signal SL from the timing generation circuit 10, and outputs this clock SS to an internal delay element. To output the clock ST. As shown in FIGS. 9A to 9D, the clock SS rises when the reference input RE is input and the phase error SC is reliably detected, that is, at the end of the discrimination unit E to which the reference input RE is input. . The up / down counter 18 increases / decreases in accordance with the phase error SC in synchronization with the clock SS.

Next, the frequency division number setting circuit 7 takes in the result as a filter output SD via the gate circuit 6.
The up / down counter 18 is an up / down counter 1
The attenuated filter output value calculated from the output of No. 8 is taken in from the gate circuit 19 in synchronization with the clock ST. A stable filter 5A can be configured by adding an attenuation element as described above without simply integrating the value of the phase error SC.

That is, according to the fifth embodiment, an up / down counter 18 capable of initializing the filter 5A to accumulate a phase error amount, and a gate circuit for outputting an attenuated value with the value of the up / down counter 18 as an input. 19, there is an effect that the jitter of the phase error can be reduced with a simple configuration.

[0077]

As described above, the phase locked loop circuit according to the first aspect of the present invention divides a discrimination signal for discriminating a reference input based on a predetermined frequency division number by a clock of a predetermined frequency. Frequency dividing means for generating, a phase comparison circuit for detecting a phase error between the reference input and the discrimination signal, a filter for removing a high-frequency component of the phase error, and the discrimination while the reference input is not continuously input A period counter for counting the number of signal periods; and a frequency division number determining means for determining the frequency division number based on the output of the filter and the output of the frequency counter. when close to the free-running period can increase the resolution of the output frequency, locking range even when the cycle of the reference input is long need not become so narrowed when the data transfer cycle is separated from the free-running period of the frequency dividing means The effect say.

As described above, the phase locked loop circuit according to the second aspect of the present invention generates a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. Frequency dividing means, a phase comparison circuit for detecting a phase error between the reference input and the discrimination signal, a filter for removing a high frequency component of the phase error, and a filter for the discrimination signal while the reference input is not continuously input. A phase synchronization circuit comprising: a period counter that counts the number of periods; and a frequency division number determining unit that determines the frequency division number based on the output of the filter, the output of the period counter, and an external control signal. This has the effect that the characteristics can be easily controlled from the outside.

As described above, the phase locked loop circuit according to claim 3 of the present invention generates a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. Frequency dividing means, a phase comparison circuit for detecting a phase error between the reference input and the discrimination signal, a filter for removing a high frequency component of the phase error, and a filter for the discrimination signal while the reference input is not continuously input. A period counter that counts the number of periods; and a frequency division number determining unit that determines the frequency division number based on the output of the filter and the output of the period counter. Includes an adder for adding the self-running cycle of the frequency dividing means, so that it is not necessary to hold the filter output for one cycle of the frequency dividing means, thereby facilitating the operation design of the filter. Unlikely to.

As described above, the phase locked loop circuit according to claim 4 of the present invention generates a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. Frequency dividing means, a phase comparison circuit that detects a phase error between the reference input and the discrimination signal and identifies the phase error into four types, a filter that removes a high frequency component of the phase error, and the reference input is continuous. A period counter that counts the number of periods of the discrimination signal while the signal is not input, and a frequency division number determining unit that determines the frequency division number based on the output of the filter and the output of the period counter. With a simple configuration, the phase error can be distinguished into four types, and when the phase error is large, the response can be speeded up.

As described above, the phase locked loop circuit according to claim 5 of the present invention generates a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency. Frequency dividing means, a phase comparison circuit for detecting a phase error between the reference input and the discrimination signal, a filter for removing a high frequency component of the phase error, and a filter for the discrimination signal while the reference input is not continuously input. A period counter that counts the number of periods; and a frequency division number determination unit that determines the frequency division number based on the output of the filter and the output of the period counter, wherein the filter is configured to accumulate the phase error. Since a counter and a gate circuit for attenuating the value of the up / down counter at an appropriate ratio are included, it is possible to reduce jitter with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a diagram showing an input / output relationship of the gate circuit according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a configuration of a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a frequency division number setting circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a phase comparison circuit according to a fourth embodiment of the present invention.

FIG. 7 is a timing chart illustrating an operation of the phase comparison circuit according to the fourth embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a filter according to a fifth embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the filter according to the fifth embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a conventional phase locked loop circuit.

FIG. 11 is a timing chart showing the operation of a conventional phase locked loop circuit.

FIG. 12 is a timing chart showing the operation of a conventional phase locked loop circuit.

FIG. 13 is a timing chart showing an operation of a conventional phase locked loop circuit.

FIG. 14 is a timing chart showing an operation of a conventional phase locked loop circuit.

FIG. 15 is a timing chart showing an operation of a conventional phase locked loop circuit.

[Explanation of symbols]

 4, 4A phase comparison circuit 5, 5A filter 6 gate circuit 7, 7A frequency division number setting circuit 8 frequency divider 9 period counter 10 timing generation circuit RE reference input CL clock DIS discrimination window signal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-76417 (JP, A) JP-A-62-242633 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03L 7/06-7/14

Claims (5)

(57) [Claims] 1. A frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency, and detecting a phase error between the reference input and the discrimination signal. A phase comparison circuit, a filter for removing a high-frequency component of the phase error, a cycle counter for counting the number of cycles of the discrimination signal while the reference input is not continuously input, and an output of the filter and the cycle counter. A phase locked loop circuit comprising a frequency division number determining means for determining the frequency division number based on an output. 2. Dividing means for dividing a clock of a predetermined frequency to generate a discrimination signal for discriminating a reference input based on a predetermined frequency division number, and detecting a phase error between the reference input and the discrimination signal. A phase comparison circuit, a filter for removing a high-frequency component of the phase error, a cycle counter for counting the number of cycles of the discrimination signal while the reference input is not continuously input, and an output of the filter; A phase locked loop circuit comprising: a frequency division number determining unit that determines the frequency division number based on an output and an external control signal. 3. A frequency dividing means for generating a discrimination signal for discriminating a reference input based on a predetermined frequency division number by dividing a clock of a predetermined frequency, and detecting a phase error between the reference input and the discrimination signal. A phase comparison circuit, a filter for removing a high-frequency component of the phase error, a cycle counter for counting the number of cycles of the discrimination signal while the reference input is not continuously input, and an output of the filter and the cycle counter. It is provided with frequency dividing number determining means for determining the frequency dividing number based on an output, wherein the frequency dividing number determining means includes an adder for adding a self-running cycle of the frequency dividing means to an output of the filter. Phase synchronization circuit. 4. A dividing means for dividing a clock of a predetermined frequency to generate a discrimination signal for discriminating a reference input based on a predetermined division number, and detecting a phase error between the reference input and the discrimination signal. A phase comparison circuit that identifies the phase error into four types, a filter that removes a high-frequency component of the phase error, a cycle counter that counts the number of cycles of the discrimination signal while the reference input is not continuously input, And a frequency dividing number determining means for determining the frequency dividing number based on the output of the filter and the output of the period counter. 5. A dividing means for dividing a clock of a predetermined frequency to generate a discrimination signal for discriminating a reference input based on a predetermined frequency division number, and detecting a phase error between the reference input and the discrimination signal. A phase comparison circuit, a filter for removing a high-frequency component of the phase error, a cycle counter for counting the number of cycles of the discrimination signal while the reference input is not continuously input, and an output of the filter and the cycle counter. A frequency division number determining means for determining the frequency division number based on an output, wherein the filter includes an up / down counter for accumulating the phase error and a gate circuit for attenuating the value of the up / down counter at an appropriate ratio. A phase locked loop circuit.