JPS63302617A - Delay circuit - Google Patents

Abstract

PURPOSE:To form a desired delay time, by constituting a delay circuit of a joint type FET operated at fast response speed and a joint type diode, and changing the threshold voltage of a logic device by a change-over switch. CONSTITUTION:When an input terminal 100 is connected to the input terminal of an input delay logic device MDL11 and the joint type field effect JFE transistors Q6 of MDAs 11 and 12 to a power source E1 by the change-over switch 15, the delay circuit forms a circuit of MDLAs 11-13 and an MDL14 with four stages in series. Also, when the input terminal 100 is connected to the connection point of resistors R1 and R2 and the JFETs Q6 of the MDLAs 11 and 12 to a power source E2 by the change-over switch 15, the MDLAs 11 and 12 are disconnected from the delay circuit, and the MDLAs 13 and 14 form the circuit of two stages in series. At this time, since the rise time and the fall time of the MDLAs 11-14 are set differently, it is possible to set the delay time by changing the threshold voltage of the logic device by selecting the number of stages of the logic devices by the switch 15, and changing a transmission delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit, and particularly to a delay circuit using a junction field effect transistor for use in a high-speed logic circuit.

[Conventional technology]

Conventionally, this type of delay circuit has a plurality of multiple input delay logic elements (hereinafter referred to as 5DL), for example 4, as shown in the circuit diagram in FIG.
They are connected in series. Each of these SDLs consists of four junction field effect transistors (hereinafter referred to as JFE).
Transistor) Ql.

It is composed of Q 2 , Q 3 and Q4 and two junction diodes (hereinafter referred to as J diodes) Dl and D2, and the drain of the JFE transistor Q1 is connected to the terminal 301 of the drain power supply (hereinafter referred to as Voo), and this JFE transistor Q1 The gate and source of JFE transistor Q2
The source of JFE transistor Q2 is connected to the drain of the line load resistor terminating power supply (
Vtt), the drain of the JFE transistor Q3 is connected to the terminal 301, the gate is connected to the drain of the JFE transistor Q2, the source is connected to the J diode D,
The cathode side of the J diode D1 is connected to the anode side of the J diode D2, the cathode side of the J diode D2 is connected to the drain of the JFE transistor Q4, and the gate and source of the JFE transistor Q4 are connected to the anode side of the JFE transistor Q4. It is connected to a terminal 303 of a source power source (hereinafter referred to as Vss), with the gate of the JFE transistor Q2 as an input terminal and the cathode side of the J diode D1 as an output terminal.

Figure 6 is the timing chart of Figure 5, and the 5th stage of the first stage.
The input signal given to the input terminal 100 of DL51 is 5D
At the output end of L51, the phase is inverted, but delayed by a time T. The same operation repeats the phase inversion and the delay of time TI in each stage, so the output terminal 200 of the 5DL54 in the fourth stage has the same phase as the input signal and the time T2 signal 4T1.
An output signal with a propagation delay time of .

[Problem that the invention seeks to solve]

However, the conventional delay circuit described above obtains delay time by connecting n stages of SDLs (n is an integer) in series, so the delay time cannot be changed externally, and the SDL transmission delay The drawback is that the delay time can only be set as an integer multiple of the time.

By the way, when designing a digital IC, there is no reference clock and the relative speed of the signal is slow! In this circuit, a delay circuit is installed on one of the signal lines to adjust the relative speed of the signal. In this case, the delay time is set by taking into account the delay time due to element delay, wiring length, stray capacitance, etc. However, the higher the frequency, the narrower the allowable range of variation in the delay time of the delay circuit, and the problem is that if the optimal delay time is not set, the relationship between relative speeds will be reversed. have.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and problems and to provide a delay circuit that can set any necessary delay time.

[Means for solving problems]

The delay circuit of the present invention is a delay circuit in which a plurality of delay logic elements having different rise and fall characteristics, each of which is composed of a junction field effect transistor and a junction diode, are connected in multiple stages and integrated. It has multiple input terminals, and connects the input signal of the delay circuit to the input of a delay logic element other than the first stage delay logic element, and
A changeover switch that applies a high-level voltage to one input terminal of at least the preceding stage delay logic element of the delay logic element to which the input is connected to put it in a signal cutoff state, and at least one input terminal of the final stage delay logic element. and a variable power supply for changing the threshold voltage that is connected to and changes the delay time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 3 is a multi-input delay logic element (hereinafter referred to as MDL) which is the basic circuit of FIG.
> is a circuit diagram. Before explaining Fig. 1, we will explain Fig. 3. This MDL is a junction field effect transistor (hereinafter referred to as JFE transistor) Ql, Q2, and Q for inverting a signal and changing the threshold voltage of a logic element.
5 and a JFE transistor Q for matching the output signal level to the input level of the next stage logic element.
3 and Q4 and junction diode (hereinafter referred to as J diode)
and a rear section consisting of DI and D2. Note that in FIG. 3, the same reference numerals as in FIG. 5 represent the same things. The front stage is JFE transistor Qt and JF
E) The rise time of the output signal is set to be shorter than the fall time depending on the ratio of the transfer conductance parameter β with the transistors Q2 and Q5. Also,
In a circuit configuration of 0 or more in which the gate input of transistor Q5 (JFE), which is one input of MDL, is connected to a variable power supply Ev for changing the threshold voltage, the voltage of the power supply Ev for changing the threshold voltage is set to be slightly lower than the low level of the input signal. The threshold voltage of this MDL can be lowered by increasing the voltage.

FIG. 4 is a timing chart of FIG. 3, and the operation of FIG. 3 will be explained below with reference to FIG. Figure 4 (
a> is a timing chart when the variable power supply Ev for changing the threshold voltage is set below the low level of the input signal, and shows the output signal of the output terminal 200 when the reference threshold voltage is between the high level and the low level of the input signal. There is. FIG. 4(b) shows the output signal of the output terminal 200 when the threshold voltage is changed by raising the variable power source Ev for changing the threshold voltage above the low level of the input signal. The rising delay time T8 in FIG. 4(b) is equal to the rising propagation delay time T4 in FIG. 4(a) plus the falling time T6 due to the difference in threshold voltage, and the falling delay time T8 is equal to is equal to the transmission delay time T3 minus the rise time T5 due to the difference in threshold voltage, so as shown in this figure, the delay time can be increased by lengthening the fall time and shortening the rise time of the output signal. Work in the direction. Furthermore, in order to change the delay time in the direction of decreasing it, the transfer conductance parameter β is set so that the fall time is shortened and the rise time is lengthened.

In addition, in the ultra-high frequency band, by utilizing the transmission delay time of the element in addition to the above, the range in which the delay time can be varied is widened. Therefore, by using an MDL based on the above principle, the number of MDLs through which a signal passes can be changed externally.

Next, proceeding with the explanation of Figure 1, this circuit is an MD with different rise times and fall times, similar to the MDL in Figure 3.
This shows a case in which four stages of L, MDLA II, 12.13, and MDL14 are connected in series. In FIG. 1, the same reference numerals as in FIG. 3 indicate the same components. MDL14 has the same circuit configuration as the MDL in Figure 3, but each of MDLA11 to MDLA13 has a separate JFE transistor Q in parallel in addition to the JFE transistor Q5 in Figure 3.
6 is provided, and the JFE transistor Q.

Similarly, the threshold voltage for the input signal can be changed by changing the potential applied to the gate of the JFE transistor Q6. In addition, the power supply Ev for changing the threshold voltage is
E) connected to the gate of transistor Q, MDLAII
A power supply E1 having the same voltage as the low level of the input signal and a power supply E2 having the same voltage as the high level of the input signal are connected to the gates of the JFE transistors Q6 and 12 via the changeover switch 15. ing.

Further, the gate of the JFE transistor Q6 of the MDLA 13 is connected to a connection point between resistors R1 and R2 provided in series between the terminals 301 and 303, and this connection point is connected to the gate of the JFE transistor Q6 through another contact of the changeover switch 15. When not connected to the input terminal 100, the voltage is the same as the low level of the input signal. Furthermore, the input terminal 100 may be connected to the connection point between the resistors R1 and R2 via the changeover switch 15 as described above, or may be connected to the connection point between the resistors R1 and R2, or the
It is connected to the gate of Q2.

In the above configuration, the input terminal 100 is connected to the input of MDLAII by the changeover switch 15.
When the JFE transistor Q6 of MD LA11-13. There are four stages of MDL14 in series. Further, when the input terminal 100 is connected to the connection point between the resistors R1 and R2, and the JFE transistor Q6 of MDLA II and 12 is connected to the power supply E2 by the changeover switch 15, MDLA II and 12 are disconnected from the delay circuit, and the delay circuit is connected to the MDLA 13 and MDR14-2
The stages are in series.

FIG. 2 is a timing chart of FIG. 1, and in the first half of the timing chart, the input terminal 100 is
In the latter half of the timing chart, the input terminal 100 is connected to MDLAII by the changeover switch 15.
This shows the case when connected to LA13, and selector switch 1
5 indicates that the delay time can be changed approximately twice.

〔Effect of the invention〕

As explained above, the present invention uses junction field effect transistors and junction diodes with fast response speed in ultra-high frequency bands, and selects the number of logic element stages using a changeover switch to adjust the propagation delay time of the delay circuit. By changing the threshold voltage of the logic element by applying a voltage to the input terminal of the logic element, it is possible to vary the delay time over a wide range and minutely, making it possible to easily match the timing between signals. effective.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a timing chart of the operation of Figure 1, Figure 3 is a circuit diagram of the basic circuit of the present invention, and Figure 4 is a diagram of the operation of Figure 3. FIG. 5 is a circuit diagram of a conventional delay circuit, and FIG. 6 is a timing chart of the operation of FIG. 5. 11 to 13...Multi-input delay logic element (MDLA>, 1
4... Multiple input delay logic element (MDL), 15... Selector switch (SW), 51-54... Multiple input delay logic element (SDL>, 100... Input terminal, 200...
・Output terminal, Ql to Q6...junction field effect transistor (JFE transistor), Dl, Dl...junction type 3rd ffi 4 圀

Claims (1)

[Claims] In a delay circuit in which a plurality of delay logic elements having different rise and fall characteristics each formed by a junction field effect transistor and a junction diode are connected in multiple stages and integrated, the delay logic element has multiple input terminals, The input signal of the delay circuit is reconnected to the input of a delay logic element other than the first stage delay logic element, and the input signal is connected to the input terminal of at least one of the delay logic elements in the preceding stage of the delay logic element to which the input is connected. The present invention is characterized by having a changeover switch that applies a level voltage to turn the signal off, and a variable power supply for changing the threshold voltage that is connected to at least one input terminal of the final stage delay logic element to change the delay time. delay circuit.