JPS63301349A - Data transfer system - Google Patents

Abstract

PURPOSE:To realize the transfer of data to be recorded at a desired time point by delaying the transmission of a request signal received from a prescribed device in case it is decided that the time needed from the output of a request signal via a prescribed device through the input of an answer signal is less than a desired period. CONSTITUTION:The signal SYNCIN produced by a string controller DSC (not shown in figure) is supplied to an AND circuit 3 at one side and to an AND circuit 1 at the other side respectively. The circuit 3 opens and closes a gate in response to the output of an FF 9 and accordingly transfers the first signal SYNCIN received from the controller DSC to a disk device as a signal SYNCIN '. Then the circuit 3 closes the gate to delay the transmission of the signal SYNCIN' in case the time needed from transmission of the signal SYNCIN' through the input of the signal SYNCIN is shorter than a prescribed period. While the signal SYNCIN is delivered as the signal SYNCIN' when said time is longer than the prescribed period.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer method, and in particular, a plurality of devices of a data processing system are connected by cables having different lengths depending on the system installation situation. The present invention relates to a data transfer method suitable for preventing data transfer control from being affected by differences in signal propagation delay times depending on the data transfer.

[Conventional technology]

In a magnetic disk device or the like, when data is transferred from a transmitting device, it is necessary to determine the timing of transmission, etc., taking into account the influence of signal propagation delays that occur depending on the length of the interface cable. Data transferred to a magnetic disk device must be recorded at a location on the magnetic disk specified by a scheduled address. As the above-mentioned scheduled address, it is usual to specify a device address, a head number, a track number, and a position in the track viewed from a reference point called an index. The data to be recorded must be presented to the head when the addressed position is below the head; to ensure that the first data to be recorded is supplied in time, it is necessary to It is necessary to output a request signal requesting data to the transmitting device a predetermined time before the time when the data is recorded. The above-mentioned predetermined time includes the propagation time of the request signal, the propagation time of the data itself, and the delay time in the transmitter, and even if any of these factors changes, the predetermined data cannot be correctly transmitted to the target address location. Unable to write.

In recent years, data transfer speeds have increased, and the time required to serialize and encode data from a transmitter and provide it to the head in magnetic disk drives has become extremely short, so signal propagation delay has become increasingly important. Differences in signal propagation delay due to differences in cable length are becoming a major factor in the design and installation conditions of equipment.

[Problem that the invention seeks to solve]

Next, using FIGS. 3 to 5, the signal propagation delay based on the above-mentioned difference in cable length will be explained using a magnetic disk device as an example.

FIG. 3 is a block diagram showing an example of a data processing device, and as shown in the figure, a processing device (hereinafter referred to as CPU) 11
and a magnetic disk controller (hereinafter referred to as DKC) 12
and string controller (hereinafter referred to as DSC) 1
3a, 13b and disk unit (hereinafter referred to as DKU)
Saletail composed of 14a, 14b. The lengths of the interface cables 16a and 16b that connect the DKC 12 and the 'DSCs 13a and 13b vary depending on the system installation situation. In the system shown in Figure 3, CP Ul
The data transferred from l is stored as a record in DKU14a.
, 14b. Records are recorded corresponding to unique addresses. Normally, this address includes the disk device address #O, #1, etc., the head number of the disk device, the track number, and a designation (seek operation) regarding the position on the track based on a predetermined starting point called an index. include.

Data is stored in DKU1 under program control of CP Ull.
4a, 14b and CP Ull. D.K.
The function of C12 is to decode the instructions output from CP Ull. The DKU 12 sends a series of instructions to the DSCs 13a and 13b in response to these instructions. This command includes one that commands actual read/write operations by the DKUs 14a and 14b (read/write), and a predetermined (7) D
These include selecting the KU 14a, 14b or the DSC 13a, 13b (select), positioning the head on a predetermined track (access), and obtaining status information regarding a specific DKU 14a, 14b or DSC 13a, 13b (sense).

FIG. 4 is a circuit diagram showing details of the DKU 12 and DSC 13a, and FIG. 5 is a time chart showing the operation of the DSC 13a. To transfer write data from CPU II to DKU14a, DSC13a sends signal 5YNC to DKU12.
It is initiated in response to sending an IN.

When DKU12 receives signal 5YNCIN, CP 01
It outputs the data byte transferred in advance from 1 as the signal BO, and sends the signal 5YNCOUT to the DSC 13a.

In this case, as shown in FIG. 5, the propagation delay time T from when the signal 5YNCIN is sent until the signal 5YNCOUT is input changes depending on the length of the cable 16a. The DSC 13a transfers the data byte, which is the content of the signal BO, to the buffer 28 or 2 in synchronization with the signal 5YNCOUT.
Set to 9. The buffers 28 and 29 shown in FIG.
It is a byte buffer, and the gate signal A is output from the flip-flop 30 by the signal 5YNCOUT.

Since B alternately repeats "1" and "0°", the signal BO is set alternately in the buffers 28 and 29 for each byte.The DSC 13a is set until the last data byte of the signal BO is transferred. , signal 5YNCIN is repeatedly sent to the DKC 12 at intervals of period T. The data bytes set in the buffers 28 and 29 are alternately input to the write circuit 34. The write circuit 34 serializes the input data bytes. , and is encoded and applied to the magnetic head of the DKU 14a.

As shown in FIG. 5, data bytes D1 to D6 input as signal BO are stored in one of the buffers 28 and 29 at the timing when signal 5YNCOUT is input.

The data bytes Di, D3 . D
5... is the data byte D2.5 in the buffer 29. D4.
The data is input to the write circuit 34 at the timing when D6... is stored, serialized and encoded, and then output as write data WD. Similarly, data bytes D2 . D4, D6, . . . store data bytes D3, . D5°... is input to the write circuit 34 at the timing when it is stored, and after being serialized and encoded, it is output as write data WD. In this way D
Data bytes DI, D2... output from SC13a
. is applied to the magnetic head of the DKU 14a. Furthermore, the fifth
In the figure, signal BR indicates a bit ring signal.

The DSC 13a is synchronized with the DKU 14a, and the first serialized data byte D1 is recorded on the track when a predetermined address position is located below the head.

To guarantee this, the magnetic disk drive outputs a signal 5YNCIN as the magnetic disk rotates, and when the address position where data byte D1 is recorded is directly below the head, the head receives and accepts data byte D1. It is structured like this.

However, if the length of the cable 16a is changed depending on the installation status of the system, the time T0 from the generation of the signal 5YNCIN to the arrival of the signal 5YNCOUT, that is, the propagation delay time will vary depending on the length of the cable 16a. Change. Normally, the propagation delay time of the cable itself used for the interface cable 16 is about 5 nal seconds per 1 m, and when the data transfer rate is 3 MB/s,
The period T shown in the figure is 333+1 seconds, and in the example shown in FIG. 4 with the data buffer 28.29, the cable 16
The length of a is allowed to be approximately 0 to 60 m.

However, as the data transfer rate increases from 3 MB/s to 4.5 or 6 MB/s, the signal 5YNC
The period T at which IN is output is 222+1 seconds or 167
Therefore, it becomes necessary to limit the length of the cable 16a from approximately 60 meters to 45 or 30 meters or less, or to increase the data buffer in the DSC 13a in addition to the buffers 28 and 29.

The first method of solving the cable length problem using conventional technology is to provide an appropriate number of buffer stages in the magnetic disk drive and buffer the data before the data is needed. The idea is to put it in. However, this method has the problem that as the data transfer speed increases, the number of buffer stages must be increased, making control complicated.

The second way to solve the cable length problem is to
For example, as described in Japanese Unexamined Patent Publication No. 55-23595, from the point in time when a control signal is sent from the receiving device to the transmitting device before starting data transfer to the point in time when the control signal is sent from the transmitting device to the receiving device. Propagation delay measurements are made by measuring the time between. As a result, during a data transfer, the control signal requesting the first data byte from the transmitting device is sent an appropriate number of bytes and bit times in advance of the point in time required to record that data byte on the disk device. Ru. However, this method has
There are problems in that the control method is complicated and the control circuits of the transmitting device and the receiving device must be changed at the same time.

The present invention was devised in view of the above-mentioned problems of the prior art, and it does not require the need to increase the data buffer of the receiving device (or shorten the cable length), and has a simple configuration that allows the data to be recorded to be stored as needed. The object of the present invention is to provide a controllable data transfer method so that the data arrives at the specified time.

[Means for solving problems]

In the data transfer method of the present invention, a first device and a second device are connected by a cable, and a response signal and data are sent from the second device in response to a data transfer request signal output from the first device. to a first device, in particular:
It is determined whether the time from when the request signal is output from the first device until when the response signal is input is within a predetermined time, and if it is determined that it is within the predetermined time, the request from the first device is It is characterized by delaying signal transmission.

[Effect]

According to the present invention, the data transfer rate between the first device and the second device is determined based on the time from when a request signal is output to when a response signal is input. and,
If it is determined that the data transfer rate is higher than the reference, the sending of the request signal is delayed. As a result, it becomes possible to transfer the data to be recorded at the required time without increasing the data buffer of the first device, without limiting the cable length, and with a simple configuration.

〔Example〕

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of a data transfer control device showing one embodiment of the present invention. The illustrated data transfer control device is composed of AND circuits 1, 2.3, a NAND circuit 5.6, and flip-flops 6.7.8.9. A signal 5YNCIN formed by a DSK (not shown) is input to AND circuit 3 on one side, and input to AND circuit 1 on the other side. AND circuit 3 is flip-flop 9
The gate is opened and closed in accordance with the output of the gate, and the signal 5YNCIN' is outputted to the DKC (not shown) accordingly. If the time from when the signal 5YNCIN' is output to when the signal 5YNCOUT is input is shorter than a predetermined time, the signal 5YNCIN' closes the AND circuit 3 and outputs the signal 5YNCIN'.
If the sending of CIN' is delayed and exceeds the specified time,
The signal 5YNCIN is output as is as the signal 5YNCIN'.

That is, the first signal 5YNCIN output from the DSC is sent to the DK as a signal 5YNCTN' via the AND circuit 3.
Transferred to U. At the same time, the first signal 5YNCI
N sets the flip-flop 6 via the AND circuit 1. Next, when the second signal 5YNCIN is input from the DSC, the flip-flop 6 is reset and the flip-flop 7 is set. Here, the flip-flop 6.7 operates as a binary counter that counts the number of signals 5YNCIN, and when the third signal 5YNCIN is input, the AND circuit 4 stops its operation. If the signal 5YNCOUT output from the DKC in response to the first signal 5YNCIN' is input before the second signal 5YNCIN is input, the NAND circuit 5 Flip-flop 8 is set via . Then, among the 0" to "7" of the tring signal BR for generating the signal 5YNCIN at the period T, "
The flip-flop 9 is set by the signal BRO indicating the timing of 0P, and the third signal 5YNCIN is inhibited by the AND circuit 3. Furthermore, since the third signal 5YNCIN is input to the AND circuit, the flip-flop 8 is reset via the NAND circuit 4, and then the flip-flop 9 is reset at the timing of the signal BRO. signal 5YN
CIN is never inhibited by AND circuit 3.

Also, the first signal 5 in response to the first signal 5YNCIN
If YNCOUT is input before the second signal 5YNCIN is input, as shown in FIG. 2(b), flip-flop 8 and flip-flop 9 are not set, so the signal is sent to DKC. Signal 5YNCIN is never inhibited by AND circuit 3.

Therefore, the number of signals 5YNCOUT in response to signal 5YNCIN at short and maximum cable lengths is
By the time the first data byte is needed, two
Therefore, two data buffers are sufficient. In addition, by performing this kind of control, the data transfer rate increases from 3 MB/s to 4.5 MB/s to 6 MB/s, and the signal
VNCIN period wiT is 222 + 1 seconds, or 1
Even if it is as short as 67+1 seconds, it becomes possible to cope with the above-mentioned higher data transfer speed without limiting the cable length to a shorter length.

In the above embodiment, the second signal 5YNCI
It was determined whether to inhibit the second signal 5YNCIN based on whether 5YNCOUT corresponding to the first signal 5YNCIN is input before N is input. However, the present invention is not limited to this, and for example, it is determined whether the time from when the first signal 5YNCIN is output until when the first signal 5YNCOUT is inputted is within a predetermined time, and the th signal 5Y
NCIN may be inhibited, and as the data transfer speed increases, multiple signals 5YN may be inhibited.
It may be configured to inhibit CIN.

Although the above embodiment has been explained using a magnetic disk device as an example, the present invention is not limited to this, and can be applied when the data transfer speed is increased on the transmitting side and the receiving side. It is.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, data to be recorded can be easily stored without increasing the number of data buffers in the receiving device and without shortening the cable length. This has the effect of making it possible to transfer the data at the point where the data is transferred.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1, and FIG. 3 is a conventional data processing system. FIG. 4 is a block diagram showing an example of the magnetic disk controller (DKC) and string controller (DS) shown in FIG.
A block diagram showing a specific example of C), and FIG. 5 is a time chart showing the operation of the string controller (DSC) shown in FIG. 4. 1.2.3...AND circuit, 4,5...NAND circuit, 6.7.8.9...flip-flop.

Claims (1)

[Claims] 1. A first device and a second device are connected by a cable, and in response to a data transfer request signal output from the first device, a response signal and data are transferred from the second device to the first device. In a data transfer method, it is determined whether the time from the output of a request signal from the first device until the input of a response signal is within a predetermined time, and if it is determined that the time is within a predetermined time, the first A data transfer method characterized by delaying the sending of a request signal from one device.