JPS6330078U - - Google Patents
Info
- Publication number
- JPS6330078U JPS6330078U JP12207286U JP12207286U JPS6330078U JP S6330078 U JPS6330078 U JP S6330078U JP 12207286 U JP12207286 U JP 12207286U JP 12207286 U JP12207286 U JP 12207286U JP S6330078 U JPS6330078 U JP S6330078U
- Authority
- JP
- Japan
- Prior art keywords
- agc
- video signal
- gain control
- circuit
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案の自動利得制御回路の構成図、
第２図は出力映像信号の波形図、第３図はＡＧＣ
が制御範囲からはずれた時の出力映像信号の波形
図、第４図はＡＧＣ用増幅器の出力波形図、第５
図は出力映像信号のペデスタルレベルの変化の様
子を示す波形図、第６図は差動増幅器入力電位の
関係を示す波形図である。
１：ＡＧＣ用増幅器、２：復調器、３：差動増
幅器、４：サンプルホールド回路、５：抵抗、６
：基準電圧源、７：比較器、８：サンプルホール
ド回路、９：基準電圧源。
Figure 1 is a configuration diagram of the automatic gain control circuit of the present invention.
Figure 2 is a waveform diagram of the output video signal, Figure 3 is the AGC
Figure 4 is a waveform diagram of the output video signal when deviates from the control range. Figure 4 is the output waveform diagram of the AGC amplifier. Figure 5 is the output waveform diagram of the AGC amplifier.
The figure is a waveform diagram showing changes in the pedestal level of the output video signal, and FIG. 6 is a waveform diagram showing the relationship between the input potentials of the differential amplifier. 1: AGC amplifier, 2: Demodulator, 3: Differential amplifier, 4: Sample and hold circuit, 5: Resistor, 6
: Reference voltage source, 7: Comparator, 8: Sample and hold circuit, 9: Reference voltage source.
Claims (1)
映像信号回路において、その出力映像信号のペデ
スタル部分をサンプリングホールドする回路と、
該サンプリングした電位と予め設定された基準電
位とを比較し、上記ＡＧＣループが制御範囲から
はずれた際に、利得制御形増幅器のゲインを強制
的にＡＧＣ制御範囲内に引き込む方向に制御する
手段とを有することを特徴とした自動利得制御回
路。 In a video signal circuit constituting an automatic gain control (hereinafter referred to as AGC) loop, a circuit that samples and holds a pedestal portion of the output video signal;
means for comparing the sampled potential with a preset reference potential and forcibly controlling the gain of the gain control amplifier in a direction to bring it within the AGC control range when the AGC loop deviates from the control range; An automatic gain control circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12207286U JPS6330078U (en) | 1986-08-11 | 1986-08-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12207286U JPS6330078U (en) | 1986-08-11 | 1986-08-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6330078U true JPS6330078U (en) | 1988-02-27 |
Family
ID=31011930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12207286U Pending JPS6330078U (en) | 1986-08-11 | 1986-08-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6330078U (en) |
-
1986
- 1986-08-11 JP JP12207286U patent/JPS6330078U/ja active Pending
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