JPS5920714U - gain control circuit - Google Patents

gain control circuit

Info

Publication number
JPS5920714U
JPS5920714U JP11540082U JP11540082U JPS5920714U JP S5920714 U JPS5920714 U JP S5920714U JP 11540082 U JP11540082 U JP 11540082U JP 11540082 U JP11540082 U JP 11540082U JP S5920714 U JPS5920714 U JP S5920714U
Authority
JP
Japan
Prior art keywords
control circuit
gain control
control voltage
gain
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11540082U
Other languages
Japanese (ja)
Inventor
本橋 実
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP11540082U priority Critical patent/JPS5920714U/en
Publication of JPS5920714U publication Critical patent/JPS5920714U/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の利得制御回路の一例を示す回路図、第2
図は第1図の特性図、第3図はこの考案による利得制御
回路の一実施例を示す回路図、第4図は第3図の特性図
である。 1・・・コントローラ、2・・・ディジタル・アナログ
コレバータ、3・・・電子ボリューム回路、4・・・ア
ンドゲート、Q□〜Q、・・・トランジスタ、R1,R
2・・・可変抵抗器、R,、R4・・・抵抗。
Figure 1 is a circuit diagram showing an example of a conventional gain control circuit;
1 is a characteristic diagram of FIG. 1, FIG. 3 is a circuit diagram showing an embodiment of the gain control circuit according to this invention, and FIG. 4 is a characteristic diagram of FIG. 3. 1... Controller, 2... Digital/analog corrector, 3... Electronic volume circuit, 4... AND gate, Q□~Q,... Transistor, R1, R
2...Variable resistor, R,, R4...Resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 直流コントロール電圧を用いて利得を制御する利得制御
回路において、前記コントロール電圧に直流バイアスを
加える手段と、前記コントロール電圧が設定値を越えて
低下した事を検出する検出手段と、この検出手段の出力
によって作動することにより前記コントロール電圧をオ
フ制御する回路とを備えたことを特徴とする利得制御回
路。
A gain control circuit that controls gain using a DC control voltage, comprising means for applying a DC bias to the control voltage, a detection means for detecting that the control voltage has decreased beyond a set value, and an output of the detection means. A gain control circuit comprising: a circuit that controls the control voltage to be turned off by operating the gain control circuit.
JP11540082U 1982-07-29 1982-07-29 gain control circuit Pending JPS5920714U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11540082U JPS5920714U (en) 1982-07-29 1982-07-29 gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11540082U JPS5920714U (en) 1982-07-29 1982-07-29 gain control circuit

Publications (1)

Publication Number Publication Date
JPS5920714U true JPS5920714U (en) 1984-02-08

Family

ID=30266397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11540082U Pending JPS5920714U (en) 1982-07-29 1982-07-29 gain control circuit

Country Status (1)

Country Link
JP (1) JPS5920714U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5535584A (en) * 1978-09-06 1980-03-12 Matsushita Electric Ind Co Ltd Sound volume controller

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5535584A (en) * 1978-09-06 1980-03-12 Matsushita Electric Ind Co Ltd Sound volume controller

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