JPS6329933A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a distinct alignment mark with high precision by shaping a protective layer having etching resistance near the forming region of the alignment mark prior to a pattern forming process including a taper etching process. CONSTITUTION:A PSG film is shaped onto a semiconductor substrate 1, to which a desired element region, etc. are formed, as a layer insulating film 2. A process in which an etching-resistant protective layer 3 is shaped for avoiding the formation of a taper in a taper etching process onto a film to be patterned in the vicinity of the forming region of an alignment mark M is included prior to a patterning process containing the taper etching process. In the pattern of a PSG film shaped in this manner, the upper edge of a pattern edge takes a tapered shape, the step coverage of a wiring conductor formed to an upper layer can be improved while the pattern edge of the alignment mark M keeps a vertical distint state, thus also maintaining the precision of alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to the formation of alignment marks in a taper etching process.

[Prior art and its problems 1 In recent years, the integration of semiconductor devices has been significantly advanced.
Elements are becoming increasingly thinner.

With the miniaturization of devices, a patterning method using orientational etching is attracting attention due to the demand for higher pattern precision.

According to anisotropic etching, there is no side etching and a pattern faithful to the mask pattern can be obtained. However, the edges (α) of the pattern obtained by anisotropic etching are steep.

For example, when anisotropic etching is used to form a contact hole in an insulating film, the edges of the pattern are steep, which can reduce the step coverage of the wiring conductor formed in the upper layer, leading to disconnections. .

Therefore, I created a taper at the top of the edge of the pattern.
Various techniques have been proposed for improving the step coverage of upper layer wiring conductors.

For example, when forming a contact hole in the silicon oxide film 100 using a reactive ion etching (RIE) method using an R resin pattern as a mask, oxygen is introduced and the mask is slightly etched to widen the opening. There is a method of forming the contact hole H. The contact hole formed by this method has a tapered opening, as shown in FIG.

By the way, in the manufacturing process of a semiconductor device, a photolithography process is used many times. Therefore, pattern alignment in each process is an important point.
In particular, as elements become increasingly finer, extremely high alignment accuracy is required. When forming the contact hole, an alignment mark used for alignment with the upper layer wiring conductor is formed at the same time. However, if the above-mentioned taper etching is performed when forming the contact hole, the alignment mark also ends up having a tapered side surface.

Auto-alignment type exposure equipment usually uses a laser alignment method, but if the upper edge of the alignment mark has a taper, if a patterned W1 body such as an aluminum alloy film is formed on this, the laser The reflected light becomes complicated, resulting in a decrease in alignment accuracy.

In this way, the required profiles of the element pattern and the alignment pattern are contradictory.

This means that the interlayer insulation can be divided into two layers: the PSG film and the BPSG film.
After forming a contact hole using anisotropic etching, a cleaning process using dilute hydrofluoric acid is introduced to taper the edge of the contact hole by utilizing the difference in etching speed between PSGgl and BPSGI13. The same is true if you do this.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to improve pattern accuracy of alignment marks and improve alignment accuracy in a film patterning process including taper etching.

[Means for Solving the Problems] Therefore, in the present invention, prior to the patterning process including the taper etching process, a taper is formed in the taper-etching process on the film to be patterned in the vicinity of the alignment mark forming area. In order to avoid this, the method includes a step of forming an etching-resistant protective layer.

[Function] Even in the taper etching process, formation of a taper can be avoided near the alignment mark, and an alignment mark with a pattern edge whose cross section is almost vertical is formed, while other parts such as contact holes are well formed. A pattern having a tapered pattern edge can be formed.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(d) are explanatory diagrams showing the process of forming an interlayer insulating film according to an embodiment of the present invention.

First, as shown in FIG. 1(a), an interlayer insulating film 2 is placed on a semiconductor substrate 1 on which a desired element region (not shown), etc. is formed.
As a result, a PSG film having a thickness of 1.2IJIn is formed.

Next, a thin layer of silicon nitride (3i3N4) with a film thickness of 500 to 1000 layers is formed on this upper layer, followed by a normal photolithography process and chemical dry etching (isotropic).
By removing unnecessary parts, a protective film 3 is formed only in the vicinity of the region where the alignment i-mark is to be formed, as shown in FIG. 1(b).

Subsequently, as shown in FIG. 1 (tc), a resist pattern 4 for forming a contact hole 1-1 is formed by photolithography. It is assumed that this resist pattern has an opening window W for forming the contact hole 1 as well as an opening window W' for forming the alignment mark M.

After this, tetrafluoromethane (CH4) decahydrogen (H2
) by reactive ion etching using a mixed gas of
Opening window W of resist pattern 4'.

The PSG film (interlayer insulating film) 2 in W' is selectively removed, but during the etching process, the 'Fi element (0
2) is introduced and etched while widening the opening of the resist pattern to form a contact hole H and an alignment mark M. At this time, the edge of a pattern such as a contact hole becomes tapered due to the retreat of the resist pattern, but since the protective layer 3 is formed in the vicinity of the alignment mark, the etching process is slow in this area, and side etching is also prevented. Therefore, an alignment mark M having a vertical pattern edge is formed. (Fig. 1(d)) The PSG film pattern formed in this way has a tapered upper edge of the pattern edge, which improves the step coverage of wiring and line conductors formed in the upper layer. In addition, since the pattern edges of the alignment marks remain vertical and clear, alignment accuracy can also be maintained well.

Next, other embodiments of the present invention will be described.

FIGS. 2(a) to 2(e) are explanatory diagrams showing the process of forming an interlayer insulating film.

First, as shown in FIG. 2(a), a first insulating film 12a made of a PSG film and a BPSG film are deposited on a semiconductor substrate 11 on which a desired element region (not shown) is formed.
After forming the second insulating film 12b made of a film, an insulating layer is applied to this upper layer. A thin silicon nitride film having a thickness of 500A to 1000A is formed as F5 as No. 13.

Next, through a normal photolithography process, the silicon nitride film is left only in the vicinity of the portion where the alignment mark is to be formed, and the rest is removed by chemical dry etching. (FIG. 2(b)) Subsequently, as shown in FIG. 2IC, a resist pattern 14 for forming a contact hole (H) is formed by photolithography. It is assumed that this resist pattern also has an opening window W' for forming the alignment mark M in addition to the opening window W for forming the contact hole 1.

After this, tetrafluoromethane<CF4) decahydrogen (H
By reactive ion etching using the mixed gas of 2), an open window w is formed using the resist pattern 14 as a mask.
Selectively remove the PSG axilla and BPSG membrane within w'. At this time, although the etching process is different, since the silicon nitride film is also etched under the same conditions, alignment marks ~1 are also formed at the same time. (FIG. 2(d)) Further, after removing the resist pattern R, dilute hydrofluoric acid treatment is performed which also serves as cleaning of the substrate 11. Here, BPSG is P
Since the etching speed for hydrofluoric acid is sufficiently higher than that for SG, only the upper 11 BPSG is etched, and the pattern edge at the contact hole portion is tapered as shown in FIG. 2(e). On the other hand, in the alignment mark M portion, since silicon nitride has high resistance to hydrofluoric acid, the silicon nitride film maintains the same pattern, and an alignment mark M having a sharp pattern edge is formed.

The pattern of the interlayer insulating film made of the first insulating film and the second insulating film formed in this way has a tapered upper edge of the pattern edge, and the wiring 4 formed in the upper layer has a tapered upper edge.
The step coverage of the body can be improved, and the pattern edge of the alignment mark maintains a clear shape at the upper edge, making it possible to maintain good alignment accuracy.

In addition, although the embodiment describes the formation of an interlayer insulating film, it goes without saying that the present invention is not limited to the formation of an interlayer insulating film and can also be applied to the formation of conductor layers such as wiring layers.

Furthermore, although anisotropic dry etching was used in the etching process for pattern formation in the embodiment, the method of the present invention is also applicable to cases where anisotropic wet etching is used.

[Effects] As explained above, according to the method of the present invention, prior to the pattern forming process including the taper etching process, etching resistance equivalent to that of the taper etching process is provided in the vicinity of the alignment mark forming area. As a result, a clear and highly viscous alignment mark is formed, and a pattern with a good tapered pattern edge can be formed, providing a highly reliable semiconductor device. can do.

[Brief explanation of drawings]

1(a) to (d) are diagrams showing the formation process of an interlayer insulating film according to an embodiment of the present invention, and FIGS. 2(a) to (e) are diagrams showing an interlayer insulating film of another embodiment of the present invention. Figure 3 showing the formation process of
The figure shows a cross-sectional shape of a contact hole and an alignment mark formed by a conventional method. 100... Silicon oxide film, 1, 11... Semiconductor substrate, 2.12... Interlayer insulating film, 12a... First insulating film, 12b... Second insulating film, 3...・Protective layer, 4
゜14...Resist pattern, W, w'...Opening window,)''...Contact hole, M...Alignment mark. Applicant's representative Takahisa Kimura Figure 1 (G) Figure 1 (b) Figure 1 (C) Figure 1 (d), B at
JQ Ro Sunnohehe-Sunnoheheichi

Claims (6)

[Claims] (1) In the pattern formation process including the taper etching process, prior to forming the etching mask, the process includes the process of forming a protective layer on the film to be patterned in the vicinity of the alignment mark formation area in order to avoid the formation of a taper. A method for manufacturing a semiconductor device, characterized in that: (2) The taper etching step is a step of etching the etching mask so that the pattern edge becomes tapered, and the protective layer has a sufficient etching rate compared to the etching mask and the film to be patterned. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is made of a slow material. (3) The pattern forming process is an anisotropic dry etching process, and includes a taper etching process in which the reaction gas is changed in the middle of the process to slightly etch even the etching mask. A method for manufacturing a semiconductor device according to scope (2). (4) The film to be patterned is a first film made of a different material.
and a second film are sequentially stacked, and in the taper etching step, after the etching mask is removed, the etching rate of the first film is set to the second film.
A process having etching conditions that is sufficiently lower than the etching rate of the film, and the protective layer is made of a third film that has etching resistance under the etching conditions. A method for manufacturing a semiconductor device according to item (1). (5) The method for manufacturing a semiconductor device according to claim (4), wherein the taper etching step is a wet treatment step using hydrofluoric acid. (6) The method for manufacturing a semiconductor device according to claim (5), wherein the first film is a PSG film, and the second film is a BPSG film.