JPS63296963A - Manufacture of recording electrode plate - Google Patents

Manufacture of recording electrode plate

Info

Publication number
JPS63296963A
JPS63296963A JP13186687A JP13186687A JPS63296963A JP S63296963 A JPS63296963 A JP S63296963A JP 13186687 A JP13186687 A JP 13186687A JP 13186687 A JP13186687 A JP 13186687A JP S63296963 A JPS63296963 A JP S63296963A
Authority
JP
Japan
Prior art keywords
plating
base material
metal layer
conductor circuit
resist mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13186687A
Other languages
Japanese (ja)
Inventor
Takeshi Kanda
神田 武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meiko Electronics Co Ltd
Original Assignee
Meiko Electronics Co Ltd
Meiko Denshi Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Electronics Co Ltd, Meiko Denshi Kogyo Co Ltd filed Critical Meiko Electronics Co Ltd
Priority to JP13186687A priority Critical patent/JPS63296963A/en
Publication of JPS63296963A publication Critical patent/JPS63296963A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/385Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective supply of electric current or selective application of magnetism to a printing or impression-transfer material
    • B41J2/39Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective supply of electric current or selective application of magnetism to a printing or impression-transfer material using multi-stylus heads
    • B41J2/395Structure of multi-stylus heads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern

Abstract

PURPOSE:To obtain a recording electrode plate on which a conductive circuit of a good transfer property and high density is certainly formed without any pinhole on the conductive circuit part, by a method wherein a thin film metal layer is placed between a conductive circuit and a conductive base material, and the conductive circuit is plated with gold by performing plating formation of the thin film metal layer and the conductive circuit by a specific method. CONSTITUTION:A part of a cathode is made from a plate conductive base material 2 of 0.08-0.23mum in surface roughness, and a distance between the cathode 1 and a plate anode is made 3-30mm. Electrolyte is so supplied that a wetted speed becomes 2.6-20.0m/sec. A thin film metal layer 5 of 1-5mum in thickness is formed by electrolytic plating under conditions of 0.15-4.0A/cm<2>. A surface of the thin film metal layer 5 of which on the surface excepting a conductive circuit 6 a resist mask is formed, is processed by gold plating and nickel plating 4. After forming the conductive circuit 6 by plating thereon under the same conditions by using copper ion electrolytic, the resist mask is peeled off and the surface is roughened. A laminar material is formed by laminating copper foils thereon via an insulating base material 10, and only the conductive base material is peeled off therefrom. After forming a through hole in this laminar material, its inner wall face and both faces of the laminar material are plated by copper and a resist mask is formed on the part other than the circuit. After solder plating on both faces of the laminar material, it is peeled off and both faces of the laminar material are etched.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、例えばファクシミリ、プリンター等各種OA
機器の記録部に使用される記録電極板の製造方法に関す
る。
Detailed Description of the Invention (Industrial Application Field) The present invention is applicable to various OA applications such as facsimiles and printers.
The present invention relates to a method of manufacturing a recording electrode plate used in a recording section of a device.

(従来の技術及びその問題点) 近年、ファクシミリ、プリンター等の記録部において、
静電記録、通電感熱記録、放電破壊記録等の方式に使用
される記録電極板は、通常、基板の一端部に複数本の帯
状導体が一定間隔で互いに平行に配列された電極部を有
するもので、この導体の端部は駆動回路に接続されてい
る。又、この記録電極板の導体密度は8〜12本/叫程
度が望まれている。
(Prior art and its problems) In recent years, in the recording section of facsimiles, printers, etc.
Recording electrode plates used in methods such as electrostatic recording, energized thermal recording, and discharge breakdown recording usually have an electrode section at one end of the substrate in which multiple strip-shaped conductors are arranged parallel to each other at regular intervals. The end of this conductor is connected to the drive circuit. Further, it is desired that the conductor density of this recording electrode plate is about 8 to 12 conductors/conductor.

従来、かかる記録電極板を製造する方法として、例えば
、銅張積層板をエツチングして所望のパターンを形成す
る方法が知られている。具体的には、銅張It層板表面
にレジストマスクを形成したのちエツチングを行って所
定の線密度の導体回路を形成するものである。しかしな
がら、銅張積層板において、銅箔の厚さは通常30μm
以上と厚いため、線密度は高々5本/工程度となってし
まう。
Conventionally, as a method of manufacturing such a recording electrode plate, for example, a method of etching a copper-clad laminate to form a desired pattern is known. Specifically, a resist mask is formed on the surface of a copper-clad It layer board, and then etching is performed to form a conductor circuit with a predetermined linear density. However, in copper-clad laminates, the thickness of copper foil is usually 30 μm.
Because of the thickness, the linear density is at most 5 lines/process.

又、厚さ5〜18mmの薄い銅箔を使用すれば、確かに
8〜12本/湿の線密度を有する回路を形成する二七が
できるが、しかし、回路の断面!(ドツト)が小さくな
るため、印刷密度が低下するという問題が生じる。更に
、銅張積層板の製造工程において発生する銅箔面のキズ
やへこみ等により回路部分の断線、ショート等が発生し
、歩留りが悪いという不都合もある。
Also, if a thin copper foil with a thickness of 5 to 18 mm is used, it is certainly possible to form a circuit with a line density of 8 to 12 lines per wet line, but the cross section of the circuit! Since the dots become smaller, a problem arises in that the printing density decreases. Furthermore, there is also the disadvantage that the yield rate is poor because scratches, dents, etc. on the surface of the copper foil that occur during the manufacturing process of the copper-clad laminate may cause disconnection or short-circuiting of circuit parts.

このような理由から、上記のようなエンチング法に代え
て、導電性基板上の所望の領域のみにメッキを施して回
路を形成したのち、この回路を、例えば、絶縁基材に転
写する、所謂、アディティブ法が提案されている。この
方法は、原理的には微細パターンの形成に有用であるが
、しかし、実際は、導電性基板表面のキズなどによりメ
ッキ層にピンホールが発生するなど、メッキ層の安定形
成が困難であり、更に、導体回路の絶縁基材への転写時
に導体回路が完全に転写されない等の転写不良が生じる
等の種々の問題があり、製造歩留りが低いと同時に、充
分満足すべき線密度の導体回路を形成することは容易で
はないという不具合がある。
For this reason, instead of the above-mentioned etching method, a so-called method is used in which a circuit is formed by plating only a desired area on a conductive substrate, and then this circuit is transferred to, for example, an insulating base material. , an additive method has been proposed. In principle, this method is useful for forming fine patterns, but in reality, it is difficult to form a plated layer stably, as pinholes occur in the plated layer due to scratches on the surface of the conductive substrate. Furthermore, there are various problems such as transfer defects such as incomplete transfer of the conductor circuit when transferring the conductor circuit to the insulating base material, resulting in a low manufacturing yield and at the same time making it difficult to produce the conductor circuit with a sufficiently satisfactory linear density. The disadvantage is that it is not easy to form.

本発明は上述の種々の問題点を解決するためにてされた
もので、導体回路部分にピンホール等が発生せず、しか
も転写性が良好で、製造歩留りが高く、しかも、高密度
の導体回路の形成が確実、且つ安定的に実現できる記録
電極板の製造方法を提供することを目的とする。
The present invention has been made to solve the various problems mentioned above, and has the advantage that pinholes etc. do not occur in the conductor circuit part, the transferability is good, the manufacturing yield is high, and the conductor circuit has high density. It is an object of the present invention to provide a method for manufacturing a recording electrode plate that can realize the formation of a circuit reliably and stably.

(問題点を解決するための手段及び作用)上記目的を達
成するために本発明によれば、表面粗度0.08〜0.
23μmの平板状導電基材を陰極として、該陰極と平板
状陽極を電極間距離3〜30mmだけ離間させ、これら
の電極に対する電解液の接液スピードが2,6〜20.
0m/secとなるように電解液を強制的に供給し、電
流密度0.15〜4.OA/−の条件で電解メッキを施
して前記導電基材に厚さ1〜5μmの薄膜金属層を形成
する工程と、形成した薄膜金属層の、導体回路を形成す
る部分を除く表面にレジストマスクを形成する工程と、
レジストマスクを形成した薄膜金属層表面に、金メッキ
もしくは金メッキ後にニッケルメッキを施してメッキ層
を形成する工程と、このメッキ層上に銅イオンを含有す
る電解液を用いて前記電解メッキ条件と同じ条件で電解
メッキを施して導体回路を形成したのち前記レジストマ
スクを剥離する工程と、形成した導体回路表面に粗面化
処理を施す工程と、斯く形成させた導体回路表面に絶縁
基材を介して銅箔を積層して一体に加熱圧着し積層体を
形成する工程と、この積層体から前記導電基材のみを剥
離する工程と、この積層体にスルーホールを形成したの
ちスルーホールの内壁面及び前記積層体の両面に銅メッ
キを施す工程と、この積層体両面の所望の回路領域を除
く領域にレジストマスクを形成する工程と、積層体両面
に半田メッキを施したのち前記レジストマスクを剥離す
る工程と、この半田メッキ層をマスクとして前記積層体
両面のエツチングを行う工程とから構成したものである
(Means and effects for solving the problems) In order to achieve the above object, according to the present invention, the surface roughness is 0.08 to 0.
A 23 μm flat conductive base material is used as a cathode, the cathode and the flat anode are spaced apart by an inter-electrode distance of 3 to 30 mm, and the contact speed of the electrolyte to these electrodes is 2.6 to 20 mm.
The electrolyte was forcibly supplied at a current density of 0.15 to 4.0 m/sec. A step of forming a thin metal layer with a thickness of 1 to 5 μm on the conductive base material by electrolytic plating under OA/- conditions, and applying a resist mask to the surface of the formed thin metal layer except for the part where the conductor circuit is to be formed. a step of forming;
A step of forming a plating layer by plating gold or nickel plating after gold plating on the surface of the thin film metal layer on which the resist mask has been formed, and applying an electrolytic solution containing copper ions on this plating layer under the same electrolytic plating conditions as described above. A step of peeling off the resist mask after forming a conductor circuit by electrolytic plating, a step of roughening the surface of the formed conductor circuit, and a step of applying an insulating substrate to the surface of the conductor circuit thus formed. A step of laminating copper foils and heat-pressing them together to form a laminate, a step of peeling only the conductive base material from this laminate, and a step of forming a through hole in this laminate and then peeling the inner wall surface of the through hole and A step of applying copper plating to both sides of the laminate, a step of forming a resist mask on both sides of the laminate except for a desired circuit area, and a step of peeling off the resist mask after applying solder plating to both sides of the laminate. and a step of etching both surfaces of the laminate using the solder plating layer as a mask.

上述の薄膜金属層を単板の導電基材と導体回路及び間に
介在させたことによる作用として、以下の3点を上げる
ことが出来る。
The following three points can be raised as effects of interposing the above-mentioned thin film metal layer between the single plate conductive base material and the conductor circuit.

(1)  *膜金属層を介在させた導体回路付単板を絶
縁基材に重ね合わせ、プレスで所定時間加圧加温し、固
化積層後分離すると、単板と薄膜金属層が70〜120
g/cmのピーリング強度で剥離分離ができ、寸法変化
、外観不良のない転写積層が容易にできる。
(1) *A veneer with a conductor circuit with a film metal layer interposed is laminated on an insulating base material, heated under pressure for a predetermined period of time using a press, and separated after solidification and lamination.
Peeling and separation is possible with a peeling strength of g/cm, and transfer lamination without dimensional changes or appearance defects can be easily achieved.

(2)単板導電基材(たとえば、ステンレススチール)
の表面には、化学的、物理的に基材表面を充分に研磨を
施しても、基材内部にある非金属介在物、電気化学的欠
陥による基材中の成分が脱落したり、金属間化合物、偏
析、気孔等が残存しており、これらの欠陥を経済的且つ
完全に補うことが出来ない0本発明の薄膜金属層は基材
の上記欠陥を補うことができ、この結果、ピンホールが
発生せず、従って、幅100!Im以下のファインパタ
ーンの回路基板を容易且つ安価に作製できる。
(2) Single plate conductive base material (e.g. stainless steel)
Even if the surface of the base material is thoroughly polished chemically and physically, components in the base material may fall off due to non-metallic inclusions or electrochemical defects inside the base material, or there may be problems between metals. Compounds, segregation, pores, etc. remain, and these defects cannot be economically and completely compensated for. does not occur, therefore the width is 100! A circuit board with a fine pattern of Im or less can be easily and inexpensively produced.

(3)単板導電基材に薄膜金属層及び銅回路を形成した
後、絶縁基材への転写積層を加熱圧着工程で実施するが
、この際、絶縁基材に塗布又は含浸したBステージの樹
脂接着剤が溶融且つゲル化過程及び固化過程で単板導電
基材の周縁部表面に流出しようとするが、この薄膜金属
層を単板基材周縁部までの広がりで単板導電基材表面を
全面的に被覆しておくことにより、流出固化した樹脂が
薄膜金属層の表面上に留まり、転写積層分離工程で単板
導電基材を薄膜金属層の境界(界面)から容易に分離で
き、単板導を基材に接着剤が密着・付着することが全く
ないという利点がある。
(3) After forming the thin film metal layer and copper circuit on the veneer conductive base material, transfer lamination to the insulating base material is carried out in a heat-press bonding process. During the melting, gelation, and solidification processes, the resin adhesive tends to flow out onto the peripheral surface of the veneer conductive base material, but this thin metal layer spreads to the veneer base material's periphery and spreads onto the surface of the veneer conductive base material. By covering the entire surface, the solidified resin will remain on the surface of the thin metal layer, and the veneer conductive substrate can be easily separated from the boundary (interface) of the thin metal layer in the transfer lamination separation process. It has the advantage that the adhesive does not adhere or adhere to the single-plate conductor as a base material.

次に、第1図ないし第13図に基づき、本発明方法によ
る記録電極板の製造工程を説明すると、先ず、本発明方
法の実施に使用される導電基材2としでは、剛性を有す
る単板、例えば、有効寸法最大1220 X 1020
mm、厚み1〜10a+mの範囲の適宜の大きさの平板
状導電材からなり、メッキ工程で使用する薬品に対する
耐薬品性、耐電食性を有することが望ましく、ステンレ
ススチール板(例えば、ハードニング処理を施した5U
S630が好適テある)、ニッケル板、チタン又はチタ
ン合金板、銅又は銅合金板等が使用される。この導電基
材2の表面の汚れ、酸化皮膜を除去すると共に、該表面
に所要の粗度を与える前処理工程を施す(第1図(a)
)。導電基材2の表面は、0.08〜0.23μmの範
囲の粗度で研磨するのが望ましい、この導電基材2の表
面粗度は、次工程で導電基材2上に形成される薄膜金属
層(薄銅膜)5の密着強度やピンホールの発生、更には
薄膜金属層5の表面粗度にも影響を与える。又、上述の
粗度規定範囲は薄膜金属層5が後述する保護層4及び導
体回路6のメッキ等の工程時に無闇に剥離せず、しかも
、後述する導電基材2の剥離工程(第1図(i))にお
いて容易に剥離できる密着性が得られるように設定され
たもので、導電基材2と薄膜金属層5間の界面8の密着
力、及び後述の薄膜金属層5とレジスト膜7間の界面9
(第3図参照)の密着力に差が生じるように、即ち、界
面9の密着力が界面8の密着力より大となるように設定
しである。
Next, the manufacturing process of the recording electrode plate according to the method of the present invention will be explained based on FIGS. , for example, effective dimensions maximum 1220 x 1020
It is made of a plate-like conductive material of an appropriate size in the range of 1 to 10 mm thick and 1 to 10 mm thick, and preferably has chemical resistance and electrolytic corrosion resistance against chemicals used in the plating process. 5U applied
S630 is preferred), nickel plate, titanium or titanium alloy plate, copper or copper alloy plate, etc. A pretreatment process is performed to remove dirt and oxide film from the surface of the conductive base material 2, and to give the surface a desired roughness (Fig. 1(a)).
). The surface of the conductive base material 2 is preferably polished to a roughness in the range of 0.08 to 0.23 μm. This surface roughness of the conductive base material 2 will be formed on the conductive base material 2 in the next step. This influences the adhesion strength of the thin metal layer (thin copper film) 5, the occurrence of pinholes, and even the surface roughness of the thin metal layer 5. In addition, the above-mentioned roughness specified range prevents the thin film metal layer 5 from peeling off during processes such as plating of the protective layer 4 and the conductive circuit 6, which will be described later. In (i)), the adhesion is set so that it can be easily peeled off, and the adhesion of the interface 8 between the conductive base material 2 and the thin metal layer 5, and the thin metal layer 5 and the resist film 7 described later. Interface between 9
(See FIG. 3) The settings are such that there is a difference in the adhesion force between the two surfaces, that is, the adhesion force at the interface 9 is greater than the adhesion force at the interface 8.

導電基材2としてステンレススチール板を使用する場合
には、例えば、導電基材2を硫酸80〜10hl/1.
60〜70℃の溶液に10〜30分間浸漬してスケール
除去を行い、次いで、水洗後、硝酸60〜100m 1
 / 12に酸性フッ化アンモニウム30g/ J2を
加えた、室温の溶液に10〜30分間浸漬してスマント
除去を行う。次に、水洗後、リン酸ナトリウム20〜5
0g/ jl!と水酸化ナトリウム50g/ lの電解
液で、電解液温度:室温〜40°C2電流値: 3〜8
A/drrrの電解条件で1〜2分間陰掻電解脱脂を行
う。
When using a stainless steel plate as the conductive base material 2, for example, the conductive base material 2 may be treated with sulfuric acid of 80 to 10 hl/1.
Scale is removed by immersing in a solution at 60-70°C for 10-30 minutes, then washed with water, and then 60-100 m 1 of nitric acid.
/ 12 and 30 g/J2 of acidic ammonium fluoride is added to the solution at room temperature for 10 to 30 minutes to remove the smant. Next, after washing with water, sodium phosphate 20-5
0g/jl! and sodium hydroxide 50g/l, electrolyte temperature: room temperature to 40°C2 current value: 3 to 8
Catching electrolytic degreasing is performed for 1 to 2 minutes under electrolytic conditions of A/drrr.

上述の粗面化処理は化学的に行うものであるが、導電基
材2表面を化学的にクリーニングした後、湿式サンドブ
ラスト(液体ホーニング)等により機械的に粗面化して
もよい。機械的に粗面化する場合には、オシレーション
付のロータリ羽布研磨装置により、例えば、スコッチブ
ライI−1240程度の別布により重研磨した後、水洗
し、その後、スコッチブライト1400〜800程度の
別布により上述し範囲の表面粗度(0,013〜0.2
3μm)になるようにヘアライン仕上げ加工を施す。
Although the above-mentioned surface roughening treatment is performed chemically, the surface of the conductive base material 2 may be chemically cleaned and then mechanically roughened by wet sandblasting (liquid honing) or the like. When roughening the surface mechanically, use a rotary cloth polisher with oscillation to perform heavy polishing with a separate cloth, for example, Scotchbrite I-1240, wash with water, and then apply Scotchbrite I-1240 or so. Surface roughness in the range mentioned above (0,013 to 0.2
A hairline finishing process is applied so that the thickness is 3 μm).

導電基材2としてニッケル板を使用する場合には、例え
ば、リン酸ナトリウム20〜50g/ j!に水酸化ナ
トリウム50g/ lを加えた電解液で、電解液温度:
室温〜40″C1電流値=3〜8A/d nfの電解条
件で1〜2分間陰極電解脱脂を行う、そして、水洗後、
フッ化水素1〜10g/ Q、50°Cの溶液、又は、
塩酸150Ill/l、50°Cの溶液に1〜10分間
浸漬して粗面化し、次いで、水洗後40〜60℃で温水
洗浄を施す。
When using a nickel plate as the conductive base material 2, for example, 20 to 50 g/j! of sodium phosphate. The electrolyte temperature is:
Perform cathode electrolytic degreasing for 1 to 2 minutes under electrolytic conditions of room temperature to 40'' C1 current value = 3 to 8 A/d nf, and after washing with water,
Hydrogen fluoride 1-10g/Q, solution at 50°C, or
The surface is roughened by immersing it in a solution of 150 Ill/l hydrochloric acid at 50°C for 1 to 10 minutes, followed by washing with water and then washing with warm water at 40 to 60°C.

導電基材2としてチタン又はチタン合金板を使用する場
合には、例えば、リン酸ナトリウム20〜50g/ l
 、 50〜60℃の溶液に3〜5分間浸漬してアルカ
リ浸漬脱脂を行う。次いで、水洗後、25Xフツ酸()
IF)−75%硝酸(HNOり溶液に浸漬して化学エツ
チングにより粗面化処理を行う。
When using a titanium or titanium alloy plate as the conductive base material 2, for example, 20 to 50 g/l of sodium phosphate.
, Perform alkaline immersion degreasing by immersing in a solution at 50 to 60°C for 3 to 5 minutes. Then, after washing with water, 25X hydrofluoric acid ()
IF)-75% nitric acid (HNO solution) to roughen the surface by chemical etching.

導電基材2として銅又は銅合金板を使用する場合には、
例えば、リン酸ナトリウム20〜50g/ Qの電解液
で、電解液温度:50〜60°C1電流値:3〜10A
/drrTの電解条件で30秒〜2分間陰極電解脱脂を
行う0次いで、水洗後、フッ化水素1〜Log/ l、
室温以下の溶液で30秒〜2分間酸洗いし、水洗する。
When using a copper or copper alloy plate as the conductive base material 2,
For example, with an electrolyte of sodium phosphate 20-50g/Q, electrolyte temperature: 50-60°C, current value: 3-10A.
/drrT electrolytic degreasing for 30 seconds to 2 minutes. Then, after washing with water, hydrogen fluoride 1 to Log/l,
Pickle in a solution at room temperature or below for 30 seconds to 2 minutes, and then wash with water.

次に、前処理を終えた導電基材2を陰極1として、これ
を陽極14に所定の距離3〜30+ll111だけ離間
させて対峙させ、所謂高速メッキにより導電基材2上に
薄膜金属層5を電解析出させる(第1図ら)、及び第2
図)、薄膜金属層5としては銅、ニッケル等が好適であ
り、これらの薄膜金属層5を1〜5μmの厚みで導電基
材2表面に積層させる。
Next, the pretreated conductive base material 2 is used as the cathode 1, and is faced to the anode 14 at a predetermined distance of 3 to 30+ll111, and a thin metal layer 5 is formed on the conductive base material 2 by so-called high-speed plating. Electrolytic deposition (Fig. 1 et al.), and 2nd
(Figure), copper, nickel, etc. are suitable for the thin film metal layer 5, and these thin film metal layers 5 are laminated on the surface of the conductive base material 2 to a thickness of 1 to 5 μm.

薄膜金属層5として銅を析出させる場合の高速メッキ条
件としては、45〜70°Cのメッキ液を陰極表面にお
いて乱流状態、即ち、電極間距離3〜30 m m s
電極に対する接液スピードが2.6〜20.0m/se
cになるように陰極電極を回転するか、固定i!電極間
強制的に電解液を供給する。このとき、メッキ液として
、例えば、硫酸銅メッキ液、ピロリン酸銅液等を使用し
、陰極電流密度0.15〜4、OA/c+11の電流を
印加し、薄膜金属層の堆積速度が25〜100μm/w
inとなるように設定することが望ましい。
The high-speed plating conditions for depositing copper as the thin film metal layer 5 are as follows: The plating solution at 45 to 70°C is placed in a turbulent flow state on the cathode surface, that is, the distance between the electrodes is 3 to 30 mm s.
Liquid contact speed to electrode is 2.6 to 20.0 m/sec
Rotate the cathode electrode so that c or fix it i! The electrolyte is forcibly supplied between the electrodes. At this time, for example, a copper sulfate plating solution, a copper pyrophosphate solution, or the like is used as the plating solution, and a current with a cathode current density of 0.15 to 4 and OA/c+11 is applied, and the deposition rate of the thin metal layer is 25 to 4. 100μm/w
It is desirable to set it so that it is in.

薄膜金属N5としてニッケルを析出させる場合の高速メ
ッキ条件としては、陰極と陽極とを300〜350mm
で離間させ、この電極間に40〜48°Cのメッキ液を
供給してエア撹拌を行う、このとき、メッキ液として、
例えば、硫酸ニッケル、スルファミン酸ニッケル等を使
用し、陰極電流密度2.2〜4、OA/dn(の電流を
印加し、薄膜金属層の堆積速度が0.8〜1.5μm/
+winとなるように設定することが望ましい。
When depositing nickel as thin film metal N5, the high-speed plating conditions are such that the cathode and anode are 300 to 350 mm apart.
A plating solution of 40 to 48°C is supplied between the electrodes and air agitated. At this time, as the plating solution,
For example, nickel sulfate, nickel sulfamate, etc. are used, and a cathode current density of 2.2 to 4 OA/dn (OA/dn) is applied, and the deposition rate of the thin metal layer is 0.8 to 1.5 μm/dn.
It is desirable to set it so that it is a +win.

尚、薄膜金属層5としてニッケル・リン合金をを用いる
ことも出来、無電解メッキによりニッケル・リン合金を
導電基材表面に析出させる。この場合の無電解ニッケル
メッキ条件としては、35〜55°Cのメッキ液を、導
電基材2表面の接液スピードが40〜80−■/sec
となるように揺動をかける。このとき、メッキ液として
、例えば、次亜リン酸又はボロン系還元剤を用いた無電
解ニッケル液等を使用し、薄膜金属層の堆積速度が30
分間に1〜2μmとなるように設定することが望ましい
Note that a nickel-phosphorus alloy can also be used as the thin metal layer 5, and the nickel-phosphorus alloy is deposited on the surface of the conductive base material by electroless plating. In this case, the electroless nickel plating conditions are such that the plating solution is applied at a temperature of 35 to 55°C, and the liquid contact speed on the surface of the conductive base material 2 is 40 to 80-■/sec.
Shake it so that At this time, for example, an electroless nickel solution using hypophosphorous acid or a boron-based reducing agent is used as the plating solution, and the deposition rate of the thin metal layer is 30%.
It is desirable to set the rate to 1 to 2 μm per minute.

高速電解メッキされた薄膜金属層5は、上述した通り所
要の表面粗度を有する導電基材2に電解積層されるので
薄膜金属層5は導電基材2に適度の密着力で密着してお
り、又、その表面粗度は上述したメッキ条件による高速
メッキによって、後述するレジストマスク7と薄膜金属
層5との所望の密着力を得るに好適な範囲内にある。つ
まり、本発明においては、導電基材の表面粗度、メッキ
液の接液スピード及び電解電流密度の各条件を組み合わ
せることにより、薄膜金属層5の表面粗度を好適に制御
することができる。従って、高速メッキにより積層され
た薄膜金属層5の表面はメッキ後に特別な表面処理を必
要としない。
The thin film metal layer 5 subjected to high-speed electrolytic plating is electrolytically laminated on the conductive base material 2 having the required surface roughness as described above, so the thin film metal layer 5 adheres to the conductive base material 2 with an appropriate adhesion force. Further, the surface roughness is within a suitable range for obtaining desired adhesion between the resist mask 7 and the thin metal layer 5, which will be described later, by high-speed plating under the above-mentioned plating conditions. That is, in the present invention, the surface roughness of the thin film metal layer 5 can be suitably controlled by combining the conditions of the surface roughness of the conductive base material, the contact speed of the plating solution, and the electrolytic current density. Therefore, the surface of the thin film metal layer 5 laminated by high-speed plating does not require any special surface treatment after plating.

又、ステンレススチール板、ニッケル板等からなる導電
基材2には電気化学的欠陥が存在し、こらの欠陥は金属
間化合物、或いは非金属介在物、偏析、気孔等からなり
、これらの欠陥はステンレススチール板の溶製時、圧延
時等に混入生成されるもので、導電基材2の表面処理だ
けでは改善し得ないものである。この欠陥は導体回路6
にピンホールを生じさせ原因となるものである。導電基
材2の表面に形成させた薄膜金属層5表面は電気化学的
に平滑であり、この薄膜金属層5上に後述する導体回路
6を形成させることにより、ピンホールの発生が防止さ
れる。
In addition, electrochemical defects exist in the conductive base material 2 made of a stainless steel plate, a nickel plate, etc., and these defects consist of intermetallic compounds, nonmetallic inclusions, segregation, pores, etc. It is mixed and generated during melting, rolling, etc. of stainless steel plates, and cannot be improved by surface treatment of the conductive base material 2 alone. This defect is caused by conductor circuit 6
This causes pinholes to form. The surface of the thin metal layer 5 formed on the surface of the conductive base material 2 is electrochemically smooth, and by forming a conductor circuit 6 to be described later on the thin metal layer 5, the generation of pinholes is prevented. .

斯く形成された薄膜金属層5の、導体回路6が形成され
る部分を除いた表面に、フォトレジスト法、印刷法等に
よりレジストマスク7が形成される(第1図(C)、第
3図)。レジスト剤としては、前述した通り、導電基材
2及び薄膜金属層5の各表面粗度と相まって、界面9の
密着力を界面8の密着力より相対的に強くすることがで
きるものが選択される。具体的には、感光性レジストフ
ィルムをラミネートする方法もしくは液状の感光性レジ
ストを塗布後乾燥することによりレジスト層を形成し、
露光・現像により所望のパターンのレジストマスク7を
形成する。尚、記録電極部の線密度が低い場合には、例
えばスクリーン印刷法によりレジストマスク7を形成し
てもよい。
A resist mask 7 is formed by a photoresist method, a printing method, etc. on the surface of the thus formed thin film metal layer 5 except for the portion where the conductor circuit 6 is formed (FIG. 1(C), FIG. 3). ). As described above, the resist agent is selected to be one that can make the adhesion of the interface 9 relatively stronger than the adhesion of the interface 8 in combination with the surface roughness of the conductive base material 2 and the thin metal layer 5. Ru. Specifically, a resist layer is formed by laminating a photosensitive resist film or by coating and drying a liquid photosensitive resist.
A resist mask 7 having a desired pattern is formed by exposure and development. Note that if the linear density of the recording electrode portion is low, the resist mask 7 may be formed by, for example, a screen printing method.

しかるのち、上記薄膜金属層5とはエツチング条件の異
なるメッキ層即ち金メッキ層又は金メッキ/ニッケルメ
ッキ層からなる保護層4を形成する(第1図(ロ)、第
4図)、この保護層4は後述する導体回路6の云わば耐
蝕層及び後段の最終的なエツチング工程におけるエツチ
ングストッパとして機能するものである。かかる金メッ
キ及びニンケルメッキの方法は特に限定されるものでは
なく、通常のメッキ方法を適宜適用することができる。
Thereafter, a protective layer 4 consisting of a gold plating layer or a gold plating/nickel plating layer is formed under different etching conditions from the thin film metal layer 5 (FIGS. 1(b) and 4). serves as a so-called corrosion-resistant layer for the conductor circuit 6, which will be described later, and as an etching stopper in the final etching step. The methods of gold plating and nickel plating are not particularly limited, and ordinary plating methods can be applied as appropriate.

次に、上述のようにして薄膜金属層5、レジストマスク
7、メッキ層4を形成させた導電基材2を陰極lとして
、これを陽極14に所定の距離(例えば、3〜3011
m、好ましくは、11〜1511m)だけ離間させて対
峙させ、高速メッキにより導体回路6を薄膜金属層5上
に銅電鋳する(第1図(e)、第5図)、この高速メッ
キの電解液としては、金属銅濃度0.20〜2.0no
f / It 、好ましくは、0.35〜0.98mo
 l / 12 、及び硫酸濃度50〜220g/ l
を含育する硫酸銅メッキ液でよく、メッキの均一性を確
保するために西独間LP−社製(7)CUPPORAP
ID Hs(商品名)を1.5mj!/j!あて添加す
る。又、ピロリン酸銅液等の通常のメッキ液を使用して
もよい。
Next, the conductive base material 2 on which the thin film metal layer 5, resist mask 7, and plating layer 4 have been formed as described above is used as a cathode l, and this is connected to the anode 14 at a predetermined distance (for example, 3 to 3011
m, preferably 11 to 1511 m), and the conductor circuit 6 is electroformed on the thin film metal layer 5 by high-speed plating (Fig. 1(e), Fig. 5). The electrolyte has a metallic copper concentration of 0.20 to 2.0 no.
f/It, preferably 0.35-0.98mo
l/12, and sulfuric acid concentration 50-220g/l
A copper sulfate plating solution containing
ID Hs (product name) 1.5mj! /j! Add by adding. Ordinary plating solutions such as copper pyrophosphate solution may also be used.

又、電流密度0.15〜4A/cd、電極に対する接液
スピード2.6〜20m/sec 、電解液温度45〜
70″c1好ましくは60〜65°Cとなるように夫々
設定する。
In addition, the current density is 0.15 to 4 A/cd, the speed of contact with the electrode is 2.6 to 20 m/sec, and the electrolyte temperature is 45 to 4.
70″c1, preferably 60 to 65°C.

メッキ液温が45°C未満であると、銅イオンの移動速
度が低下するため電極表面に分極層が生じ易くなり、メ
ッキ堆積速度が低下する。一方、液温か70℃を越える
とメッキ液23の蒸発量が多くなり濃度が不安定なると
共に、液温高温化による設備的制限が加わる。
When the plating solution temperature is less than 45° C., the moving speed of copper ions decreases, making it easy to form a polarized layer on the electrode surface, resulting in a decrease in the plating deposition rate. On the other hand, if the liquid temperature exceeds 70° C., the amount of evaporation of the plating liquid 23 increases and the concentration becomes unstable, and equipment restrictions are imposed due to the high liquid temperature.

電流密度と電極に対する接液スピードとを上述の所定の
条件に設定することにより、耐蝕メッキ層4上に、毎分
25〜100μmの堆積速度で導体回路6を堆積させ、
従来のメッキ法の10〜200倍の高能率で銅電鋳を行
うことが出来、実用上極めて大きな意義を有する。しか
も、堆積する銅粒子を極めて微細にすることができ、導
体回路6の伸び率は抗張力を損なうことなく16〜25
%に達する。この伸び率は通常のメッキ法により形成さ
れた導体回路の伸び率より1.5〜2倍以上であり(圧
延アニール銅箔と同等以上の値であり)、極めて柔らか
い銅膜を作製することが出来る。このように圧延アニー
ル銅箔と同等の性能を有することから、高折曲性が必要
なフレキシブル基板において特に有効である。又、生成
した導体回路6の表面粒子を、平均粒子径で3.0〜7
.5μmと極めて微細にすることができ、その結果、続
く粗面化処理(電解メッキ)工程において形成される突
起状析出物も極めて微細なものとすることが出来る。更
に、導体回路6は電気化学的に平滑な薄膜金属層5上に
形成された保護層4上に積層するので、10μm以下の
厚さでもピンホールが生しない。
By setting the current density and the speed of contact with the electrode to the above-described predetermined conditions, the conductor circuit 6 is deposited on the corrosion-resistant plating layer 4 at a deposition rate of 25 to 100 μm per minute,
Copper electroforming can be performed with efficiency 10 to 200 times higher than conventional plating methods, and has extremely significant practical significance. Moreover, the deposited copper particles can be made extremely fine, and the elongation rate of the conductor circuit 6 can be increased to 16 to 25 without impairing the tensile strength.
reach %. This elongation rate is 1.5 to 2 times or more than the elongation rate of a conductor circuit formed by a normal plating method (a value equal to or higher than that of rolled annealed copper foil), making it possible to create an extremely soft copper film. I can do it. Since it has performance equivalent to that of rolled annealed copper foil, it is particularly effective in flexible substrates that require high bendability. Moreover, the surface particles of the generated conductor circuit 6 have an average particle diameter of 3.0 to 7.
.. It can be made extremely fine as 5 μm, and as a result, the protruding precipitates formed in the subsequent surface roughening treatment (electrolytic plating) process can also be made extremely fine. Furthermore, since the conductor circuit 6 is laminated on the protective layer 4 formed on the electrochemically smooth thin film metal layer 5, no pinholes will occur even if the conductor circuit 6 has a thickness of 10 μm or less.

銅電鋳工程において、導体回路6が所要の厚み(例えば
、2μm〜300μm)に達した時点で通電及びメッキ
液の供給を停止し、水洗後、レジストマスク7の除去工
程に進む(第1図(f)、第6図)、このレジストマス
ク7の剥離除去には、例えば、カセイソーダ等の溶解液
が使用され、この溶解液中に30〜60秒浸漬してレジ
ストマスク7を溶解除去し、水洗、乾燥する。
In the copper electroforming process, when the conductor circuit 6 reaches the required thickness (for example, 2 μm to 300 μm), the supply of electricity and the plating solution is stopped, and after washing with water, the process proceeds to the step of removing the resist mask 7 (Fig. 1). (f), FIG. 6), to peel off and remove the resist mask 7, a dissolving solution such as caustic soda is used, and the resist mask 7 is dissolved and removed by immersing it in this dissolving solution for 30 to 60 seconds. Wash with water and dry.

引き続き導体回路6を粗面化するための粗面化電解メッ
キを実施する(第1図(8))。この粗面化電解メッキ
工程における電解条件は、電流密度が0.25〜0.8
5A/c+a、電極間距離が26〜50m、電極に対す
る電解液の接液スピードが0,6〜1.5s/secと
なるよ)に夫々設定する。尚、電解液としては特に限定
されないが、たとえば、硫酸銅(CuS01・5 th
o) : 80=150g/ l、硫酸(HgSO4)
:40〜80g/l、及び硝酸カリウム(KN(h) 
: 25〜50g/ Itよりなる混合溶液等を使用す
る。
Subsequently, roughening electrolytic plating is performed to roughen the conductor circuit 6 (FIG. 1 (8)). The electrolytic conditions in this roughening electrolytic plating process are such that the current density is 0.25 to 0.8.
5A/c+a, the distance between the electrodes is 26 to 50 m, and the speed at which the electrolyte contacts the electrodes is 0.6 to 1.5 s/sec). The electrolytic solution is not particularly limited, but for example, copper sulfate (CuS01.5 th
o): 80=150g/l, sulfuric acid (HgSO4)
:40-80g/l, and potassium nitrate (KN(h)
: Use a mixed solution etc. consisting of 25-50g/It.

この粗面化処理により導体回路6の粗面上には突起状析
出物が付着形成され、この突起状析出物の平均粒径は1
〜5μmとなり、後述する絶縁基材10との密着性が極
めて良好となる。
Through this surface roughening treatment, protruding precipitates are formed on the rough surface of the conductor circuit 6, and the average particle size of the protruding precipitates is 1.
~5 μm, and the adhesion to the insulating base material 10 described later is extremely good.

尚、上述した粗面化処理後に更に導体回路6表面にクロ
メート処理を施すと、銅と絶縁基材中の樹脂又は接着剤
との親和性を増大し、ピーリング強度はもとより、導体
回路の耐熱性(例えば、はんだ耐熱性)も15%程度向
上するという利点がある。このクロメート処理は、具体
的には、0.7〜12g/ l濃度の重クロム酸カリウ
ム溶液に常温で5〜45秒間浸漬するか、市販の電解ク
ロメート処理液にてクロメート処理を施す。
Furthermore, if the surface of the conductor circuit 6 is further subjected to chromate treatment after the above-mentioned surface roughening treatment, the affinity between the copper and the resin or adhesive in the insulating base material is increased, and not only the peeling strength but also the heat resistance of the conductor circuit is improved. There is an advantage that (for example, soldering heat resistance) is also improved by about 15%. Specifically, this chromate treatment is performed by immersing the product in a potassium dichromate solution having a concentration of 0.7 to 12 g/l for 5 to 45 seconds at room temperature, or by performing chromate treatment using a commercially available electrolytic chromate treatment solution.

次いで、薄膜金属層5を介して導電基材2に形成させた
保護N4及び導体回路6を、これらの薄膜金属N5及び
導電基材2と共に絶縁基材10上に積層すると共に、当
該絶縁基材lOの他側面にはw4箔3を積層し、ホット
プレスによりこれらを一体に加熱圧着させる(第1図(
5)、第7図)。絶縁基材10としては、有機材料、及
び無機材料のいずれのものでもよく、例えば、ガラス、
エポキシ系樹脂、フェノール系樹脂、ポリイミド系樹脂
、ポリエステル系樹脂、アーラミド樹脂等の材料を用い
ることができる。また、鉄、アルミ等の導電性材料の表
面にホーロウを被覆し、又アルミ表面を酸化するアルマ
イト処理を施して絶縁した材料でもよい。一般には、ガ
ラス布等にエポキシ樹脂を含浸させ、半硬化状Ml(B
ステージ)にあるプリプレグに導体回路6が没入する状
態(第6図に示す状態)に加熱・加圧され、これと接着
される。
Next, the protection N4 and conductor circuit 6 formed on the conductive base material 2 via the thin film metal layer 5 are laminated on the insulating base material 10 together with the thin film metal N5 and the conductive base material 2, and the insulating base material A W4 foil 3 is laminated on the other side of the IO, and these are heat-pressed together using a hot press (see Fig. 1).
5), Figure 7). The insulating base material 10 may be either an organic material or an inorganic material, such as glass,
Materials such as epoxy resin, phenol resin, polyimide resin, polyester resin, and aramid resin can be used. Alternatively, a material insulated by coating the surface of a conductive material such as iron or aluminum with enamel and performing an alumite treatment to oxidize the aluminum surface may be used. Generally, glass cloth or the like is impregnated with epoxy resin, and semi-cured Ml(B
The conductor circuit 6 is heated and pressurized so that it is immersed in the prepreg (stage) (the state shown in FIG. 6), and is bonded thereto.

この転写工程において、導体回路6は厚手の導電基材2
と一体にvI!、縁基材10に積層され、加熱圧着され
るので、導体回路6は導電基材2に保持されたまま転写
されることになり、寸法安定性が確保される。又、導電
基材2が転写時の転写治具を兼ねるので特別の治具が不
要であり、更に、導体回路6と導電基材2との間に薄膜
金属N5が介在し、薄膜金属層5と導体回路6とが強い
密着力で結合しているので導体回路6が転写時にずれて
移動する(所謂、スイングを起こす)ことがなく、寸法
安定性が良いので微細な導体回路パターンを有する高密
度回路にも適用可能である(例えば、パターン幅数μm
−数十μmが実現出来る)。更に、万一導体回路6にピ
ンホールがあっても導体回路6と導電基材2との間に薄
膜金属層5及び保護層4が密着状態で介在しているので
接着剤等がピンホールを通って導体回路6表面に露出す
ることがない。
In this transfer process, the conductor circuit 6 is transferred to the thick conductive base material 2.
And all together vI! , is laminated on the edge base material 10 and bonded under heat and pressure, so that the conductive circuit 6 is transferred while being held on the conductive base material 2, and dimensional stability is ensured. Further, since the conductive base material 2 also serves as a transfer jig during transfer, no special jig is required.Furthermore, the thin film metal N5 is interposed between the conductive circuit 6 and the conductive base material 2, and the thin film metal layer 5 Since the conductor circuit 6 and the conductor circuit 6 are bonded with strong adhesion, the conductor circuit 6 does not shift or move during transfer (so-called swinging), and has good dimensional stability. It is also applicable to density circuits (for example, pattern width of several μm
- several tens of micrometers can be achieved). Furthermore, even if there is a pinhole in the conductor circuit 6, since the thin film metal layer 5 and the protective layer 4 are interposed in close contact between the conductor circuit 6 and the conductive base material 2, the adhesive etc. will not cause the pinhole. It does not pass through and be exposed to the surface of the conductor circuit 6.

次に、絶縁基材10の加熱固化を待って導TL基材2を
、絶縁基材10に転写された導体回路6、保護層4及び
薄膜金属115から剥離する(第1図(1)、第8図)
。このとき、導電基材2と薄膜金属層5との間の密着力
より、薄膜金属N5と導体回路6の密着力の方が大であ
り、更に、導電基材2と薄膜金属N5との間の密着力よ
り、導体回路6と絶縁基材10の密着力の方が大である
から、導電基材2は薄膜金属層5との界面8で分離して
wA縁基材10側にはWi膜金金属115保i1層4及
び導体回路6が一体に密着している。
Next, after heating and solidifying the insulating base material 10, the conductive TL base material 2 is peeled off from the conductor circuit 6, protective layer 4, and thin film metal 115 transferred to the insulating base material 10 (FIG. 1 (1), Figure 8)
. At this time, the adhesion force between the thin film metal N5 and the conductor circuit 6 is greater than the adhesion force between the conductive base material 2 and the thin film metal layer 5, and the adhesion force between the conductive base material 2 and the thin film metal layer N5 is greater. Since the adhesion between the conductor circuit 6 and the insulating base material 10 is greater than the adhesion between The film gold metal 115, the insulation layer 4, and the conductor circuit 6 are in close contact with each other.

導電基材2と絶縁基材10間に薄膜金属層5が介在され
るから、絶縁基材10の接着剤は導電基材2に直接付着
することがなく、又、分離が導電基材2と薄膜金i層5
間で生じるから、70〜120g/ CMのピーリング
強度で導を基材2を容易に剥離することが出来、導体回
路6に不均一な力が掛からず、転写時の寸法安定性がこ
の時にも確保される。
Since the thin metal layer 5 is interposed between the conductive base material 2 and the insulating base material 10, the adhesive of the insulating base material 10 does not directly adhere to the conductive base material 2, and separation occurs between the conductive base material 2 and the conductive base material 2. Thin film gold i-layer 5
Since the conductor is generated between 70 and 120 g/CM, the conductive base material 2 can be easily peeled off with a peeling strength of 70 to 120 g/CM, no uneven force is applied to the conductive circuit 6, and dimensional stability during transfer is maintained even at this time. Secured.

次いで、絶縁基材10の両面に積層された導体回路6及
び銅箔3の間を接続するためのスルーホール101を形
成する(第1図(j)、第9図)、このスルーホール形
成工程には、通常の方法例えばドリル等を使用した切削
加工を適用することができる。しかるのち、スルーホー
ル101の内壁面101a、導体回路6及び銅箔3の全
面に例えば銅のスルーホールメッキを施すことにより銅
層102を形成する(第1図(ト)、第10図)、この
工程は、具体的には、電解銅メッキ又は無電解銅メッキ
とを組み合わせて実施することができる。
Next, a through hole 101 is formed for connecting between the conductor circuit 6 and the copper foil 3 laminated on both sides of the insulating base material 10 (FIG. 1 (j), FIG. 9). This through hole forming step For example, a conventional method such as cutting using a drill or the like can be applied. Thereafter, a copper layer 102 is formed by, for example, through-hole plating copper on the inner wall surface 101a of the through-hole 101, the conductor circuit 6, and the entire surface of the copper foil 3 (FIGS. 1(G) and 10). Specifically, this step can be performed in combination with electrolytic copper plating or electroless copper plating.

次に、lEl、Ft 102上の上記スルーホール10
1の内壁面101a、スルーホール101開口周縁部及
び積層体下面の回路形成領域を除く領域にレジストマス
ク103を形成する(第1図(+)、第11図)。この
工程は上記第1図(C)の工程で述べたのと同様にして
実行することができる。
Next, the above through hole 10 on lEl, Ft 102
A resist mask 103 is formed on the inner wall surface 101a of 1, the peripheral edge of the opening of the through hole 101, and the lower surface of the laminate except for the circuit forming area (FIG. 1(+), FIG. 11). This step can be performed in the same manner as described in the step of FIG. 1(C) above.

しかるのち、上記レジストマスク103が形成されてい
ない領域に半田メッキを施し、半田メッキ層104を形
成したのち(第1図(ホ))、レジストマスク103を
剥離除去する(第1図(n)、第12図)。
After that, solder plating is applied to the area where the resist mask 103 is not formed to form a solder plating layer 104 (FIG. 1(e)), and then the resist mask 103 is peeled off (FIG. 1(n)). , Figure 12).

最後に、半田メッキ層104をエツチングレジストとし
て積層体両面のエツチングを行い、記録電極板を完成す
る(第1図(0)、第13図)、このエツチング工程は
、半田メッキ1104を腐食させることなく銅層102
、I脱金属1115及び銅箔3をエツチングしうるエツ
チング液、例えば、クロム酸と硫酸との混合水溶液を使
用した湿式エンチングにより実行することが可能である
。この工程において、積層体上面では、薄膜金属N5上
に当該薄膜金属層とはエツチング条件を異にする金又は
金/ニッケルメッキ層よりなる保護層4が形成されてい
るため、エツチングはこの保護層4で停止する。従って
、オーバーエツチングによるパターンの断線等が発生せ
ず、導体回路の線密度を高めることが可能となる。
Finally, both sides of the laminate are etched using the solder plating layer 104 as an etching resist to complete the recording electrode plate (FIG. 1(0), FIG. 13).This etching process does not corrode the solder plating 1104. copper layer 102
, I Demetallization 1115 and copper foil 3 can be etched by wet etching using an etching solution capable of etching, for example, a mixed aqueous solution of chromic acid and sulfuric acid. In this step, on the top surface of the laminate, a protective layer 4 made of gold or a gold/nickel plating layer whose etching conditions are different from that of the thin metal layer is formed on the thin metal N5, so the etching is performed on this protective layer. Stop at 4. Therefore, pattern breakage due to overetching does not occur, and the line density of the conductive circuit can be increased.

第14図乃至第17図は第1図Q:1)及び(e)に示
す工程において、ホリゾンタル型の高速メッキを実施す
るメッキ装置の一例を示し、メッキ装置11のフレーム
12の上部中央に水平に板状不溶性陽極14が設置され
、陰極1はこの陽極14に平行に対向させて固定される
。不溶性陽極14は第14図〜第16図に示すように大
電流を通電するために2枚の銅板14a、14bが重合
され、これらの表面全体に鉛14cが、肉厚2〜10m
m、好ましくは3〜7ma+の範囲内で一様にアセチレ
ントーチ等で被覆して構成される。鉛被覆14cは、通
常、鉛93%、スズ7%の鉛合金を使用する。極間距離
が100μm不均一になると、電鋳される銅膜は、35
μm銅で数μmのばらつきが生じ、高電流密度(0,8
〜1.2A/CTI)で長時間(1000時間以上)使
用する場合には、電極の部分的な電解消耗により膜厚の
ばらつきは更に大きくなる。このため、電極の再加工修
正により電極間距離を維持する必要がある。鉛被覆の電
極に代えて、チタン板にプラチナ、パラジュウム等の微
粉末を熱解重合性樹脂でペースト状にし、これを粗面化
されたチタン板表面に均一に塗布し700〜800℃で
焼き付けて不溶性陽極14としてもよい、このチタン板
陽極を使用すると、電解消耗が極めて少なくなくなり、
長時間に亘り(1000時間以上)電極の再加工修正の
必要がない。
14 to 17 show an example of a plating device that performs horizontal high-speed plating in the steps shown in FIG. 1 Q: 1) and (e). A plate-shaped insoluble anode 14 is installed, and the cathode 1 is fixed so as to face this anode 14 in parallel. As shown in FIGS. 14 to 16, the insoluble anode 14 is made up of two copper plates 14a and 14b that are polymerized in order to pass a large current, and lead 14c is coated over the entire surface of these plates with a thickness of 2 to 10 m.
m, preferably within the range of 3 to 7 ma+, and is uniformly coated with an acetylene torch or the like. The lead coating 14c typically uses a lead alloy containing 93% lead and 7% tin. When the distance between the electrodes becomes uneven by 100 μm, the electroformed copper film becomes 35
Variations of several μm occur in μm copper, and high current density (0,8
When used for a long time (more than 1000 hours) at a temperature of 1.2 A/CTI), the variation in film thickness becomes even larger due to partial electrolytic consumption of the electrode. Therefore, it is necessary to maintain the distance between the electrodes by reworking and correcting the electrodes. Instead of lead-coated electrodes, fine powders of platinum, palladium, etc. are made into a paste on a titanium plate using a thermally depolymerizable resin, and this is evenly applied to the roughened surface of the titanium plate and baked at 700 to 800℃. By using this titanium plate anode, which can be used as an insoluble anode 14, electrolytic consumption is extremely low.
There is no need to rework or correct the electrode for a long time (more than 1000 hours).

陰極1は、第1図(b)の薄膜金属層形成工程では、工
程(a)で研磨された導電基材2の研磨面が、第1図(
e)の導体回路電鋳工程では、薄膜金属層5及びレジス
トマスク7の形成された導電基材2の面を前記陽極14
側に対向させて取付は固定される。
In the thin film metal layer forming step of FIG. 1(b), the polished surface of the conductive base material 2 polished in step (a) of the cathode 1 is as shown in FIG.
In the conductor circuit electroforming step e), the surface of the conductive base material 2 on which the thin film metal layer 5 and the resist mask 7 are formed is placed on the anode 14.
The mounting is fixed with opposite sides.

陰極1と不溶性陽極14間の離間距離は前述した薄膜金
属N5の形成工程及び導体回路6の電鋳工程の夫々に応
じた最適距離に設定される。
The distance between the cathode 1 and the insoluble anode 14 is set to the optimum distance depending on the process of forming the thin film metal N5 and the electroforming process of the conductive circuit 6, respectively.

陰極1及び不溶性陽極14間の空隙部13の入口側には
高速流でメッキ液23を圧送するノズル15の一端が接
続され、このノズル15は空隙部13の入口部で第17
回に示すように不溶性陽極14の略全幅に臨んで開口し
ており、ノズル15の他端は導管16を介してポンプ1
7に接続されている。ポンプ】7は更に図示しない導管
を介してメッキ液貯槽(図示せず)に接続されている。
One end of a nozzle 15 for pumping the plating solution 23 at high speed is connected to the inlet side of the gap 13 between the cathode 1 and the insoluble anode 14.
As shown in Figure 3, the nozzle 15 is opened to face substantially the entire width of the insoluble anode 14, and the other end of the nozzle 15 is connected to the pump 1 through a conduit 16.
7 is connected. The pump 7 is further connected to a plating solution storage tank (not shown) via a conduit (not shown).

空隙部13の出口側(ノズル15を設けた不溶性陽極1
4の対向辺側)には不溶性陽極14の略全幅にわたって
排液口18が開口しており、この排液口18は導管19
を介して前記メッキ液貯槽に接続されている。そして、
前記ノズル15及び排液口18はメッキ液23が空隙部
13を一様の速度分布で流れることが出来るように、こ
れらのノズル15及び排液口18の流れ方向の断面形状
変化は滑らかに変化している。ポンプ17から吐出され
たメッキ液23は、導管16、ノズル15、陰極1と不
溶性陽極14との空隙部13、排液口18、導管19を
順次通過してメッキ液貯槽に戻され、ここから再びポン
プ17により上述の経路で連続して循環される。
The outlet side of the cavity 13 (the insoluble anode 1 provided with the nozzle 15)
4), a drain port 18 is opened over substantially the entire width of the insoluble anode 14, and this drain port 18 is connected to a conduit 19.
It is connected to the plating solution storage tank via. and,
The cross-sectional shape of the nozzle 15 and the drain port 18 in the flow direction changes smoothly so that the plating solution 23 can flow through the gap 13 with a uniform velocity distribution. are doing. The plating solution 23 discharged from the pump 17 sequentially passes through the conduit 16, the nozzle 15, the gap 13 between the cathode 1 and the insoluble anode 14, the drain port 18, and the conduit 19, and is returned to the plating solution storage tank. It is again continuously circulated by the pump 17 along the above-mentioned path.

メッキ液23をノズル15から電極間空隙部13へ前述
した好適のメッキ液速度で供給すると、陰極1表面近傍
でメッキ液流れは乱流状態になっており、電極表面近傍
の金属イオン濃度が極度に低下しないように、即ち分極
層の生長を抑えて、高速度でメッキ膜を成長させること
が可能となる。
When the plating solution 23 is supplied from the nozzle 15 to the interelectrode gap 13 at the above-described suitable plating solution speed, the plating solution flow becomes turbulent near the surface of the cathode 1, and the metal ion concentration near the electrode surface becomes extremely high. It becomes possible to grow the plated film at high speed while preventing the growth of the polarized layer from decreasing.

本発明におけるメッキ工程では、陰極1と不溶性陽極1
4との間に、銅、黒鉛、鉛等の耐薬品性、高導電性を有
する給電板20、陽極電源ケーブル21、陰極電源ケー
ブル22を介して、前述した所要の高電流が給電される
ようになっており、不溶性陽極14に対向する陰極1表
面及びその非導電性レジストマスク7でマスキングしな
い部分に、毎分25〜100μm程度の堆積速度で銅膜
を電解析出することができる。
In the plating process in the present invention, a cathode 1 and an insoluble anode 1
4, the required high current as described above is supplied via a power supply plate 20 made of copper, graphite, lead, etc., which has chemical resistance and high conductivity, an anode power cable 21, and a cathode power cable 22. Therefore, a copper film can be electrolytically deposited on the surface of the cathode 1 facing the insoluble anode 14 and the portion thereof not masked by the non-conductive resist mask 7 at a deposition rate of about 25 to 100 μm per minute.

なお、本発明の製造方法において、使用する高速メッキ
装置としては、上述したホリゾンタル型のものに限定さ
れるものではなく、例えば、バーチカル型、回転型等を
適宜使用することができる。
In addition, in the manufacturing method of the present invention, the high-speed plating apparatus used is not limited to the above-mentioned horizontal type, and for example, a vertical type, a rotary type, etc. can be used as appropriate.

(実施例) 次に、本発明の詳細な説明する。(Example) Next, the present invention will be explained in detail.

(以下余白) 第1表は、本発明方法及び比較方法により作製された記
録電極板の評価試験結果を示し、導電基材2の表面粗度
、薄膜金属層5の電解条件、導体回路6の電解条件、導
体回路6の粗面化処理条件を種々に変え、転写性、導体
回路6と絶縁基材10間のピーリング強度、導体回路6
の伸び率等の評価試験を行ったものであり、第1表に示
す試験条件以外の条件は、総ての供試回路板で同じであ
り、それらは以下の通りである。尚、レジストマスクは
導体回路の粗面化処理に先立って溶解除去した。
(Leaving space below) Table 1 shows the evaluation test results of the recording electrode plates produced by the method of the present invention and the comparative method, including the surface roughness of the conductive substrate 2, the electrolytic conditions of the thin metal layer 5, and the conditions of the conductor circuit 6. The electrolytic conditions and the roughening treatment conditions of the conductor circuit 6 were varied to improve transferability, peeling strength between the conductor circuit 6 and the insulating base material 10, and the conductor circuit 6.
The test conditions other than those shown in Table 1 were the same for all test circuit boards, and they are as follows. Note that the resist mask was dissolved and removed prior to the surface roughening treatment of the conductor circuit.

専里基せ: 材質:ハードニング処理を施したステンレススチール単
板(sus630)、 表面処理:オシレーシゴン付ロータリ別布研磨装置を使
用して第1表に示す粗度に 研磨、 1■魚員1: 材t:銅薄膜(l電基材表面に3μmの膜厚で堆積) 電解条件:電極間路gllfmm、硫#18(Ig/ 
1の硫酸銅メッキ液使用 童j−ヨLl:厚さ1〜2μm ■体皿農1墾: 電解条件:電極間距離11mm、硫酸180g/ ff
iの硫酸銅メッキ液使用、堆積膜厚35 μm(但し、比較例3は9μm)、 ■里■処互ニッシュラメッキ、 電解条件:硫r11m100g/l!、硫11150 
g / A、硝酸カリウム30 g / Nよりなる混
合溶液使用、堆積膜厚3μm。
Special base: Material: Stainless steel veneer with hardening treatment (SUS630), Surface treatment: Polished to the roughness shown in Table 1 using a rotary cloth polishing device with an oscillation gun, 1 ■ Fish member 1 : Material t: Copper thin film (deposited on the surface of the electric base material with a film thickness of 3 μm) Electrolytic conditions: electrode gap gllfmm, sulfur #18 (Ig/
1 using copper sulfate plating solution: Thickness 1 to 2 μm ■ Body plate 1: Electrolysis conditions: electrode distance 11 mm, sulfuric acid 180 g/ff
Use of copper sulfate plating solution of i, deposited film thickness 35 μm (however, 9 μm in Comparative Example 3), Nisura plating with *ri* process, electrolytic conditions: sulfur r11m 100g/l! , sulfur 11150
g/A, a mixed solution consisting of potassium nitrate 30 g/N was used, and the deposited film thickness was 3 μm.

■橡益社: 材fニガラスエポキシC−10 ’;1)Lt−#−)b /  : を気)” IJ 
/L/、孔径0.8mmスルーホールメッキ :厚さ2
5μmの銅無電解メッキ 手1し」什Ll:厚さ7μm 第1表において、本発明方法を適用した実施例1〜3は
いずれも、導電基材(単板)2の表面粗度、薄膜金属層
5の電解条件、導体回路6の電解条件、及び導体回路6
の粗面化処理条件がいずれも本発明の規定する条件範囲
内にあり、転写性、導体回路6と絶縁基材10間のピー
リング強度、導体回路6の伸び率がいずれも良好であり
、総合評価も良(0)である。
■IJ: Material f Niglass epoxy C-10';
/L/, hole diameter 0.8mm through-hole plating: thickness 2
In Table 1, in Examples 1 to 3 to which the method of the present invention was applied, the surface roughness of the conductive substrate (veneer) 2, the thin film Electrolytic conditions for metal layer 5, electrolytic conditions for conductor circuit 6, and conductor circuit 6
The surface roughening treatment conditions are all within the condition range prescribed by the present invention, and the transferability, peeling strength between the conductor circuit 6 and the insulating base material 10, and elongation rate of the conductor circuit 6 are all good, and the overall The evaluation is also good (0).

一方、導電基材(単板)2の表面粗度が本発明方法の規
定する下限値を外れる比較例1では、薄膜金属層がその
形成工程中において導電基材(単板)2より剥離(早い
剥がれ)が生じ、上限値を外れる比較例2では、転写工
程時に導電基材(単板)2と薄膜金属層5との密着強度
が大きく(ピーリング値310g/cm)、部分的に薄
膜金属層5が導電基材2側に残留し、回路ずれが生じる
。又、導電基材2の表面粗度が大きいと薄膜金属層2に
多数のピンホールが発生し、絶縁基材10の積層時に薄
膜金属層のレジストマスク除去部に出来たピンホール内
に入り込んだ絶縁基材の接着剤が導電基材2の表面に付
着するため、絶縁基材10と導電基材2とが強く密着し
てしまい、転写性が阻害される。尚、100μm以下の
径のピンホールが1dn(当たりに1個以上存在すると
き、多数のピンホールが発生していると判定した。
On the other hand, in Comparative Example 1 in which the surface roughness of the conductive substrate (veneer) 2 is outside the lower limit defined by the method of the present invention, the thin metal layer peels off from the conductive substrate (veneer) 2 during the formation process. In Comparative Example 2, which exceeds the upper limit due to early peeling, the adhesion strength between the conductive base material (single plate) 2 and the thin film metal layer 5 is high (peeling value 310 g/cm), and the thin film metal layer 5 partially peels off during the transfer process. Layer 5 remains on the conductive base material 2 side, causing circuit misalignment. Moreover, if the surface roughness of the conductive base material 2 is large, many pinholes are generated in the thin film metal layer 2, and when the insulating base material 10 is laminated, the pinholes get into the pinholes formed in the resist mask removed part of the thin film metal layer. Since the adhesive of the insulating base material adheres to the surface of the conductive base material 2, the insulating base material 10 and the conductive base material 2 come into close contact with each other, and transferability is inhibited. In addition, when there were one or more pinholes with a diameter of 100 μm or less per dn, it was determined that a large number of pinholes were generated.

導電基材2表面に薄膜金属層5を形成させずに導電基材
2に直接レジストマスク7及び導体回路6を形成させる
と、導体回路(膜厚9μm)6にピンホールが発生する
と共に、レジストマスク7と導体回路6とを一体に転写
する場合は、レジストマスク7と導電基材2との密着強
度が大きいため、転写時にレジストマスク7が導電基材
2表面に残留してしまい、又、レジストマスク7を除去
後に導体回路6を転写する場合は、絶縁基材10と導電
基材2とが接着剤により密着してしまい、導電基材2の
剥離が困難になり、何れにしても転写性が著しく阻害さ
れる(比較例3)。
If the resist mask 7 and conductor circuit 6 are formed directly on the conductive base material 2 without forming the thin metal layer 5 on the surface of the conductive base material 2, pinholes will occur in the conductor circuit (film thickness 9 μm) 6 and the resist When the mask 7 and the conductor circuit 6 are integrally transferred, the adhesion strength between the resist mask 7 and the conductive base material 2 is large, so the resist mask 7 remains on the surface of the conductive base material 2 during transfer, and When transferring the conductor circuit 6 after removing the resist mask 7, the insulating base material 10 and the conductive base material 2 will stick together with the adhesive, making it difficult to peel off the conductive base material 2, and in any case, the transfer will not be possible. (Comparative Example 3).

導体回路6の電解時に電解液の接液スピードが本発明方
法の規定する上限値を超えると電解中にレジストマスク
7が剥離しく比較例4)、電流密度が本発明方法の規定
する上限値を超えると、ノジュラ状メッキ、所謂「メッ
キ焼け」が発生し、形成された導体回路6の伸び率も8
%と低く、フレキシブル基板用回路に使用することが出
来ない(比較例5)。
If the contact speed of the electrolyte during electrolysis of the conductor circuit 6 exceeds the upper limit specified by the method of the present invention, the resist mask 7 will peel off during electrolysis (Comparative Example 4), and the current density exceeds the upper limit specified by the method of the present invention. If it exceeds 8, nodular plating, so-called "plating burn" will occur, and the elongation rate of the formed conductor circuit 6 will also be 8.
%, and cannot be used for flexible substrate circuits (Comparative Example 5).

導体回路6表面の粗面化処理における電解メッキ時の電
流密度が本発明方法の規定する下限値を下回ると光沢の
あるメッキ表面となり、粗面化メッキが形成されない(
比較例6)、粗面化が不充分な導体回路6を絶縁基材1
0に転写すると、導体回路6と絶縁基材10間のビーリ
ング値は0.7kg/amとなり、密着強度が不足する
If the current density during electrolytic plating in the roughening treatment of the surface of the conductor circuit 6 is below the lower limit specified by the method of the present invention, the plated surface will be shiny and no roughened plating will be formed (
Comparative Example 6), the conductor circuit 6 with insufficient surface roughening was replaced with the insulating base material 1.
0, the beering value between the conductor circuit 6 and the insulating base material 10 is 0.7 kg/am, resulting in insufficient adhesion strength.

導電基材2の表面粗度、薄膜金属層5の電解条件、導体
回路6の電解条件、及び導体回路6の粗面体処理条件の
いずれかが本発明の規定する条件範囲をはずれる比較例
1〜6は上述の通りの不都合を有し、総合評価はいずれ
も不可(×)である。
Comparative Examples 1 to 1 in which any of the surface roughness of the conductive base material 2, the electrolytic conditions of the thin film metal layer 5, the electrolytic conditions of the conductive circuit 6, and the roughened surface treatment conditions of the conductive circuit 6 are out of the condition range prescribed by the present invention. No. 6 has the above-mentioned disadvantages, and the overall evaluation is poor (x).

(発明の効果) 以上詳述したように、本発明の記録電極板の製造方法に
よれば、表面粗度0.08〜0.23μmの平板状導電
基材を陰極として、該陰極と平板状陽極を電極間距離3
〜30mmだけ離間させ、これらの電極に対する電解液
の接液スピードが2.6〜20.0mノsecとなるよ
うに電解液を強制的に供給し、電流密度0.15〜4.
0A/cボの条件で電解メッキを施して前記導電基材に
厚さ1〜5μmの薄膜金属層を形成する工程と、形成し
た薄膜金属層の、導体回路を形成する部分を除く表面に
レジストマスクを形成する工程と、レジストマスクを形
成した薄膜金属層表面に、金メッキもしくは金メッキ後
にニッケルメッキを施してメッキ層を形成する工程と、
このメッキ層上に銅イオンを含有する電解液を用いて前
記電解メッキ条件と同じ条件で電解メッキを施して導体
回路を形成したのち前記レジストマスクを剥離する工程
と、形成した導体回路表面に粗面化処理を施す工程と、
斯く形成させた導体回路表面に絶縁基材を介してw4箔
を積層して一体に加熱圧着し積層体を形成する工程と、
この積層体から前記導電基材のみを剥離する工程と、こ
の積層体にスルーホールを形成したのちスルーホールの
内壁面及び前記積層体の両面に銅メッキを施す工程と、
この積層体両面の所望の回路領域を除く領域にレジスト
マスクを形成する工程と、積層体両面に半田メッキを施
したのち前記レジストマスクを剥離する工程と、この半
田メッキ層をマスクとして前記積層体両面のエツチング
を行う工程とから構成したので、薄膜金属層及び導体回
路のメッキ形成時間が従来のメッキ方法に比較して著し
く短縮され、生産性が高く、工程も簡略化されるので本
発明方法を実施する導体回路板の製造装置に必要な設備
及びその設置面積が少なくて済む。
(Effects of the Invention) As described in detail above, according to the method for manufacturing a recording electrode plate of the present invention, a flat conductive substrate having a surface roughness of 0.08 to 0.23 μm is used as a cathode, The distance between the anode and the electrode is 3
The electrodes were separated by ~30 mm, and the electrolyte was forcibly supplied so that the contact speed of the electrolyte to these electrodes was 2.6 to 20.0 msec, and the current density was 0.15 to 4.0 msec.
A step of forming a thin metal layer with a thickness of 1 to 5 μm on the conductive base material by electrolytic plating under the conditions of 0A/c, and applying a resist on the surface of the formed thin metal layer except for the part where the conductor circuit is to be formed. a step of forming a mask; a step of forming a plating layer by plating gold or nickel plating after gold plating on the surface of the thin film metal layer on which the resist mask is formed;
Electrolytic plating is performed on this plating layer using an electrolytic solution containing copper ions under the same electrolytic plating conditions as described above to form a conductor circuit, and then the resist mask is peeled off, and the surface of the formed conductor circuit is roughened. A step of applying surface treatment,
A step of laminating W4 foil on the surface of the conductor circuit thus formed via an insulating base material and heat-pressing them together to form a laminate;
a step of peeling only the conductive base material from this laminate; a step of forming a through hole in this laminate and then applying copper plating to the inner wall surface of the through hole and both sides of the laminate;
A step of forming a resist mask on both sides of the laminate except for the desired circuit area, a step of peeling off the resist mask after applying solder plating to both sides of the laminate, and a step of peeling off the resist mask using the solder plating layer as a mask. Since it consists of a step of etching both sides, the time required for plating thin film metal layers and conductor circuits is significantly shortened compared to conventional plating methods, productivity is high, and the process is simplified. The equipment required for a conductor circuit board manufacturing apparatus for carrying out the process and its installation area can be reduced.

又、導体回路と導電基材間に薄膜金属層を介在させるの
で、メッキ形成される導体回路にピンホール等の欠陥が
生じ難く、しかも、転写時の転写が容易で寸法安定性に
優れているという利点がある。
In addition, since a thin metal layer is interposed between the conductor circuit and the conductive base material, defects such as pinholes are less likely to occur in the conductor circuit formed by plating, and it is also easy to transfer and has excellent dimensional stability. There is an advantage.

更に、導体回路を金又は金/ニッケルメッキよりなる保
護層により保護したので、オーバーエツチング等による
断線の発生が防止され、微細な回路パターンも安定して
製造出来るので歩留まりが向上して品質も向上するとい
う種々の優れた効果を奏する。
Furthermore, since the conductor circuit is protected by a protective layer made of gold or gold/nickel plating, disconnections due to overetching are prevented, and even fine circuit patterns can be stably manufactured, improving yield and quality. It has various excellent effects.

更に、本発明の製造方法によれば、高速電解メッキを使
用することにより、抗張力が高く、しかもアニール銅と
同等以上の延び率を示す導体回路を形成することができ
るという利点もある。
Further, according to the manufacturing method of the present invention, by using high-speed electrolytic plating, there is an advantage that a conductor circuit having high tensile strength and an elongation rate equal to or higher than that of annealed copper can be formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明に係る記録電極板の製造方法の製造手
順を示す工程フーロチャート、第2図乃至第13図は、
第1図に示す工程における導体回路板の断面構成図、第
14図はホリゾンタル型の高速メッキ装置の構成を示す
正面断面図、第15図は同高速メッキ装置の側面図、第
16図は、第15図に示すXVI−XVI矢線に沿う断
面図、第17図は、第16図に示すX■−X■矢線に沿
う断面図。 1・・・陰極、2・・・導電基材、4・・・保護層(金
又は金/ニッケルメッキ闇)、5・・・薄膜金属層、6
・・・導体回路、7・・・レジストマスク、10.10
a・・・絶縁基板、11・・・ホリゾンタル型高速メッ
キ装置、14・・・不溶性陽極、101・・・スルーホ
ール。
FIG. 1 is a process flowchart showing the manufacturing procedure of the recording electrode plate manufacturing method according to the present invention, and FIGS. 2 to 13 are
A cross-sectional configuration diagram of a conductor circuit board in the process shown in FIG. 1, FIG. 14 is a front sectional view showing the configuration of a horizontal type high-speed plating device, FIG. 15 is a side view of the same high-speed plating device, and FIG. 16 is a 15 is a sectional view taken along the XVI-XVI arrow line shown in FIG. 15, and FIG. 17 is a sectional view taken along the X■-X■ arrow line shown in FIG. 16. DESCRIPTION OF SYMBOLS 1... Cathode, 2... Conductive base material, 4... Protective layer (gold or gold/nickel plating dark), 5... Thin film metal layer, 6
...Conductor circuit, 7...Resist mask, 10.10
a... Insulating substrate, 11... Horizontal type high speed plating device, 14... Insoluble anode, 101... Through hole.

Claims (4)

【特許請求の範囲】[Claims] (1)表面粗度0.08〜0.23μmの平板状導電基
材を陰極として、該陰極と平板状陽極を電極間距離3〜
30mmだけ離間させ、これらの電極に対する電解液の
接液スピードが2.6〜20.0m/secとなるよう
に電解液を強制的に供給し、電流密度0.15〜4.0
A/cm^2の条件で電解メッキを施して前記導電基材
に厚さ1〜5μmの薄膜金属層を形成する工程と、形成
した薄膜金属層の、導体回路を形成する部分を除く表面
にレジストマスクを形成する工程と、レジストマスクを
形成した薄膜金属層表面に、金メッキもしくは金メッキ
後にニッケルメッキを施してメッキ層を形成する工程と
、このメッキ層上に銅イオンを含有する電解液を用いて
前記電解メッキ条件と同じ条件で電解メッキを施して導
体回路を形成したのち前記レジストマスクを剥離する工
程と、形成した導体回路表面に粗面化処理を施す工程と
、斯く形成させた導体回路表面に絶縁基材を介して銅箔
を積層して一体に加熱圧着し積層体を形成する工程と、
この積層体から前記導電基材のみを剥離する工程と、こ
の積層体にスルーホールを形成したのちスルーホールの
内壁面及び前記積層体の両面に銅メッキを施す工程と、
この積層体両面の所望の回路領域を除く領域にレジスト
マスクを形成する工程と、積層体両面に半田メッキを施
したのち前記レジストマスクを剥離する工程と、この半
田メッキ層をマスクとして前記積層体両面のエッチング
を行う工程とからなることを特徴とする記録電極板の製
造方法。
(1) A flat conductive base material with a surface roughness of 0.08 to 0.23 μm is used as a cathode, and the cathode and flat anode are separated from each other at a distance of 3 to 3.
The electrodes were separated by 30 mm, and the electrolyte was forcibly supplied so that the contact speed of the electrolyte to these electrodes was 2.6 to 20.0 m/sec, and the current density was 0.15 to 4.0 m/sec.
A step of electroplating under the conditions of A/cm^2 to form a thin metal layer with a thickness of 1 to 5 μm on the conductive base material, and a step of forming a thin metal layer on the surface of the formed thin metal layer except for the part where the conductor circuit is to be formed. A step of forming a resist mask, a step of forming a plating layer by plating gold or nickel plating after gold plating on the surface of the thin metal layer on which the resist mask is formed, and using an electrolytic solution containing copper ions on this plating layer. a step of performing electrolytic plating under the same conditions as the electrolytic plating conditions to form a conductor circuit, and then peeling off the resist mask; a step of roughening the surface of the formed conductor circuit; A step of laminating copper foil on the surface via an insulating base material and heat-pressing them together to form a laminate;
a step of peeling only the conductive base material from this laminate; a step of forming a through hole in this laminate and then applying copper plating to the inner wall surface of the through hole and both sides of the laminate;
A step of forming a resist mask on both sides of the laminate except for the desired circuit area, a step of peeling off the resist mask after applying solder plating to both sides of the laminate, and a step of peeling off the resist mask using the solder plating layer as a mask. A method for manufacturing a recording electrode plate, comprising the step of etching both sides.
(2)前記導体回路表面に、銅イオンと硝酸イオンとを
含有する酸性電解液を用い、電流密度0.25〜0.8
5A/cm^2)前記電極に対する前記酸性電解液の接
液スピード0.6〜1.5m/sec、電極間距離26
〜50mmの条件で、堆積膜厚が2〜5μmになるまで
粗面化処理を施すことを特徴とする特許請求の範囲第1
項記載の導体回路板の製造方法。
(2) Using an acidic electrolyte containing copper ions and nitrate ions on the surface of the conductor circuit, the current density is 0.25 to 0.8.
5A/cm^2) Contact speed of the acidic electrolyte with respect to the electrode: 0.6 to 1.5 m/sec, inter-electrode distance: 26
Claim 1, characterized in that the surface roughening treatment is performed under conditions of ~50 mm until the deposited film thickness becomes 2 to 5 μm.
A method for manufacturing a conductive circuit board as described in Section 1.
(3)前記粗面化処理を施した後、更に前記導体回路表
面にクロメート処理を施すことを特徴とする特許請求の
範囲第2項記載の導体回路板の製造方法。
(3) The method for manufacturing a conductive circuit board according to claim 2, further comprising performing a chromate treatment on the surface of the conductive circuit after the surface roughening treatment.
(4)前記陰極及び陽極を共に固定して、これらの電極
間に前記電解液を強制的に供給することを特徴とする特
許請求の範囲第1項乃至第3項のいずれか記載の導体回
路板の製造方法。
(4) The conductor circuit according to any one of claims 1 to 3, characterized in that the cathode and anode are fixed together and the electrolyte is forcibly supplied between these electrodes. Method of manufacturing the board.
JP13186687A 1987-05-29 1987-05-29 Manufacture of recording electrode plate Pending JPS63296963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13186687A JPS63296963A (en) 1987-05-29 1987-05-29 Manufacture of recording electrode plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13186687A JPS63296963A (en) 1987-05-29 1987-05-29 Manufacture of recording electrode plate

Publications (1)

Publication Number Publication Date
JPS63296963A true JPS63296963A (en) 1988-12-05

Family

ID=15067960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13186687A Pending JPS63296963A (en) 1987-05-29 1987-05-29 Manufacture of recording electrode plate

Country Status (1)

Country Link
JP (1) JPS63296963A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11665828B2 (en) * 2018-11-29 2023-05-30 Samwon Act Co., Ltd. Method for manufacturing FCCL capable of controlling flexibility and stiffness of conductive pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11665828B2 (en) * 2018-11-29 2023-05-30 Samwon Act Co., Ltd. Method for manufacturing FCCL capable of controlling flexibility and stiffness of conductive pattern

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