JPS6329532A - Film carrier package - Google Patents

Film carrier package

Info

Publication number
JPS6329532A
JPS6329532A JP61171570A JP17157086A JPS6329532A JP S6329532 A JPS6329532 A JP S6329532A JP 61171570 A JP61171570 A JP 61171570A JP 17157086 A JP17157086 A JP 17157086A JP S6329532 A JPS6329532 A JP S6329532A
Authority
JP
Japan
Prior art keywords
chip
resin
film carrier
potting
carrier package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61171570A
Other languages
Japanese (ja)
Inventor
Tasuku Unno
海野　翼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61171570A priority Critical patent/JPS6329532A/en
Publication of JPS6329532A publication Critical patent/JPS6329532A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the drooping of resin and turning of the resin into a bottom surface, to perform excellent application on one surface and to improve bonding work, by providing step parts on the side surfaces of a semiconductor element, and providing a horizontal surface, which is approximately perpendicular to the side surface. CONSTITUTION:A chip 1 is attached to the lower surface of a chip potting finger lead 10 through bumps 11. The chip 1 is formed as a chip having step parts. Resin solution is potted in a device hole. After thermosetting a potting liquid 13 remains on a horizontal surface of the side surface of the chip 1. Therefore, the resin does not creep to the bottom surface and does not droop to the lower part of the bottom surface of the chip 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はフィルムキャリアパッケージに関し、特に、−
・わゆろ片面レジン筐りのフィルムキャリアパッケージ
におけろレジンポツティングの際のレジンのたれなどを
防止し当該パッケージを薄膜化できる技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a film carrier package, and in particular -
・Relates to technology that can prevent resin dripping during resin potting in film carrier packages with single-sided resin casings and make the packages thinner.

〔従来の技術〕[Conventional technology]

半導体素子の実装方式の一つにテープキャリア方式があ
る。この方式は別称フィルムキャリア方式とかＴ　Ａ　
Ｂ　（Ｔａｐｅ　Ａｕｔｏｍａｔｅｄ　Ｂｏｎｄｉｎｇ
　）方式とか呼ばれており、一般に、長尺のスプロケッ
トホール付きフィルムテープに半導体素子を連続的に組
込んでいく方式で、当該ホールを利用してフィルム（テ
ープ）を送り、位置合せを行なう。One of the mounting methods for semiconductor elements is the tape carrier method. This method is also known as the film carrier method.
B (Tape Automated Bonding
) method, and is generally a method in which semiconductor elements are successively assembled into a long film tape with sprocket holes, and the film (tape) is fed and aligned using the holes.

この方式の一例は、適宜幅のテープに前記スプロケット
ホールと半導体素子の組込み用デバイスホールとを穿設
し、銅箔をラミネートし、ホトレジスト技術やエツチン
グ技術を用いて、所望のリードパターンを形成する。Ｃ
の方式では、前記デバイスホール内にフィンガ状のリー
ドを突出させるのが一つの特徴となっている。An example of this method is to drill the sprocket hole and a device hole for incorporating a semiconductor element in a tape of an appropriate width, laminate copper foil, and form a desired lead pattern using photoresist technology or etching technology. . C
One of the features of this method is that finger-shaped leads protrude into the device hole.

そして、このリードに半導体素子をフェイスアップで位
置合せしてボンディングする。Then, the semiconductor element is aligned face-up to the leads and bonded.

次いで、当該ボンディング後に、半導体素子や当該ポン
ディング部の封止のために、樹脂溶液をポッティングし
、熱硬化させ樹脂を塗布する。この塗布の方法として、
従来、半導体素子の表裏面に樹脂を塗布するいわゆる両
面レジン塗布方式があったが、これでは厚さが厚くなり
過ぎ、ＩＣカードなどの薄物に組込みＢ’ｌいという難
点がある。Next, after the bonding, a resin solution is potted and thermally cured to seal the semiconductor element and the bonding portion. As a method of applying this,
Conventionally, there has been a so-called double-sided resin coating method in which resin is applied to the front and back surfaces of a semiconductor element, but this method has the disadvantage that the thickness is too thick and it is difficult to incorporate it into a thin object such as an IC card.

そこで、半導体素子の片面のみに樹脂溶液をポッティン
グし、樹脂を塗布するという片面レジン塗布方式が提案
されている。Therefore, a single-sided resin coating method has been proposed in which a resin solution is potted on only one side of a semiconductor element and the resin is applied.

なお、フィルムキャリアについて述べた文献の例として
、（株）工業調査会１９８０年１月１５日発行ｒＩＣ化
実装技術ｊ　ｐ１０７〜１１３およびｐ１７５並びにｐ
１４３〜１４６があげられる。Examples of documents that describe film carriers include Kogyo Kenkyukai Co., Ltd., IC Mounting Technology J, published on January 15, 1980, p.107-113, p.175 and p.
143 to 146 are listed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記片面レジン塗りの場合、そのポツテ
ィングの際に樹脂溶液が半導体素子の底面下部にまで６
たれ”てきたり、あるいはその底面にまで周り込んでき
γこりし、その熱硬化したものがＴＡＢ素子全体の厚さ
を増大し、結局ＴＡＢ素子の薄膜化の要請に答えろこと
ができないし、また、ポツティング不良により歩留を悪
化させることになっていた。However, in the case of single-sided resin coating, the resin solution reaches the bottom of the semiconductor element during potting.
It may sag, or it may get all the way around the bottom surface and cause γ stiffness, and the heat-cured material increases the overall thickness of the TAB element, which ultimately makes it impossible to meet the demand for thinner TAB elements. Poor potting caused a decline in yield.

本発明はかかる従来技術の有する欠点を解消し、レジン
のたれ平底面への周り込みを防止し片面塗りを良好に行
なうことができ、ポツティングの作業性を向上させその
歩留を向上させ、かつ、ＴＡＢ素子の薄膜化に寄与する
ことのできる技術を提供することを目的とする。The present invention eliminates the drawbacks of the prior art, prevents resin from dripping around the flat bottom surface, enables good single-sided coating, improves potting workability, and improves yield. The present invention aims to provide a technology that can contribute to thinning TAB elements.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔問題点を解決するための手段〕[Means for solving problems]

本願において開示される発明のうち代表的なものの概要
を簡単に説明丁れは、下記のとおりである。A brief summary of representative inventions disclosed in this application is as follows.

丁なわち、本発明では半導体素子（チップ）の側面を段
付とし、当該側面（垂直面）に対し略直角の水平面を設
けた。That is, in the present invention, the side surface of the semiconductor element (chip) is stepped, and a horizontal surface substantially perpendicular to the side surface (vertical surface) is provided.

〔作用〕[Effect]

これにより、当該水平面でレジンの流れが止まり、した
がって、チップの底面にレジンが周り込んだり、当該底
面の下部にたれ下ることを防止することができた。As a result, the flow of the resin was stopped on the horizontal surface, and therefore, it was possible to prevent the resin from getting around the bottom surface of the chip or dripping down to the bottom of the bottom surface.

当該レジンの周り込みやたれ下りが防止できたので、フ
ィルムキャリアパッケージの薄膜化を達成することかで
き、また、ポッティングの作業性も良くなりその歩留も
向上した。Since it was possible to prevent the resin from wrapping around or dripping down, it was possible to achieve a thinner film carrier package, and the workability of potting was also improved, resulting in an increase in yield.

〔実施例〕〔Example〕

次に、本発明を図面に示す実施例に基づいて説明する。 Next, the present invention will be explained based on embodiments shown in the drawings.

第２図は本発明に使用されるチップの一例斜視図を示す
が、同図に示すようにチップ１の周側面に段を付設し、
当該チップを段付チップとする。FIG. 2 shows a perspective view of an example of the chip used in the present invention. As shown in the figure, a step is attached to the circumferential side of the chip 1,
The chip is a stepped chip.

チップ１の側面（垂直面）２．３に対し直角方向に水平
面４を設ける。A horizontal surface 4 is provided in a direction perpendicular to the side surface (vertical surface) 2.3 of the chip 1.

第３図はフィルムキャリアの一例平面図を示す。FIG. 3 shows a plan view of an example of a film carrier.

樹脂フィルムテープ５の両端部にはスプロケットホール
（バーフォレーンヨンホール）６が適宜間隔をおいて複
数穿設されている。A plurality of sprocket holes (bar fore holes) 6 are bored at appropriate intervals at both ends of the resin film tape 5.

当該ホール６の内側のテスト用バッド７からリード８が
伸び、デバイスホール９の内側に突出している。この突
出したチップボンディング用フィンガーリード１０の下
面にはチップ１がそのバンプ（突起を極）１１により取
着されている。このチップ１は第２図に示すような段付
チップに構成されている。Leads 8 extend from the test pad 7 inside the hole 6 and protrude inside the device hole 9. A chip 1 is attached to the lower surface of this protruding chip bonding finger lead 10 by means of its bumps (protrusions as poles) 11. This chip 1 is configured as a stepped chip as shown in FIG.

このチップ１の表蘭（上面）側から、デバイスホール９
内に、樹脂溶液をポッティングする。樹脂を熱硬化させ
た後切断線１２に沿い当該フィルムキャリアを切断する
。From the front (top) side of this chip 1, device hole 9
Pot the resin solution inside. After thermosetting the resin, the film carrier is cut along the cutting line 12.

第１図は、当該切断後の本発明の実施例を示すフィルム
キャリアパッケージの要部断面図である。FIG. 1 is a sectional view of a main part of a film carrier package showing an embodiment of the present invention after the cutting.

第１図に示すように、熱硬化後のポツティング液１３は
、チップ１の側面の前記水平面（段部）４にてとどまり
チップ１の底面に周わり込んだり、チップ１の底面下部
にたれ下ったりすることが防止されている。As shown in FIG. 1, the potting liquid 13 after thermosetting stays on the horizontal surface (step) 4 on the side surface of the chip 1, goes around the bottom surface of the chip 1, or drips down to the lower part of the bottom surface of the chip 1. It is prevented that

当該ポッティング液１３は、例えばエポキシ樹脂を溶剤
に溶解せしめてなる樹脂溶液により構成される。硬化剤
などの必要な添加剤を含んでいてもよい。The potting liquid 13 is composed of, for example, a resin solution obtained by dissolving an epoxy resin in a solvent. It may also contain necessary additives such as curing agents.

不発明におけるバンプの形成などは公知の当該フィルム
キャリアパッケージの形成技術を用いろことができる。Bumps can be formed using known techniques for forming the film carrier package.

半導体素子（チップ）１は、例えばシリコン単結晶？！
５版から成り、周知の技術罠よってこのチップ内には多
数の回路素子が形成され、１つの回路機能が与えられて
いる。回路素子の具体例は、例えばＮ１０Ｓトランジス
タから成り、これらの回路素子によって、例えば論理回
路およびメモリの回路機能が形成されている。Is the semiconductor element (chip) 1 made of silicon single crystal, for example? !
It consists of 5 versions, and by well-known technical tricks, a large number of circuit elements are formed within this chip to provide a single circuit function. A specific example of the circuit elements is, for example, an N10S transistor, and these circuit elements form the circuit functions of, for example, a logic circuit and a memory.

段付チップ１の形成は、例えば次のようにして行なうこ
とができろ。The stepped chip 1 can be formed, for example, as follows.

第４図は、ウェハの斜視図であり、このウェハ１４をス
クライブ線１５に沼いスクライブ（ダイシング）すると
チップを得ることができろが、当該ダイシング工程にお
いて、第５図に示すように大きさの異なるカッター１６
．１７により順次スクライブ線１５をつけていき、ウェ
ハ１４を切断すると第２図に示すようなチップ側面切断
面に段部４を有するチップ１を得るＣとができろ。FIG. 4 is a perspective view of a wafer. Chips can be obtained by scribing (dicing) this wafer 14 along scribe lines 15, but in the dicing process, the size as shown in FIG. 16 different cutters
．． When the wafer 14 is cut by scribing the scribe lines 15 in sequence using steps 17 and 17, a chip 1 having a stepped portion 4 on the cut side surface of the chip as shown in FIG. 2 is obtained.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明し１こが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。The invention made by the present inventor has been specifically described above based on examples.1 However, it is understood that the present invention is not limited to the above-mentioned examples, and that various changes can be made without departing from the gist of the invention. Needless to say.

例えば、上記実施例では段部（水平面）を−カ所設けろ
例を示したが、二刀所以上設げてもよい。For example, in the above embodiment, the stepped portion (horizontal surface) is provided at two or more locations, but two or more steps may be provided.

本発明のフィルムキャリアパッケージは片面塗りでそれ
もレジンのたれなどが防止されているので、極めて薄（
構成することができ、ＩＣカードとか電卓とか１チツプ
マイコンとか薄膜化が要求されるものに好適に組込みす
ることができる。The film carrier package of the present invention is coated on one side and prevents resin dripping, so it is extremely thin (
It can be suitably incorporated into IC cards, calculators, one-chip microcomputers, and other devices that require a thin film.

〔発明の効果〕〔Effect of the invention〕

本願において開示されろ発明のうち代表的なものによっ
て得られる効果を簡単に説明子れば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

本発明によれば、片面塗布方式のフィルムキャリアパッ
ケージにおいて、レジンのだれや底面への周り込みを防
止してポッティングの作業性を向上させ、その歩留を向
上しフィルムキャリアパッケージにおいて片面塗りと薄
膜化を実現することに成功した点工業上非常：て有意義
なものがある。According to the present invention, in a single-sided coating type film carrier package, potting workability is improved by preventing the resin from dripping or getting around the bottom surface, and the yield is improved. The fact that we succeeded in realizing this is extremely significant from an industrial perspective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例を示す要部断面図、第２図は本
発明の実施例を示すチップの斜視図、第３図はフィルム
キャリアの一例平面図、第４図はウェハの一例斜視図、 第５図は本発明の実施例を示す工程説明図である。 トチツブ、２，３・・・側面、４・・・水平面（段部）
、５・・・樹脂フィルムテープ、６・・・スプロケット
ホール、７・・・テスト用パッド、８・・リード、９・
・・デバイスホール、１０・・・チップボンディング用
フィンガーリード、１１・・・バンプ、１２・・・切断
線、１３・・・樹脂溶液、１４・・・ウニ・・、１５・
・・スクライブ線、１６・・カッター、１７・・・カッ
ター。 代理人　升埋士　　少　川　勝　男　　ノ、−゛チノ 第　　　１　　　図 １′７ 第　　２　　図Fig. 1 is a sectional view of a main part showing an embodiment of the present invention, Fig. 2 is a perspective view of a chip showing an embodiment of the invention, Fig. 3 is a plan view of an example of a film carrier, and Fig. 4 is an example of a wafer. The perspective view and FIG. 5 are process explanatory diagrams showing an embodiment of the present invention. Tochitsubu, 2, 3...Side surface, 4...Horizontal surface (stepped part)
, 5... Resin film tape, 6... Sprocket hole, 7... Test pad, 8... Lead, 9...
... Device hole, 10... Finger lead for chip bonding, 11... Bump, 12... Cutting line, 13... Resin solution, 14... Sea urchin..., 15.
...Scribe line, 16...Cutter, 17...Cutter. Agent Masu Burial Officer Katsuo Shokawa No. 1 Figure 1'7 Figure 2

Claims (1)

【特許請求の範囲】 １、立体形状に構成された半導体チップの周側面に段を
付設し、該チップの上面において該チップとリードとを
接続し、当該チップの上部から封止用樹脂溶液をポッテ
ィングして成ることを特徴とするフィルムキャリアパッ
ケージ。 ２、段付チップの段付が、ウェハのダイシング工程で行
われて成る、特許請求の範囲第１項記載のフィルムキャ
リアパッケージ。[Claims] 1. A step is attached to the circumferential side of a three-dimensional semiconductor chip, the chip and leads are connected on the top surface of the chip, and a sealing resin solution is applied from the top of the chip. A film carrier package characterized by being made by potting. 2. The film carrier package according to claim 1, wherein the stepped chip is stepped in a wafer dicing process.
JP61171570A 1986-07-23 1986-07-23 Film carrier package Pending JPS6329532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61171570A JPS6329532A (en) 1986-07-23 1986-07-23 Film carrier package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61171570A JPS6329532A (en) 1986-07-23 1986-07-23 Film carrier package

Publications (1)

Publication Number Publication Date
JPS6329532A true JPS6329532A (en) 1988-02-08

Family

ID=15925594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61171570A Pending JPS6329532A (en) 1986-07-23 1986-07-23 Film carrier package

Country Status (1)

Country Link
JP (1) JPS6329532A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09237807A (en) * 1996-02-28 1997-09-09 Nec Corp Manufacture of heat radiating resin sealed semiconductor device
JP2006073843A (en) * 2004-09-03 2006-03-16 Nec Electronics Corp Semiconductor device and its manufacturing method
US10350166B2 (en) 2009-07-29 2019-07-16 Foamix Pharmaceuticals Ltd. Non surface active agent non polymeric agent hydro-alcoholic foamable compositions, breakable foams and their uses

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09237807A (en) * 1996-02-28 1997-09-09 Nec Corp Manufacture of heat radiating resin sealed semiconductor device
JP2006073843A (en) * 2004-09-03 2006-03-16 Nec Electronics Corp Semiconductor device and its manufacturing method
US10350166B2 (en) 2009-07-29 2019-07-16 Foamix Pharmaceuticals Ltd. Non surface active agent non polymeric agent hydro-alcoholic foamable compositions, breakable foams and their uses

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