JPS63293862A - Method of flattening semiconductor substrate having step difference - Google Patents

Abstract

PURPOSE:To provide an interlayer insulating film having improved flatness and to improve the reliability of interconnections, by rotatively applying silica sol having siloxane bonds on a semiconductor substrate having step differences, and heat treating the silica sol for vitrifying the same and forming a silica film. CONSTITUTION:A silicon substrate 1 is thermally oxidized to form an underlying SiO2 film 2. Aluminum interconnection pattern 3 is formed thereon. Silica sol 7 having three-dimensional siloxane bonds is applied rotatively and is heat treated to vaporize the diluent thereof. The silica sol is further heat treated in the air. In this manner, an interlayer insulating film having improved flatness can be obtained and the reliability of the interconnection can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for planarizing an interlayer insulating film formed on a semiconductor substrate having steps, and particularly relates to planarizing steps that occur in a multilayer wiring process.

2. Description of the Related Art In the manufacture of semiconductor devices, as wiring patterns and transistors become more WTM, it has become necessary to flatten the underlying step with a glabella insulating film. The conventional planarization method is to use silica glass containing boron and phosphorus (hereinafter referred to as BPSG film).
The melt flow method, which flattens the material by flowing it at a high temperature of 900°C or higher, and the SOG method, which forms an insulating film (hereinafter referred to as silica film) by spin coating a solution containing a siloxane compound (hereinafter referred to as coating solution), etc. Can be mentioned.

Among these methods, the melt flow method requires a high temperature of 900'C or more, so it cannot be applied after the formation of the first layer Al wiring in a multilayer wiring process using AI. Therefore, after the formation of the first layer At wiring, the glabellar insulating film is flattened using the SOG method in which a silica film is formed by heat treatment at 450° C. or lower. Below is a fourth planarization method using the conventional SOG method.
This will be explained using figures.

FIG. 4 is a cross-sectional view showing the process of flattening the step caused by the first layer Al wiring, and for the sake of simplicity, transistors and the like formed before the first layer Al wiring process are omitted. First, a silicon dioxide film (hereinafter referred to as 5i02 film) 2 is formed as an insulating layer on a semiconductor substrate 1 by a thermal oxidation method or a CVD method, and then a first layer Al wiring 3 is formed. Furthermore, a 5i02 film 4 was formed by the CVD method, and then the coating solution was spin-coated to form a thickness of 300 nm, heat treated at 450°C for 30 minutes, and the glass was heated to form a silica film RT! A
form 5. Thereafter, a 5i02 film 6 is further formed by the CVD method to complete the flattening process.

Conventionally, as a coating liquid for forming the silica film membrane 5, a siloxane-based compound such as Rn5i (○
H) A solution containing a siloxane monomer or oligomer represented by 4-n, or a solution containing a one-dimensional or ladder type chain polysiloxane generally represented by the following structural formula is used. The symbol R in the above structural formula is
Indicates an organic group such as CH3, C2H3, C6H5. When a solution containing a siloxane monomer or oligomer is used as a silica film, cracks occur when the film thickness exceeds 300 nm.

Therefore, its flatness is extremely poor, and it remains at the level of a gentle taper on a steep step. On the other hand, when a solution containing chain polysiloxane is used as a silica film, it can be made as thick as about 1 μm on flat areas, and relatively good flatness can be achieved on steps formed by silicon or 5i02 films. can get. However, cracks still occur on AI wiring having a large area and in portions where the line width of the AI wiring is 2.0 μm or less.

The above-mentioned siloxane compounds are vitrified by heat treatment through a polycondensation reaction represented by the following formula %. This reaction almost converges at 900°C-1000°C, but at 450°C
It will not progress completely in about 30 minutes. The siloxane compound has an extremely high content of organic components such as alkyl groups in the molecule, resulting in reaction products and solvents being incorporated into the film and unreacted organic components remaining in the silica film. This adversely affects insulation properties and device reliability.

There is also a method of using polyimide resin for the applied insulating film. Polyimide resin has advantages such as better flatness than the silica film membrane, and can be made thicker because it is less prone to cracking, but on the other hand, it has greater hygroscopicity and a higher content of impurities than the silica film membrane. Furthermore, since the polarizability is high, there are many drawbacks such as deterioration of transistor performance.

Problems to be Solved by the Invention With the miniaturization of semiconductor devices, planarization of insulating films has become an indispensable technique. Formation of an interlayer insulating film by spin coating is low temperature, the process is simple, and it will become increasingly important in the future as a method for planarization without damage. However, there is no current coating liquid that satisfies all the requirements such as flatness, film thickness, crack resistance, insulation, moisture resistance, and high purity. One effective material that satisfies these conditions at the same time is a silanol compound, which has a structure similar to that of the 5i02 film and has a small amount of organic components, that is, a material that produces few reaction products due to thermal decomposition. In view of the above, an object of the present invention is to provide a method for planarizing a semiconductor substrate having steps using a glabellar insulating film that can be thickly filmed, has excellent flatness, and has low organic components and high insulation properties. It is said that

Means for Solving the Problems The present invention uses a silica sol having three-dimensional siloxane bonds (-Si-〇-3L-) as the coating liquid, spin coats it onto a semiconductor substrate having steps, and then heat-treats it. This is a method for planarizing a semiconductor substrate having steps, which is characterized by forming a silica film on a glass substrate.

The functional silica sol is one in which fine silica particles having a particle size of about 10 to 1100 nm are dispersed in a solvent. The terminal organic group exists only on the surface of the silica fine particles, and the inside thereof is composed of three-dimensional siloxane bonds (-Si-0-3i-). Therefore, there are fewer reaction products during the polycondensation reaction.
That is, shrinkage of the film due to heat treatment is suppressed. Therefore, by using the method according to the present invention, it is possible to form a thick interlayer insulating film with no cracks and excellent flatness. Further, it is possible to reduce the incorporation of unreacted organic components and reaction products remaining in the silica film into the film.

EXAMPLES The present invention will be explained in more detail below based on the drawings.

Example 1 As shown in FIG. 1, the base level difference is made by thermally oxidizing the silicon substrate 1 at 1000° C. to form the base 5i02 film 2 with a thickness of 400 nm.
The wiring pattern 3 of AI was formed thereon. The wiring pattern of A1 has a minimum line width of 1.2 μm,
When the minimum space is 1.0 μm, the film thickness of A], that is, the value indicated by the symbol in FIG. 1 is 1.0 μm. Siloxane bonds (-Si-0-3
i-), for example, a silica sol having an average particle size of 2 in a mixed solvent of water and isopropyl alcohol.
A silica sol containing 0 nm fine particles dispersed at a concentration of 15 wt% was spin-coated at 200 rpm for 30 seconds.
The solvent was evaporated by heat treatment at 20°C for 30 minutes, and the
Heat treatment was performed at 00°C for 130 minutes and then at 450°C for 130 minutes.

The thickness of the silica film membrane 7 formed in this way is
It was 1.1 μm on a flat surface. When the flatness is expressed as (1-a/b) using the symbols a and b in FIG. 1, the flatness of A1 with respect to the space C was good as shown in FIG. This flatness was comparable to that of conventional polyimide resins. Also, unlike conventional silanol-based compounds, no cracks occurred on the At wiring over a wide area or even in areas where the At wiring space was 1.0 μm.

Example 2 As a case closer to the conventional example, as shown in FIG.
After depositing the 5i02 film 4 to a thickness of 200 nm by the method, a silica film film 7 was formed in the same manner as in Example 1 above. If the flatness is expressed as (1-d/e) using the symbols d and e in FIG. 2 as in Example 1 above, the flatness of the silica film is equivalent to that in Example 1 above. Ta. In this case, the width f of the groove of the base step became narrower overall than the AI space due to the deposition of 5i021i14, and good flatness was obtained without cracking even with a groove width of 0.6 μm. In this way, Al
5 by CVD method between the wiring 3 and the silica film membrane 7
By sandwiching the i02 film 4, AI caused by the solvent of the coating solution can be removed.
can prevent corrosion.

In addition, the At wiring in Example 1 and Example 2 consists of AI and S.
It may also be an alloy with t, Cu, or the like.

Furthermore, the formation of the 5i02 film 4 is not limited to the CVD method, but may also be performed by bias sputtering or bias ECR. Further, phosphorus or boron may be added to the 5i02 film 4 or the silica film film 7 as an impurity.

In particular, the addition of phosphorus produces a gettering effect,
Deterioration of At wiring can be suppressed.

This time, a silica film was formed on a silicon substrate without steps in the same manner as in Example 1, and the film thickness before heat treatment and after heat treatment were measured. The film thickness after heat treatment was 95 to 98% of the film thickness after heat treatment. 70 of conventional coating liquid
Compared to ~80%, membrane shrinkage was significantly suppressed.

Effects of the Invention By using the method of the present invention, a glabellar insulating film with excellent flatness can be formed through a simple process, the upper layer At wiring is less likely to be disconnected, and the reliability of the wiring is significantly improved. Further, in the photolithography process, a more @:fM pattern can be easily formed. Furthermore, by using the method according to the present invention, it is possible to reduce the incorporation of unreacted organic components, reaction products, and solvents remaining in the silica film into the film, improve insulation properties, and reduce adverse effects on devices. It can be prevented.

[Brief explanation of drawings]

1 and 2 are partially enlarged sectional views of a semiconductor substrate for explaining an embodiment using the planarization method according to the present invention, and FIG. 3 is a partial enlarged sectional view of a semiconductor substrate using the planarization method according to the present invention. FIG. 4 is a diagram showing the flatness characteristic of the invention silica film film with respect to the space of the At wiring. FIG. 4 is a partially enlarged sectional view of a semiconductor substrate for explaining a method for flattening an interlayer insulating film by the conventional SOG method. 1...Semiconductor substrate, 2.4.6...5i02 film 3.
...AI wiring, 7...Silica film membrane using silica sol. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2 Figure 3 A, e space figure 4 A1 Shield agent

Claims (1)

[Claims] A coated insulator is formed by spin-coating a silica sol having three-dimensional siloxane bonds (-Si-O-Si-) onto a semiconductor substrate having steps, and the coated insulator is heat-treated to vitrify it. A method for planarizing a semiconductor substrate having steps, characterized in that: