JPS63292726A - Hierarchical decoding system - Google Patents

Abstract

PURPOSE:To attain hierarchical decoding with the quantity of operation equal to that of nonhierarchical decoding by utilizing effectively the result of arithme tic operation at each decoding stage for the arithmetic operation of the next stage. CONSTITUTION:Signals F0, F4 among coded signals (conversion data) F0-F7 are fed to a decoding circuit 11, the signals F2, F6 are fed to a decoding circuit 12 and the signals F1, F3, F5 and F7 are fed to a decoding circuit 13 and the decoding circuits 11, 12 apply the prescribed arithmetic operation to the next stage. Since the result of halfway of the arithmetic operation of each decoder circuit is utilized effectively the arithmetic operation of the decoding circuit of the next stage, the duplicated arithmetic operation having been so far applied in each decoding circuit is not required, and hierarchical decoding is applied by the quantity of arithmetic operation equal to the nonhierarchical decoding to maintain the advantage of the hierarchical decoding without any modification.

Description

[Detailed Description of the Invention] [Summary] The present invention is a transform coding method that hierarchically decodes frequency components, and the calculation results at each decoding stage are effectively used for the calculation at the next stage. However, this method performs hierarchical decoding with the same amount of computation as non-hierarchical decoding.

[Industrial application field]

The present invention relates to a hierarchical decoding method of transform encoding using orthogonal transform of a signal, for example, when a digital image signal or the like is band-compressed and transmitted.

[Conventional technology]

Examples of the encoding method include predictive encoding, vector quantization, and transform encoding. Among these methods, transform encoding requires complicated processing, but provides a relatively high quality decoded signal with a high compression ratio. In communication between a host computer and a terminal device that transmit encoded data via a narrowband channel as shown in Figure 5, when decoding is performed at the terminal, hierarchical decoding is required because the data transmission time is long. It is desirable to know the outline of the decoded signal at an early point in time after decoding.

The conventional technology will be explained below using transform coding using 8-point fast discrete cosine transform (FDCT) as an example.

FIG. 6 shows the processing flow of the FDCT method. Encoded data is obtained by performing FDCT on original data and then quantizing it, and decoded data is obtained by inversely quantizing it and then performing inverse FDCT.

The inverse FDCT part in the figure will be referred to as a decoding circuit hereinafter. When the decoding circuit receives transformed data obtained by dequantizing encoded data, it performs inverse FDCT and outputs decoded data.

An example of a non-hierarchical decoding method is shown in FIGS. 7 and 8. The non-hierarchical decoding circuit converts the converted data F(0) to
This circuit creates decoded signals r(0) to f(7) by performing the calculations shown in FIG. 8 on F(7).

The amount of calculation in this case is indicated by addition i■) 26 times, multiplication 1
6 times.

Here, a signal flow graph as shown in FIG. 8 will be explained. The signal encoded as described above is F(0)~
The decoded signal is denoted by F(7) and the decoded signal is f(0) to f(
7). The direction of processing is from left to right. ■
means adding the signals from the left, cosπ/
4 indicates that the signal from the left to which this is attached is multiplied by cosπ/4. - indicates the sign of the signal is inverted. This conversion is expressed mathematically as follows.

K=0.1.・-, N-1 j=0.1. -9N-1 An example of a conventional hierarchical decoding method is shown in FIGS. 9 and 10 to 12. In this case, three decoding circuits are used. In decoding circuit l, F(0) and F(4)
The calculation shown in Fig. 10 is performed for F(0) and F(4
) component is created. Decoding circuit (2
), then F(0) , F(4), F(2) , F(6)
The calculation shown in Fig. 11 is performed for F(0), F(
4) Create a decoded signal 2 containing F(2) and F(6) components. In the decoding circuit (3), F(0) to F(7
) for F(0) to F(
A decoded signal 3 containing all components of 7) is created.

In this way, in the hierarchical decoding method, decoding is performed by gradually increasing the frequency components included in the decoded signal. The total amount of calculations in this case is 36 additions and 24 multiplications. However, in multiplication, multiplication of one signal by the same value or the same value with different sign in one decoding circuit is calculated as one time.

[Problem that the invention seeks to solve]

When the above-described hierarchical decoding method is applied to, for example, an image signal, a decoded signal 1 containing F(0) and F(4) components is generated.
Since the image is created first, a general overview of the image can be obtained at an early stage. However, there are problems in that the total amount of calculations increases and the response time increases compared to non-hierarchical decoding methods.

In view of the above-mentioned problems with conventional hierarchical decoding methods, an object of the present invention is to realize a hierarchical decoding method that requires the same amount of computation as a non-hierarchical decoding method, thereby reducing processing time. It is to make it.

[Means for solving problems]

In the present invention, frequency components are hierarchically decoded.
A plurality of stages of decoding circuitry (e.g. first decoding circuit 11.1)
2.13) In the hierarchical decoding method in transform coding, each decoding circuit decodes based on the calculation result of the previous stage decoding circuit and the frequency component of the decoding circuit at that stage, , a hierarchical decoding method is provided which is characterized in that a decoded signal finally containing frequency components of all stages is obtained.

As one embodiment of the present invention, a hierarchical decoding method is provided that uses a fast discrete cosine transform as the orthogonal transform as the transform encoding.

[For production]

By using the above method, the intermediate results of the calculations in each decoding circuit can be effectively used in the calculations of the next stage decoding circuit, so that the calculations that were performed repeatedly in each decoding circuit can be avoided. Therefore, it is possible to improve the decoding processing speed.

〔Example〕

A block diagram of a decoding circuit that performs a hierarchical decoding method as an embodiment of the present invention is shown in FIG.

The decoding circuit is composed of three decoding circuits (1) to (3), and their signal flow graphs are shown in FIGS. 2 to 4.

In FIG. 1, among encoded signals (converted data) F(0) to F(7) to be decoded, F(0) and F(4) are sent to the decoding circuit (1) 11, and F( 2) and F
(6) goes to decoding circuit (2) 12, F(1), F(3)
, F(5), and F(7) are supplied to the decoding circuit (3) 13. The decoding circuit 11 performs processing as shown in the signal flow graph of FIG. 2 to create a decoded signal 1 (f(0) to f(7)) including F(0) and F(4).

That is, the decoding circuit 11 adds F(0) multiplied by CO8π/4 and F(4) multiplied by cosπ/4 to obtain f (0), f (3), f (4).
, f (7), and add F(0) multiplied by cosπ/4 and F(4) multiplied by −cosπ/4 to obtain f(1), f(2), f( 5), f(6)
shall be. The sum of the product of F(0) and cosyc/4 and the product of F(4) and cosπ/4 is accumulated as necessary and supplied to the next stage decoding circuit 12. F (0) and cosπ/
The sum of the product of 4 and the product of F(4) and -cosπ/4 is similarly accumulated and supplied to the decoding circuit 12. That is, the calculated values of the calculations enclosed in blocks and shaded in the figure are supplied to the next stage.

A signal flow graph of the decoding circuit 12 is shown in FIG. The calculated values from the previous stage are supplied to the portion indicated by the broken line block. This circuit is supplied with F(2) and F(6), and the calculations shown in the figure are performed to obtain F(0).
, F(4), F(2), and F(6), a decoded signal 2 (f(0) to f(7)) is obtained. In this circuit as well, the calculated values in the shaded arithmetic processing are supplied to the next stage (decoding circuit 13).

A signal flow graph of the decoding circuit 13 is shown in FIG. This circuit receives four inputs from the previous stage decoding circuit 12, and F(1), F(5), F(3), F(7)
Then, perform the calculation process shown in the figure to obtain F(
Decoded signal 3 (f(0) to f (
7)) is obtained.

In this embodiment, the calculation result shown in the solid line block with diagonal lines in FIG. 2 is used in the decoding circuit in FIG.
can be avoided. Similarly, by using the calculation results shown in the solid line blocks with diagonal lines in FIG. 3 in the decoding circuit shown in FIG. 4, the calculations conventionally performed in the blocks shown in broken lines become unnecessary.

According to this embodiment, the total amount of calculations is 26 additions and 16 multiplications, which is the same as the non-hierarchical decoding method.

Although the present embodiment has been described using FDCT as an example, other high-speed orthogonal transformation algorithms can also be used.

〔Effect of the invention〕

According to the present invention, hierarchical decoding can be performed with the same amount of computation as non-hierarchical decoding, and the advantages of hierarchical decoding can be maintained without reducing processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a decoding circuit that performs a hierarchical decoding method as an embodiment of the present invention, FIG. 2 is a diagram showing a signal flow graph of the decoding circuit (1) in FIG. 1, and FIG. Figure 4 is a diagram showing the signal flow graph of the decoding circuit (2) in Figure 1. Figure 5 is a diagram showing the signal flow graph of the decoding circuit (3) in Figure 1. A block diagram of the system; Figure 6 is a block diagram showing the processing flow of the FDCT method to explain related technology; Figure 7 is a block diagram showing a conventional non-hierarchical decoding circuit; Figure 8 is a conventional example. 9 is a block diagram of a conventional hierarchical decoding circuit, and FIGS. 10, 11, and 12 are diagrams showing a signal flow graph of a non-hierarchical decoding circuit of FIG. 1), (2), and (3) are diagrams showing signal flow graphs, respectively. In the figure, 11...decoding circuit (1), 12...decoding circuit (2)
), 13... decoding circuit (3).

Claims (1)

[Claims] 1. In a hierarchical decoding method in transform encoding, which consists of a plurality of stages of decoding circuits (11, 12, 13) that hierarchically decode frequency components, each of the decoding circuits comprises: , the calculation result of the decoding circuit of the previous stage,
A hierarchical decoding method characterized by decoding based on the frequency components of a decoding circuit at that stage to obtain a decoded signal containing frequency components at previous stages. 2. The hierarchical decoding method according to claim 1, wherein a high-speed discrete cosine transform is used as the orthogonal transform as the transform encoding.