JPH0821861B2 - Hierarchical decoding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is a transform coding method for hierarchically decoding frequency components, and the calculation result at each decoding stage is effectively used for the calculation at the next stage. However, this is a method of performing hierarchical decoding with an amount of calculation equivalent to that of non-hierarchical decoding.

[Industrial applications]

The present invention relates to a hierarchical decoding method of transform coding using orthogonal transform of a signal when, for example, a digital image signal or the like is band-compressed and transmitted.

[Conventional technology]

Predictive coding, vector quantization, transform coding, etc. are mentioned as a coding system. Among them, transform coding requires complicated processing, but a decoded signal with a high compression rate and a relatively high quality can be obtained. In the communication between the host computer and the terminal equipment which transmits the encoded data as shown in FIG. 5 through the narrow band channel, when the terminal decodes, the data transmission time is long and therefore the hierarchical decoding is performed. It is desirable to know the outline of the decoded signal at an early point after the conversion.

A conventional technique will be described below by taking transform coding using 8-point fast discrete cosine transform (FDCT) as an example. Figure 6 shows the flow of FDCT processing. Encoded data is FD on the original data
After performing CT, it is quantized, and by dequantizing it and then performing inverse FDCT, decoded data can be obtained. The portion of the inverse FDCT in the figure will be called the decoding circuit hereinafter. The decoding circuit executes the inverse FDCT when the transformed data obtained by dequantizing the encoded data is input, and outputs the decoded data.

An example of a non-hierarchical decoding scheme is shown in FIGS. 7 and 8. The non-hierarchical decoding circuit uses the converted data F (0)
It is a circuit which produces | generates decoded signal f (0) -f (7) by performing the calculation shown in FIG. 8 with respect to-F (7). The calculation amount in this case is addition (displayed by) 26 times, multiplication
16 times.

Here, a signal flow graph as shown in FIG. 8 will be described. The signal encoded as described above is F (0)
~ F (7), the decoded signal is f (0) ~ f
This is indicated by (7). The process proceeds from left to right.
Means to add the signals from the left side, cosπ / 4
Indicates that the signal from the left with this is multiplied by cosπ / 4. The display of-inverts the sign of the signal. This conversion is expressed by the following formula.

An example of a conventional hierarchical decoding scheme is shown in FIGS. 9 and 10-12. In this case, three decoding circuits are used. The decoding circuit 1 performs the operation shown in FIG. 10 on F (0) and F (4) to create a decoded signal 1 including F (0) and F (4) components. In the decoding circuit (2), the calculation shown in FIG. 11 is performed on F (0), F (4), F (2), F (6), and F (0), F (4), F (4)
Create a decoded signal 2 containing (2) and F (6) components. In the decoding circuit (3), the calculation shown in FIG. 12 is performed on F (0) to F (7) to create a decoded signal 3 including all components of F (0) to F (7).

As described above, in the hierarchical decoding method, decoding is performed by a method of gradually increasing the frequency components included in the decoded signal.
In this case, the total calculation amount is 36 additions and 24 multiplications. However, in the multiplication, one signal in one decoding circuit is multiplied by the same value or the same value with a different sign as once.

[Problems to be solved by the invention]

When the above-mentioned hierarchical decoding method is applied to, for example, an image signal or the like, the decoded signal 1 including the F (0) and F (4) components is first created, so that a general overview of the image can be obtained at an early stage. Obtainable. However, compared to the non-hierarchical decoding method, there is a problem that the total calculation amount increases and the response time becomes long.

The object of the present invention is to realize the hierarchical decoding method that requires the same amount of calculation as the specific hierarchical decoding method in view of the above-mentioned problems in the conventional hierarchical decoding method, and can shorten the processing time. Is to

[Means for solving problems]

In the present invention, a decoding circuit having a plurality of stages (for example, the decoding circuits 11 and 1 in FIG. 1) for hierarchically decoding frequency components
2, 13), each decoding circuit decodes based on the operation result of the decoding circuit of the previous stage and the frequency component of the decoding circuit of that stage,
Thereby, a hierarchical decoding scheme is provided which is characterized by finally obtaining a decoded signal containing frequency components of all stages.

As one embodiment of the present invention, there is provided a hierarchical decoding method using a fast discrete cosine transform as an orthogonal transform as the transform coding.

[Work]

If the above method is used, the intermediate result of the operation in each decoding circuit can be effectively used in the operation of the decoding circuit in the next stage, so that the operation which has been duplicated in each decoding circuit is not performed. Therefore, the decoding processing speed can be improved.

〔Example〕

FIG. 1 is a block diagram of a decoding circuit that performs a hierarchical decoding method as an embodiment of the present invention. The decoding circuit is composed of three decoding circuits (1) to (3), and their signal flow graphs are shown in FIGS. 2 to 4.

In FIG. 1, of the encoded signals (conversion data) F (0) to F (7) to be decoded, F (0)
And F (4) to the decoding circuit (1) 11, F (2) and F (6) to the decoding circuit (2) 12, F (1), F (3),
F (5) and F (7) are supplied to the decoding circuit (3) 13.
The decoding circuit 11 performs the processing as shown in the signal flow graph of FIG. 2 to create the decoded signal 1 (f (0) to f (7)) including F (0) and F (4). That is, in the decoding circuit 11, F (0) multiplied by cosπ / 4 and F (4) multiplied by cosπ / 4 are added to obtain f
(0), f (3), f (4), f (7), and F (0)
Is multiplied by cosπ / 4 and F (4) is multiplied by −cosπ / 4, and f (1), f (2), f (5),
Let f (6). The product of F (0) and cosπ / 4 and F (4)
And the product of cosπ / 4 and the sum of them are accumulated as needed and are supplied to the decoding circuit 12 in the next stage. The product of F (0) and cosπ / 4,
The sum of F (4) and the product of −cosπ / 4 is also accumulated and supplied to the decoding circuit 12. That is, the calculation value of the calculation surrounded by the blocks and shaded in the figure is supplied to the next stage.

A signal flow graph of the decoding circuit 12 is shown in FIG. The calculated value from the previous stage is supplied to the portion indicated by the broken line block. F (2) and F (6) are supplied to this circuit, and the calculation shown in the figure is performed to F (0),
Decoded signal 2 (f containing F (4), F (2), F (6)
(0) to f (7)) are obtained. Also in this circuit, the calculation value in the calculation process with diagonal lines is in the next stage (decoding circuit).
13).

A signal flow graph of the decoding circuit 13 is shown in FIG. This circuit receives four inputs from the decoding circuit 12 in the previous stage, and also receives F (1), F (5), F (3), and F (7) to perform the arithmetic processing as shown in the figure. , F (0)
Decoded signal 3 (f (0) to f (7)) including ~ F (7)
Is obtained.

In the present embodiment, the calculation result shown by the solid line block with diagonal lines in FIG. 2 is used in the decoding circuit in FIG. 3 to avoid duplicate calculation (calculation which is conventionally performed in the broken line block). . Similarly, by utilizing the calculation result shown by the shaded solid line block in FIG. 3 in the decoding circuit in FIG. 4, the calculation conventionally performed in the broken line block becomes unnecessary. According to the present embodiment, the total calculation amount is 26 times of addition,
The multiplication is 16 times, and the amount of calculation is the same as the non-hierarchical decoding method.

In the present embodiment, the FDCT has been described as an example, but another fast algorithm of orthogonal transformation can be used.

〔The invention's effect〕

According to the present invention, hierarchical decoding can be performed with an amount of calculation equivalent to that of non-hierarchical decoding, and the advantages of hierarchical decoding can be maintained without reducing the processing speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a decoding circuit that performs a hierarchical decoding system as an embodiment of the present invention, FIG. 2 is a diagram showing a signal flow graph of the decoding circuit (1) in FIG. 1, and FIG. FIG. 4 is a diagram showing a signal flow graph of the decoding circuit (2) in FIG. 1, FIG. 4 is a diagram showing a signal flow graph of the decoding circuit (3) in FIG. 1, and FIG. 5 is a transmission for explaining related art. 6 is a block diagram of the system, FIG. 6 is a block diagram showing a processing flow of the FDCT method for explaining related arts, FIG. 7 is a block diagram showing a non-hierarchical decoding circuit of a conventional example, and FIG. 8 is a conventional example. 9 is a signal flow graph of the non-hierarchical decoding circuit of FIG. 9, FIG. 9 is a block diagram of a conventional hierarchical decoding circuit, and FIGS. 10, 11, and 12 are decoding circuits of FIG. The signal flow graphs of 1), (2), and (3) are shown respectively. FIG. In the figure, 11 ... Decoding circuit (1), 12 ... Decoding circuit (2), 13 ... Decoding circuit (3).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Nakagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP-A-63-212287 (JP, A) JP-A-63-263983 (JP, A) Japanese Patent Publication 4-32457 (JP, B2)

Claims (2)

[Claims] 1. A hierarchical decoding system in transform coding, comprising a plurality of stages of decoding circuits (11, 12, 13) for hierarchically decoding frequency components, wherein each decoding circuit The operation result of the stage decoding circuit,
A hierarchical decoding method characterized in that decoding is performed based on the frequency components of the decoding circuit at that stage, and a decoded signal including the frequency components at the stages up to that point is obtained. 2. The hierarchical decoding system according to claim 1, wherein a high-speed discrete cosine transform is used as an orthogonal transform as the transform coding.