JPS63292617A - Manufacture of soi substrate - Google Patents
Manufacture of soi substrateInfo
- Publication number
- JPS63292617A JPS63292617A JP12689087A JP12689087A JPS63292617A JP S63292617 A JPS63292617 A JP S63292617A JP 12689087 A JP12689087 A JP 12689087A JP 12689087 A JP12689087 A JP 12689087A JP S63292617 A JPS63292617 A JP S63292617A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- crystal grains
- crystal
- orientation
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000013078 crystal Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 238000009279 wet oxidation reaction Methods 0.000 abstract description 2
- 230000005465 channeling Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はＳＯＩ基板の製造方法に関し、特に単結晶基板
を種として用いることなく、結晶方位の制御されたＳＯ
Ｉ基板を製造する方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing an SOI substrate, and in particular to a method for manufacturing an SOI substrate with controlled crystal orientation, without using a single crystal substrate as a seed.
The present invention relates to a method of manufacturing an I-substrate.
［従来の技術］
Ｓ ＯＩ （Ｓｉ ｌ １ｃｏｎ Ｏｎ Ｉｎ５ｕｌａ
ｔｏｒ）構造は、半導体集積回路の高集積化、高速度化
、耐放射線などにとって有利であることから、重要性が
高い。また、能動層を絶縁体層を介して多層に重ねた積
層素子（三次元回路素子）のための基本技術である。[Prior art] SOI
The (tor) structure is highly important because it is advantageous for higher integration, higher speed, radiation resistance, etc. of semiconductor integrated circuits. It is also a basic technology for multilayer devices (three-dimensional circuit devices) in which active layers are stacked in multiple layers with insulating layers interposed in between.
Ｓｏｌ構造において、その結晶方位を制御することは各
素子時、性の均一性を保つために不可欠の技術である。In the Sol structure, controlling the crystal orientation is an essential technique for maintaining uniformity of properties in each element.
しかし、一般にＳＯＩ構造における絶縁体は非晶質であ
るために、結晶方位の制御されたＳＯＩ基板の製造には
特別の工夫か必要である。However, since the insulator in the SOI structure is generally amorphous, special measures are required to manufacture an SOI substrate with controlled crystal orientation.
単結晶基板を種としない結晶方位の制御方法としては、
■グラフオエピタキシー法（ジャーナル・オブ・クリス
タルグロース８志、第６３巻、５２７ページ〉、■シー
ドセレクションスルーイオンチャネリング法（アプライ
ド・フィジックス・レター誌、第１４６巻、６８３ペー
ジ〉、■２−ステップレーザアニール法（第４５回応用
物理学会講演会予稿集、４１２ページ）などが提供され
ている。As a method for controlling crystal orientation without using a single crystal substrate as a seed,
■Graphoepitaxy method (Journal of Crystal Growth 8th Vol. 63, page 527), ■Seed selection through ion channeling method (Applied Physics Letters, volume 146, page 683), ■2-step Laser annealing methods (Proceedings of the 45th Japan Society of Applied Physics Conference, page 412) are provided.
［発明が解決しようとする問題点］
上述の結晶方位制？ｆｆ１１方法は、それぞれに特徴を
有しているか、実用化にあたっては問題点を残している
。すなわち、■のグラフカエピタキシー法では、加二「
か困！Ａｌｔであること、および熱処理中に変形か生じ
ること、■のシードセレクションスルーイオンチャネリ
ング法では８０１層の厚さに苅する制限かぎびしく、ま
た、イオンビームの平行性、単板の保持精度の点て通常
のイオン注入装置か使えないこと、■の２−ステップレ
ーリ゛アニール法ではスループッ１への低さ、高温プロ
セスであることなどがそれぞれ問題となる。従ってこれ
らの問題点を解決したＳＯ■基板の製造方法か望まれて
いる。[Problem to be solved by the invention] The above-mentioned crystal orientation system? Each of the ff11 methods has its own characteristics, or there are still problems in practical implementation. In other words, in the graphka epitaxy method of ■,
Trouble! In the seed selection through ion channeling method described in (2), there is a severe limitation on the thickness of 801 layers, and there are also problems with the parallelism of the ion beam and the holding accuracy of the veneer. However, there are problems such as the inability to use a normal ion implantation device, the low throughput of 1, and the high temperature process in the 2-step Ray annealing method (2). Therefore, there is a need for a method of manufacturing SO2 substrates that solves these problems.
「問題点を解決するための手段」
本発明は非晶質絶縁体上に多結晶シリコン膜をその結晶
粒径と同等以下の膜厚に堆積Ｊる工程と酸化速度か結晶
方位によって異なる選択的熱酸化を前記多結晶シリコン
膜に対して行う工程と、この工程で形成されたＳｉＯ２
をエツチングにより除去して単板法線方向の結晶方位に
おいて最も前記酸化速度か小さくなるようなシリコン結
晶粒のみを残す工程と、この結晶粒か残された基板上に
非晶質シ１ノ］ンを堆積する工程と、この非晶質シリコ
ンを熱処理して前記結晶粒を種とする結晶化を行う工程
とを備えてなることを特徴とするＳＯＩ基板の製造方法
である。``Means for Solving the Problems'' The present invention involves a process of depositing a polycrystalline silicon film on an amorphous insulator to a thickness equal to or less than the crystal grain size, and a selective method that varies depending on the oxidation rate or crystal orientation. A step of thermally oxidizing the polycrystalline silicon film and SiO2 formed in this step.
A process of removing by etching to leave only the silicon crystal grains that have the lowest oxidation rate in the crystal orientation in the normal direction of the veneer, and forming an amorphous silicone on the remaining substrate with these crystal grains. This method of manufacturing an SOI substrate is characterized by comprising a step of depositing amorphous silicon, and a step of heat-treating the amorphous silicon to crystallize it using the crystal grains as seeds.
［作用］
単結晶基板を使用しないで結晶方位を制御するために、
本発明では、最初に非晶質絶縁体上に堆積された多結晶
シリコン膜に含まれる各種の方位の結晶粒の中から、特
定の方位を持つ結晶粒のみを残す工程を設けている。シ
リ」ンの熱酸化の速度は、適当な条件下では結晶面方位
に大きく依存する。これを利用することによって基板法
線方向の結晶方位か酸化速度の最も小さい方位となる結
晶粒のみを残覆−ことかてぎる。例えば、９００ ’Ｃ
てのウエッ］〜酸化によれば酸化速度は（１１１）、（
３１１）、 （１００）面の順であり、 （１００）面
の酸化速度か最も小さく、他の面は（ｉｏｏ）面の１，
５倍程度大きな値でおる。熱酸化の過程において、はじ
めは多結晶シリコン膜の表面から酸化されるか、酸化の
進行にしたかって各結晶粒の側面からの酸化も生じる。[Function] In order to control the crystal orientation without using a single crystal substrate,
In the present invention, a step is provided in which only crystal grains having a specific orientation are left among crystal grains having various orientations contained in a polycrystalline silicon film initially deposited on an amorphous insulator. The rate of thermal oxidation of silicon is highly dependent on crystal plane orientation under appropriate conditions. By utilizing this, it is possible to leave only the crystal grains oriented in the direction normal to the substrate or in the direction with the lowest oxidation rate. For example, 900'C
According to oxidation, the oxidation rate is (111), (
311), (100) plane, the oxidation rate of (100) plane is the lowest, and the other planes are (ioo) plane 1,
The value is about 5 times larger. In the process of thermal oxidation, the surface of the polycrystalline silicon film is oxidized first, or as the oxidation progresses, oxidation also occurs from the side surfaces of each crystal grain.
しかし、結晶粒径が膜厚と同程度以上て市れば、酸化速
度の大きな方位の結晶粒かすぺ゛Ｃ基板で市る非晶質絶
縁体との界面まで酸化され、しかも酸化速度の小さな方
位の結晶粒は部分的にしか酸化されない状態が得られる
。この時点て酸化を停止したのら、酸化物ＳｉＯ２をエ
ツチングで除去すれば良い。However, if the crystal grain size is equal to or larger than the film thickness, the crystal grains in the direction where the oxidation rate is high will be oxidized to the interface with the amorphous insulator formed on the SPEC substrate, and the oxidation rate will be low. A state is obtained in which oriented crystal grains are only partially oxidized. After stopping the oxidation at this point, the oxide SiO2 may be removed by etching.
一旦、特定方位の結晶粒のみが残れば、この上に非晶質
シリコンを堆積し結晶化を行わけると、残された特定方
位の結晶粒か種となって結晶化か牛し、仝而を同一結晶
方位とすることかできる。Once only crystal grains with a specific orientation remain, if amorphous silicon is deposited on top of this and crystallized, the remaining crystal grains with a specific orientation will become seeds and will crystallize. can have the same crystal orientation.
［実施例］
以下、本発明の実施例について図面を参照して詳細に説
明する。[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明方法の一実施例を説明するための工程図
である。ます、ＳｉＯ２基板１上に多結晶シリコン膜２
を６７０°○でのｌ ＰＣＶＤ法により形成した（第１
図（ａ））。次に９００’Ｃてのウェット酸化処理と、
酸化物ＳｉＯ２のエツチングを行った。FIG. 1 is a process diagram for explaining one embodiment of the method of the present invention. First, a polycrystalline silicon film 2 is formed on a SiO2 substrate 1.
was formed by l PCVD method at 670°○ (first
Figure (a)). Next, wet oxidation treatment at 900'C,
The oxide SiO2 was etched.
この結果、多結晶シリコン膜に含まれる各種の結晶方位
の結晶粒のうち、酸化速度の最も小さい基板法線方向か
＜１００＞の結晶′）ｇＩ３が選択的に残される（第１
図（ｂ））。次いてこのトに基板を常温に保ち、真空装
置内で非晶質シリコン４を堆積する（第１図（Ｃ））。As a result, among the crystal grains with various crystal orientations contained in the polycrystalline silicon film, the crystals (')gI3 in the direction normal to the substrate or <100>, which have the lowest oxidation rate, are selectively left (the first
Figure (b)). Next, while keeping the substrate at room temperature, amorphous silicon 4 is deposited in a vacuum apparatus (FIG. 1(C)).
６００°Ｃて４時間の熱処理を行うことにより、前）ホ
の選択的に残された結晶粒を種とする非晶質シリコンの
結晶化が起こり、仝而かｄｏｏ＞方位に制御されたＳＯ
Ｉ層５が得られた（第１図（ｄ））。この８０１層の膜
厚は堆積させる非晶質シリコンの厚さを変えることによ
り所望の厚さとすることかできた。By performing heat treatment at 600°C for 4 hours, amorphous silicon crystallizes using the selectively left crystal grains of (e) as seeds, resulting in SO controlled in the doo> orientation.
An I layer 5 was obtained (FIG. 1(d)). The thickness of the 801 layer could be adjusted to a desired thickness by changing the thickness of the amorphous silicon deposited.
上）小の工程においては、多結晶シリコン膜を６７０°
ＣてのＬ Ｐ ＣＶ Ｄ法で形成したか、これは多結晶
シリコン膜の配向性がほぼランダムとなり＜１１１＞、
＜１１０＞、＜３１１＞、＜１００＞などの結晶粒の割
合かほぼ一様となる条件である。ＬＰＣＶＤ法−〇 −
の温度、圧力によりこの配向性は変化するので、目的に
応じてこれらの条件を決定すればよい。また、非晶質シ
リコンの結晶化を６００℃の同相成長 （ａ）によって
行っているが、同相成長の場合、温度か高い方が成長速
度は速くなるが、非晶質シリコン中ての核形成が生じて
方位制御か不十分となるためにここ−Ｃは６００°Ｃと
している。Above) In the small process, the polycrystalline silicon film is
The orientation of the polycrystalline silicon film is almost random and is formed using the L P CV D method.
This is a condition in which the ratio of crystal grains such as <110>, <311>, and <100> is almost uniform. Since this orientation changes depending on the temperature and pressure of the LPCVD method, these conditions may be determined depending on the purpose. In addition, amorphous silicon is crystallized by in-phase growth at 600°C (a), but in the case of in-phase growth, the higher the temperature, the faster the growth rate, but nucleation in amorphous silicon -C is set to 600°C because this causes insufficient azimuth control.
本発明の方法によれば、酸化速度が結晶方位に依存する
条件下での熱酸化という簡単な方法で特定の方位を持つ
結晶粒のみを残すことかでき、方位制御のされたＳＯＩ
基板が得られる。According to the method of the present invention, only crystal grains with a specific orientation can be left by a simple method of thermal oxidation under conditions where the oxidation rate depends on the crystal orientation, and SOI with orientation control can be obtained.
A substrate is obtained.
第１図は本発明方法の一実施例を示す工程図で （Ｃ）
ある。
１・・・ＳｉＯ２基板 ２・・・多結晶シリコン
膜３・・・基板法線方向か＜１００＞の結晶粒４・・・
非晶質シリコン ５・・・ＳＯＩ層（ｄ）
代理人弁即士 舘 野 千惠子第１図Figure 1 is a process diagram showing an example of the method of the present invention (C)
be. 1...SiO2 substrate 2...Polycrystalline silicon film 3...Crystal grains of <100> in the normal direction of the substrate 4...
Amorphous silicon 5...SOI layer (d) Attorney Chieko Tateno Figure 1
Claims (1)
径と同等以下の膜厚に堆積する工程と、酸化速度が結晶
方位によって異なる選択的熱酸化を前記多結晶シリコン
膜に対して行う工程と、この工程で形成されたＳｉＯ＿
２をエッチングにより除去して基板法線方向の結晶方位
において最も前記酸化速度が小さくなるようなシリコン
結晶粒のみを残す工程と、この結晶粒が残された基板上
に非晶質シリコンを堆積する工程と、この非晶質シリコ
ンを熱処理して前記結晶粒を種とする結晶化を行う工程
とを備えてなることを特徴とするＳＯＩ基板の製造方法
。(1) A process of depositing a polycrystalline silicon film on an amorphous insulator to a thickness equal to or less than the crystal grain size, and selective thermal oxidation of the polycrystalline silicon film, the oxidation rate of which varies depending on the crystal orientation. and the SiO_ formed in this process.
2 by etching to leave only the silicon crystal grains where the oxidation rate is the lowest in the crystal orientation in the normal direction of the substrate, and depositing amorphous silicon on the substrate where the crystal grains remain. A method for manufacturing an SOI substrate, comprising: a step of heat-treating the amorphous silicon to crystallize the amorphous silicon using the crystal grains as seeds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12689087A JPS63292617A (en) | 1987-05-26 | 1987-05-26 | Manufacture of soi substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12689087A JPS63292617A (en) | 1987-05-26 | 1987-05-26 | Manufacture of soi substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63292617A true JPS63292617A (en) | 1988-11-29 |
Family
ID=14946391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12689087A Pending JPS63292617A (en) | 1987-05-26 | 1987-05-26 | Manufacture of soi substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63292617A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7351654B2 (en) | 2004-05-19 | 2008-04-01 | Elpida Memory, Inc. | Semiconductor device and method for producing the same |
-
1987
- 1987-05-26 JP JP12689087A patent/JPS63292617A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7351654B2 (en) | 2004-05-19 | 2008-04-01 | Elpida Memory, Inc. | Semiconductor device and method for producing the same |
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