JP2002313719A - Crystalline semiconductor thin film and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high quality crystallization of an amorphous semiconductor thin film to form a high performance semiconductor deice (e.g. TFT). SOLUTION: The manufacturing method comprises forming a specified pattern 10 from an amorphous silicon thin film, introducing a catalyst element into introducing regions 11 and heat treating to from crystal grains 100. The width and thickness of a crystallized region 12 are not greater than ten times the crystal grain 100 (e.g. 1 μm or less) in the initial crystallizing stage. This allowing only the single crystal grin 100 to pass through the crystallizing region 12. Among equivalent <111> planes, only any one kind of facets are formed on the top ends of the crystal grains 100 and moved in a one-dimensional direction to crystallize the amorphous silicon thin film in the crystallizing regions 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a crystalline semiconductor thin film and a method for manufacturing the same. More specifically, the present invention relates to a crystalline semiconductor thin film crystallized by heating an amorphous semiconductor formed on an amorphous substrate or an amorphous insulating film, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A technique of forming a high-performance polysilicon thin film on an amorphous substrate or an amorphous insulating film to form a thin film transistor (TFT) is applied to a liquid crystal display or an SRAM. (Static R
The range of application of andom access memory) to load devices and application to three-dimensional ICs is extremely wide and is being actively studied.

In recent years, in particular, single-crystal substrates or SOI (Si
Crystallization technology that is comparable to a substrate (icon on insulator) and aims at high mobility is being enthusiastically studied. Among these techniques, a technique of crystallizing an amorphous silicon thin film by adding a trace amount of a transition metal represented by nickel is very unique. By this method, a very wide area can be formed without a large tilt grain boundary. This method uses SMC (Silicide-Midiated Crystallization).
) Method, MIC (Metal Induced Crystallization)
Method, MILC (Metal Induced Lateral Crystallizatio)
n) Often abbreviated as law. If the metal is particularly limited to nickel, CANDI (Crystallization Assi
sted by Nickel DIsilicide) method. For example, for the invention already filed by the applicant (Japanese Patent Application 2000
According to -320095), it is possible to crystallize such that a large tilt grain boundary does not exist in a predetermined region.

[0004]

It is known that the CANDI method can crystallize a predetermined region so that there is no large-angle grain boundary, so that higher TFT characteristics can be obtained as compared with the conventional solid phase growth method. Have been. However, as compared with a melt crystallization method such as a laser crystallization method, the top data of the characteristics is inferior. This is because the crystal obtained by the CANDI method has a relatively high density of crystal defects, although the characteristic deterioration due to grain boundaries is small. Therefore, an SOP that attempts to integrate circuits having various functions on a glass substrate
In order to form TFTs with higher characteristics required for applications such as (System On Panel), it is desired to reduce crystal defects and further improve crystal quality itself.

Therefore, the present inventors have investigated in detail the cause of high crystal defects in the current CANDI method. CAND
In the I method, the crystal is grown in units of a fiber having a width of about 10 nm to 100 nm, and an N
A platelet of iSi ₂ is present. This silicide platelet moves with the growth of the fiber and always exists at the tip of the fiber. The crystals of NiSi ₂ and silicon differ only by 0.4% in lattice constant, and have very good matching. It is a feature of the CANDI method that silicon grows favorably on the NiSi ₂ platelet.

However, when the growth at the fiber tip was examined in detail, the following problems were found. The NiSi ₂ platelet at the tip has a so-called facet growth surrounded by {111} planes. In the growth of a thin film, it cannot be grown in the film thickness direction, so {111}
There will be three growth planes equivalent to the plane. For example, when the fiber tip has a {100} crystal plane, these three growth faces are all inclined at 54.75 degrees with respect to the fiber tip face, and intersect each other at right angles.

FIG. 1A is a perspective view showing the shape of a NiSi ₂ platelet 100 at the tip of a fiber growing on a {100} plane, and the {100} plane of the fiber is indicated by oblique lines. FIG. 1B is a schematic view showing a change in the shape of the fiber tip surface 1 growing on the {100} plane. As the fiber grows from the amorphous silicon side 2 to the crystalline silicon side 3, the fiber tip face 1 Becomes wider. FIG. 1A, 1
As shown in B, 3 of NiSi ₂ play door toilet 100
Since the crystallization proceeds at the same rate from the growth plane in the direction, the width of the fiber increases rapidly. In order to maintain the balance of the amount of nickel necessary for silicide formation at the tip of the fiber, the NiSi ₂ platelet 100 rapidly becomes thinner, and gradually becomes unable to maintain the amount of nickel necessary for silicide formation, and eventually stops crystal growth. Would.

After the growth is stopped for a certain period of time, when the tip of the fiber is replenished with nickel and small silicide can be formed again, the growth in the growth direction causes splitting or branching in another equivalent direction, and the growth is resumed. Begin. In the solid phase growth, stress is generally large, so that minute crystal orientation fluctuations occur between fibers due to splitting or branching, and crystal defects such as dislocations are induced. FIG.
TEM of {100} -grown fiber
This is a photograph taken by a Smission Electron Microscope, and the width of the fiber is rapidly expanding from the bottom to the top of the photograph.

FIG. 3A is a perspective view showing the shape of the NiSi ₂ platelet 100 at the tip of the fiber growing on the {110} plane, and the {110} plane of the fiber is shown by oblique lines. FIG. 3B is a schematic diagram showing a change in the shape of the fiber tip surface 1 growing on the {110} plane. As the fiber grows from the amorphous silicon side 2 to the crystalline silicon side 3, the fiber tip face 1 Gradually increases. When the fiber has a {110} plane or another crystal plane, they intersect each other at an obtuse angle,
The speed at which the width of the fiber spreads decreases. However, as in the case of the {100} plane, the width of the fiber gradually widens, and growth cannot be maintained. Therefore, the growth stops temporarily, and thereafter, the branch grows in an equivalent direction.

As described above, for each fiber, a high-quality crystal is formed by epitaxial growth on the NiSi ₂ platelet 100. Nevertheless, the NiSi ₂ platelet 100 having a certain size is maintained since it grows from three growth planes equivalent to the {111} plane at the tip in the growth direction (hereinafter, also referred to as two-dimensional growth). No, splitting and branching occur frequently. Due to misfit between crystals due to division or branch growth, the whole is a thin film containing high-density crystal defects.

An object of the present invention is to provide a high-quality crystalline semiconductor thin film having extremely few crystal defects and a method for producing the same.

[0012]

According to a method of manufacturing a crystalline semiconductor thin film of the present invention, a catalytic element for promoting crystallization of the amorphous semiconductor thin film is introduced into an amorphous semiconductor thin film formed on a substrate. Forming a crystal grain from the semiconductor and the catalyst element, and crystallizing the amorphous semiconductor thin film by moving the crystal grain, the method for manufacturing a crystalline semiconductor thin film, comprising: Forming a pattern including at least a step of forming the amorphous semiconductor thin film, a first region including an introduction region into which the catalyst element is introduced, and a crystallized region connected to the first region; Forming a semiconductor thin film, introducing the catalytic element into the introduction region, heating the catalytic element introduced into the introduction region to form at least a single crystal grain, Single grain movement Crystallizing the amorphous semiconductor thin film in the crystallized region, wherein the thickness and width of the crystallized region are set to 10 times the size of the crystal grains formed at the beginning of crystal growth. A facet of only one of the equivalent {111} planes is formed at the tip of the single crystal grain moving in the crystallization region, and the facet is one-dimensional. By moving in the direction, the amorphous semiconductor thin film is crystallized.

The method for producing a crystalline semiconductor thin film of the present invention comprises:
It is preferable that the thickness and width of the crystallized region be 1 μm or less.

Further, the first region of the pattern further has a pre-growth region connecting the introduction region and the crystallization region, and a width of the pre-growth region at a connection portion with the crystallization region is The crystal grains larger than the width of the crystallization region and formed in the introduction region may pass through the preliminary growth region toward the crystallization region.

[0015] The crystalline semiconductor thin film of the present invention is characterized in that crystal grains formed from a catalyst element for promoting crystallization of an amorphous semiconductor thin film and the semiconductor move in the amorphous semiconductor thin film. A crystalline semiconductor thin film obtained by crystallizing the amorphous semiconductor thin film, wherein a facet of only one of the equivalent {111} faces is formed at a tip of the crystal grain; Moves in a one-dimensional direction, whereby the amorphous semiconductor thin film is crystallized.

In the crystalline semiconductor thin film according to the present invention, the thickness and width of a crystallized region in which the facet moves in a one-dimensional direction are not more than 10 times the width of the crystal grains formed at an early stage of crystal growth. Is preferred.

A semiconductor device according to the present invention includes the above crystalline semiconductor thin film. Further, the TFT of the present invention includes the above crystalline semiconductor thin film in a channel region, and a gate electrode is in contact with both side surfaces of the crystalline semiconductor thin film in the channel region. Further, a display device of the present invention includes the semiconductor device described above.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, a TFT using a crystalline silicon thin film for a channel will be described as an example. The present invention can be applied to silicon, germanium, a mixed crystal of germanium and silicon, and compounds thereof.

Although an amorphous substrate or an amorphous insulating film is used as the substrate, a quartz substrate is used in the following embodiments. Before forming the amorphous silicon film on the quartz substrate, a base film made of silicon oxide is formed on the quartz substrate to prevent impurities in the substrate from diffusing into the amorphous silicon film. preferable. In the present invention, the “substrate” includes a substrate in which another film such as a base film is stacked on an amorphous substrate or an amorphous insulating film.

In this specification, for the sake of simplicity, the terms “pattern” and “amorphous silicon thin film” may be omitted. For example, “the film thickness of the pattern in the crystallized region” may be described as “the film thickness of the crystallized region”.

(Embodiment 1) The method for producing a crystalline semiconductor thin film of the present invention comprises (1) a step of forming an amorphous semiconductor thin film on a substrate, (2) an introduction region into which a catalytic element is introduced, Forming an amorphous semiconductor thin film in a pattern having at least a crystallization region connected to the region, (3) introducing a catalyst element into the introduction region, and (4) introducing the catalyst element into the introduction region. A step of heating to form at least a single crystal grain; and (5) a step of crystallizing the amorphous semiconductor thin film in the crystallization region by moving the single crystal grain. FIG. 4 is a plan view illustrating a manufacturing process of the crystalline semiconductor thin film of the first embodiment. Each manufacturing process (1) to (5) will be described with reference to FIG.

(1) Step of Forming Amorphous Silicon Thin Film This step is a step of forming an amorphous silicon thin film on a substrate. The method of forming the amorphous silicon thin film on the substrate is not particularly limited, but may be a plasma CVD (Chemic) method.
al Vapor Deposition) method and sputtering method.

The thickness of the amorphous silicon thin film formed on the substrate is 10 times or less, preferably 1 μm or less, of the width of the crystal grains formed in the initial stage of crystal growth. The thickness of the amorphous silicon thin film is set to 10 times the width of a crystal grain formed in the initial stage of crystal growth.
If it exceeds twice, two-dimensional growth may occur in a crystallization region described later, and crystallinity may be deteriorated.

The width of a crystal grain formed at the initial stage of crystal growth is
Although it depends on the type of the catalyst element, for example, NiSi ₂
In this case, it is about 5 nm to 100 nm. The width of the crystal grains formed in the initial stage of crystal growth can be measured using, for example, an optical microscope. The lower limit of the thickness of the amorphous silicon thin film is not particularly limited, and is determined in consideration of the characteristics of a semiconductor device to be manufactured. In the present embodiment, the thickness of the amorphous silicon thin film is 30 nm or more and 100 nm or less. The width of the crystal grains formed in the initial stage of crystal growth will be described later.

(2) Patterning Step In this step, an amorphous silicon thin film is formed into a predetermined pattern (FIG. 4).
A). This pattern 10
At least a first region 15 including the introduction region 11 and a crystallization region 12 connected to the first region 15 are provided. The introduction region 11 is a region into which a catalyst element that promotes crystallization of the amorphous silicon thin film is introduced. The crystallization region 12 is made of TF
This is a region that becomes a channel of T.

The width of the crystallized region 12 is 10 times or less, preferably 1 μm or less, of the width of a crystal grain formed at the beginning of crystal growth. If the width of the crystallized region 12 exceeds 10 times the width of the crystal grains formed in the initial stage of crystal growth, two-dimensional growth occurs in the crystallized region 12 and the crystallinity may be degraded.

The thickness and width of the crystallized region 12 are limited to 10 times or less, preferably 1 μm or less, of the width of a crystal grain formed at the beginning of crystal growth. In other words, since the width is limited to about the same as the crystal grain, only a single (one) crystal grain can pass through the crystallization region 12. Also, the facets of the crystal grains in contact with the amorphous silicon thin film are only one kind among the equivalent {111} planes, and crystal growth (hereinafter also referred to as one-dimensional growth) on this single {111} plane. ). In other words, the facets of the crystal grains move in a one-dimensional direction. Therefore, in the crystallization region 12, the crystal grain at the tip in the growth direction can keep a certain size, and the growth is continued without being disturbed. The entire crystallized region 12 becomes single crystal silicon with very few crystal defects due to favorable epitaxial growth.

The width W1 of the crystallization region 12 refers to the length of the crystallization region 12 in a direction perpendicular to the macroscopic growth direction. The macroscopic growth direction is, in other words, the direction in which the facets of the crystal grains move in the crystallization region 12.

The first region 15 of the pattern 10 further has a preliminary growth region 17 connecting the introduction region 11 and the crystallization region 12. The single or plural crystal grains formed in the introduction region 11 grow toward the crystallization region 12 through the preliminary growth region 17. The width W2 of the pre-growth region 17 at the connection portion 13 with the crystallization region 12 is larger than the width W1 of the crystallization region 12. Thereby, the crystallization region 1
At least one crystal grain can be present in the vicinity of the connection portion 13 between the pre-growth region 17 and the crystallization region 1.
The crystal grains which move in 2 can be secured.

The pattern 10 has a second region 16 connected to the crystallization region 12. The second region 16 includes a two-dimensional growth region 19 and an unnecessary crystallization region connected to the two-dimensional growth region 19. Region 14. The two-dimensional growth area 19 is
This is a region where crystal grains that have grown one-dimensionally in the crystallization region 12 grow two-dimensionally. The unnecessary crystallization region 14 is a region where the tips of crystal growth are gathered, and is a region where the catalyst element is accumulated.

The formation of the pattern 10 may be performed using a normal photolithography method. A photoresist is applied on an amorphous silicon thin film, and prebaking, exposure,
Through each step of photolithography for development, patterning of a predetermined shape is performed.

Note that the first region 15 of the pattern 10 may include only the introduction region 11, and the introduction region 11 may be connected to the crystallization region 12. In this case, the crystallization region 1
The width of the introduction region 11 at the connection with the second region 2 is set to be larger than the width W1 of the crystallization region 12.

(3) Catalyst Element Introducing Step This step is a step of introducing a catalytic element for promoting crystallization of silicon into the introduction region 11 of the amorphous silicon thin film.
First, in order to introduce the catalytic element only into the introduction region 11 of the pattern 10, the amorphous silicon thin film other than the introduction region 11 is protected. As shown in FIG. 4B, a normal pressure CVD method using a SiH ₄ gas and an O ₂ gas was performed on a quartz substrate on which an amorphous silicon thin film pattern was formed.
An SiO ₂ film (not shown) having a thickness of nm is formed. Then, a photoresist (not shown) is applied on the SiO ₂ film (not shown), and the SiO ₂ film 15 covering the rectangular introduction region 11 is formed through the respective steps of pre-baking, exposure and development photolithography. The amorphous silicon thin film in the introduction region 11 is exposed by etching with an etching solution of 10: 1 BHF. A catalyst element is introduced into the exposed introduction region 11 of the amorphous silicon thin film.

In this embodiment, Ni is used as a catalyst element. In addition to Ni, catalyst elements that promote crystallization of the semiconductor include Fe, Co, Ge, Ru, Rh, Pd, and O.
s, Ir, Pt, Cu, Au, In, Sn, Al, Sb
The use of one or two or more elements selected from these elements has the effect of promoting crystallization in a trace amount.

Examples of the method for introducing a catalyst element include sputtering, vapor deposition, plating, ion doping, and CVD.
And a spin coating method. Spin coating is a method in which a solution or dispersion of a catalyst element is applied to a substrate and dried, and the catalyst introduced into the amorphous silicon thin film is adjusted by adjusting the concentration of the catalyst element in the solution or dispersion. The amount of the element can be adjusted.

A solution containing a catalyst element is coated with a solution having a surface concentration of 1 × 10 ¹¹ to 2 × 10 ¹⁶ atoms / cm by spin coating.
^Then, the concentration of the catalytic element in the amorphous silicon film is 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ²¹ atoms / cm 3
It can be about ³ or less. The surface concentration of the catalytic element can be measured by a total reflection X-ray fluorescence (TRXRF) method or the like. The solution containing the catalytic element is
Water, methanol, ethanol, n-propanol, i-
It is preferable to include at least one solvent selected from the group consisting of propanol and acetone.

(4) Step of Forming Crystal Grains This step is a step of forming a compound (silicide) of silicon and a catalyst element and forming crystal grains from silicide. In the crystallization method using a catalytic element, silicide is formed by a reaction between the catalytic element and silicon in a heating step in a state where the catalytic element is introduced.

The heat treatment is performed using an electric furnace under a nitrogen atmosphere, and the heat treatment is performed at a temperature of 550 ° C. to 650 ° C. for 1 hour to 50 hours. Heat treatment is RT
A (rapid thermal annealing) may be used.

For example, disilicide (NiSi ₂ )
Is formed at about 300 ° C. to 400 ° C., and when heated to about 500 ° C. or more, crystal growth starts and crystal grains are formed. NiSi formed at the beginning of the crystal growth
The crystal grain ₂ is an octahedral nucleus, and the diameter of the nucleus is about 10 nm or more and 100 nm or less, for example, 50 nm. The crystal grains formed in the introduction region 11 are adjacent to the pre-growth region 1
The two-dimensionally growing amorphous silicon thin film of No. 7 is crystallized. The fiber grows as the crystal grains move in the amorphous silicon thin film. Among the crystal grains, a particularly thin plate-like one is called a platelet and exists at the tip in the direction in which the fiber grows. This playlet,
It is surrounded by four equivalent {111} planes and cannot grow in the film thickness direction by crystal growth in a thin film. Therefore, three equivalent {111} planes become facets, and the width of the fiber is expanded by facet growth. .

Since the {111} plane of the NiSi ₂ platelet has a low fiber spreading speed, the time until crystal growth stops is long, and the growth distance is long. FIG. 5A
FIG. 3 is a schematic diagram showing the movement of a NiSi ₂ platelet at the tip of a fiber due to crystal growth. As shown in FIG. 5A, the platelet 100 generated in the introduction area 11
Goes toward the crystallization region 12 while crystallizing the amorphous silicon thin film in the adjacent pre-growth region 17. Although FIG. 5A shows a single platelet 100,
A plurality of crystal grains may be grown.

(5) Crystallization Step This step is a step in which a single crystal grain moves in the crystallization region 12 to crystallize the amorphous semiconductor thin film in the crystallization region 12. The playlet 100 is
It moves to the connecting portion 13 between the pre-growth region 17 and the crystallization region 12 while increasing the width (while growing two-dimensionally).
The platelet 100 in the initial stage of crystal growth has a thickness of about several tens of degrees in the growth direction. Size) can be increased to about ten times the initial stage of crystal growth. Since the thickness and width of the crystallized region 12 are 10 times or less the size of the crystal grains formed at the initial stage of crystal growth, only a single (one) crystal grain can pass.

Also, by limiting the thickness and width of the crystallization region 12, the equivalent three-
Facets of only one of the {111} planes are formed. Therefore, as shown in FIGS. 5B and 5C, only one type of facet of the crystal grain moves in the one-dimensional direction, so that crystallization proceeds from the amorphous silicon side 2 to the crystalline silicon side 3 (one-dimensional). growth). Thereby, the two-dimensional growth is eliminated, and the growth can be performed only in the one-dimensional direction at the tip of the growth direction. Becomes

The crystal grains after passing through the crystallization region 12 are as follows:
Since the width of the crystallized region 12 is no longer restricted, the second region 16 (two-dimensional growth region 19
And the unnecessary crystallization region 14) are again two-dimensionally grown.

After the crystallization is completed, the introduction region 11 and the unnecessary crystallization region 14 are removed by etching (see FIG. 4C). This is because nickel causing a leak is accumulated in the introduction region 11 and the unnecessary crystallization region 14. This removal step can also serve as etching when defining the active regions (source and drain regions) of the element (TFT).

Subsequent steps can proceed in the same manner as a normal TFT manufacturing step. Briefly, after depositing a gate insulating film, a film serving as a gate electrode is deposited and processed into a gate shape. Thereafter, n-type or p-type impurities are implanted into the source and drain regions, and the resistance is reduced by activation annealing. After depositing an insulating film, the contact portion 18 is opened (see FIG. 4D), and a wiring film is deposited.
After processing this wiring film, by annealing,
The simplest TFT is completed.

(Embodiment 2) When a transistor for driving a liquid crystal is considered, a constant driving voltage is required. However, even if single crystal silicon is used, a constant driving voltage is required in an extremely miniaturized channel. Often difficult to obtain. However, as shown in FIGS. 6A and 6B, the drive voltage can be ensured by employing the transistor 20 having the double gate structure. That is, the thickness of the semiconductor thin film in the crystallized region 12 serving as a channel is increased, and the gate electrode 21 is in contact with both side surfaces 12a of the semiconductor thin film in the crystallized region 12. In the case of the double gate structure, the thickness D1 of the semiconductor thin film in the crystallization region 12 is
The size is set to 10 times or less, preferably 1 μm or less, of the size of the crystal grains formed in the initial stage of crystal growth. In the present embodiment, 2
The thickness is set to not less than 00 nm and not more than 1 μm. The crystallization region 12
Is required to be 10 times or less, for example, 1 μm or less, of the size of the crystal grains formed in the initial stage of crystal growth. In the present embodiment, the width W1 is 30 nm or more and 1 μm or less. The thinner the width W1 of the crystallization region 12, the more easily the complete depletion type driving by the double gate is performed.

The TFT of the present embodiment is the same as the TFT of the first embodiment.
It can be manufactured in the same manner as T. Briefly referring to FIG. 6B, when nickel is introduced into the nickel introduction region 11 provided outside the source / drain portion and heat treatment is performed, a silicide having a size corresponding to the thickness D1 of the amorphous silicon thin film is obtained. A single or a plurality of grains are formed and grow up to the connection portion 13 between the preliminary growth region 17 and the crystallization region 12. Only a single silicide grain can pass through the crystallized region 12 serving as a channel of the TFT.
Only one type of facet moves in the one-dimensional direction. Complete one-dimensional growth is realized in the crystallization region 12. After passing through the crystallization region 12, the silicide grains pass through the two-dimensional growth region 19 and grow two-dimensionally to the unnecessary crystallization region.

After the crystallization is completed, the introduction region 11 and the unnecessary crystallization region 14 are removed by etching (see FIG. 6B). This removal step can also serve as etching when defining the active regions (source and drain regions) of the element (TFT). Further, after forming the gate insulating film 22, as shown in FIG. 6A, the gate electrode 21 is provided so as to cover both side surfaces 12a of the channel (crystallized region 12). The channel width at this time is twice the film thickness D1 of the channel (crystallized region 12). For example, if the thickness D1 of the channel (crystallized region 12) is 1 μm, the channel width becomes about 2 μm. Note that the width of the channel does not mean the width W1 of the crystallized region 12, but the width of the surface where the channel (crystallized region 12) is in contact with the gate electrode 21 via the gate insulating film 22. As described above, even when the width W1 of the crystallization region is limited to, for example, 1 μm or less, the channel width can be reduced to approximately 2 μm by employing the double gate structure, and the current driving capability can be further improved. It is possible.

(Embodiment 3) TFT 30 of this embodiment
In FIG. 7, the crystallization region is divided into two crystallization regions 121 and 122, as shown in FIG. Each crystallization region 12
The gate electrode 21 is in contact with both side surfaces 121a and 122a of the gate electrodes 1 and 122 via the gate insulating film 22. At this time, the channel width is the thickness D2 of the crystallized regions 121 and 122.
4 times of In this embodiment, the TFTs having a relatively long channel length (the length in the longitudinal direction of the crystallized region overlapping with the gate electrode 21) L1 are also used for the TFTs of the crystallized regions 121 and 12.
2 can be reduced, and the TFT can be made flat. Therefore, manufacturing becomes easy. For example, even if the channel length L1 is designed to be 2 μm, the crystallized region 1 is divided into two portions each having a thickness of 500 nm.
21 and 122, the channel width is 500 nm ×
4 = 2 μm, the ratio of channel length / channel width can be set to 1, and a flat TFT can be manufactured.

As described above, the crystalline semiconductor thin film of the present invention is a high-quality semiconductor thin film having very few crystal defects. Therefore, when a plurality of switching elements are manufactured from the semiconductor thin film of the present invention, the mobility is large. A high-performance semiconductor device having high ON characteristics can be obtained.

In a liquid crystal display device using the semiconductor device of the present invention as a switching element, a clear image in which the occurrence of display unevenness is suppressed can be obtained. The liquid crystal display device includes at least an element substrate having the semiconductor device of the present invention, a counter substrate disposed to face the element substrate, having a counter electrode, and a liquid crystal layer interposed between the element substrate and the counter substrate. Prepare. It is also possible to manufacture a drive circuit from the crystalline semiconductor thin film of the present invention. By forming the switching element and the drive circuit from the semiconductor thin film on the glass substrate, a significant cost reduction, downsizing, and improvement in reliability can be achieved. Can be realized.

[0052]

According to the present invention, high-quality crystallization of an amorphous semiconductor thin film can be realized, and a high-performance semiconductor device (for example, a TFT) can be formed.

[Brief description of the drawings]

FIG. 1A is a perspective view showing the shape of a NiSi ₂ platelet 100 at the tip of a fiber growing on a {100} plane.

FIG. 1B is a schematic diagram showing a change in the shape of a fiber tip surface 1 growing on a {100} plane.

FIG. 2 TE of {100} grown fiber
M is a photograph.

FIG. 3A is a perspective view showing the shape of a NiSi ₂ platelet 100 at the tip of a fiber growing on a {110} plane.

FIG. 3B is a schematic diagram showing a change in the shape of the fiber tip surface 1 growing on a {110} plane.

FIG. 4 is a plan view illustrating a manufacturing process of the crystalline semiconductor thin film of the first embodiment.

FIG. 5A: NiSi ₂ at the fiber tip by crystal growth
FIG. 3 is a schematic diagram showing movement of a platelet 100.

5B is a perspective view schematically showing the NiSi ₂ platelet 100 moving in the crystallization region 12. FIG.

5C is a perspective view schematically showing the NiSi ₂ platelet 100 moving in the crystallization region 12. FIG.

FIG. 6A is a perspective view showing a TFT according to a second embodiment.

FIG. 6B is a perspective view schematically showing a state during crystallization according to the second embodiment.

FIG. 7 is a perspective view showing a TFT according to a third embodiment.

[Explanation of symbols]

 Reference Signs List 10 pattern 11 introduction region 12, 121, 122 crystallization region 15 first region 17 pre-growth region W1 width of crystallization region D1, D2 film thickness 12a, 121a, 122a side surface of channel region 21 gate electrode 100 platelet (crystal grain) )

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI theme coat ゛ (Reference) H01L 29/78 617N 618C F-term (Reference) 2H092 JA24 JA35 JA37 JA41 KA05 MA02 MA04 MA05 MA08 MA12 MA29 NA21 NA22 NA24 NA29 5F052 AA11 AA17 AA24 CA04 DA02 DB03 DB07 FA06 FA07 JA01 5F110 AA30 BB01 BB07 BB11 CC10 DD03 DD13 EE30 GG01 GG02 GG03 GG13 GG17 GG24 GG25 GG29 GG43 GG45 HJ23 PP01 PP02 PP10 PP23 PP34 PP36

Claims (8)

[Claims] A catalyst element for promoting crystallization of the amorphous semiconductor thin film is introduced into the amorphous semiconductor thin film formed on the substrate, and crystal grains are formed from the semiconductor and the catalyst element; A method for manufacturing a crystalline semiconductor thin film, wherein the amorphous semiconductor thin film is crystallized by moving the crystal grains, wherein the step of forming the amorphous semiconductor thin film on the substrate; A first region including an introduction region to be introduced;
Forming the amorphous semiconductor thin film in a pattern having at least a crystallization region connected to the first region; introducing the catalyst element into the introduction region; and introducing the catalyst element into the introduction region. Heating the catalyst element to form at least a single crystal grain, and crystallizing the amorphous semiconductor thin film in the crystallization region by moving the single crystal grain; Wherein the thickness and width of the crystallized region are not more than 10 times the size of the crystal grain formed at the beginning of crystal growth, and the tip of the single crystal grain moving in the crystallized region A facet of only one of the equivalent {111} faces is formed, and the amorphous semiconductor thin film is crystallized by moving the facet in a one-dimensional direction. Thin film Manufacturing method. 2. The thickness and width of the crystallized region are 1 μm.
The method for producing a crystalline semiconductor thin film according to claim 1, wherein the method is as follows. 3. The first region of the pattern further includes a pre-growth region connecting the introduction region and the crystallization region, and a width of the pre-growth region at a connection with the crystallization region is 2. The manufacturing method of the crystalline semiconductor thin film according to claim 1, wherein the crystal grains formed in the introduction region are larger than a width of the crystallization region and travel toward the crystallization region through the pre-growth region. Method. 4. The amorphous semiconductor thin film is formed by moving crystal grains formed from a catalyst element promoting the crystallization of the amorphous semiconductor thin film and the semiconductor in the amorphous semiconductor thin film. A crystallized crystalline semiconductor thin film, wherein a facet of only one of the equivalent {111} faces is formed at a tip of the crystal grain, and the facet moves in a one-dimensional direction. A crystalline semiconductor thin film obtained by crystallizing the amorphous semiconductor thin film. 5. The crystallized region in which the facet moves in a one-dimensional direction has a film thickness and a width that are 10 times or less the size of the crystal grains formed at an early stage of crystal growth. Crystalline semiconductor thin film. 6. A semiconductor device comprising the crystalline semiconductor thin film according to claim 4. 7. A channel region comprising the crystalline semiconductor thin film according to claim 4 or 5, wherein a gate electrode contacts both side surfaces of the crystalline semiconductor thin film in the channel region.
Thin film transistor. 8. A liquid crystal display device including the semiconductor device according to claim 6.