JP2002280300A - Manufacturing method of semiconductor thin film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor thin film of crystal grain having proper crystallinity. SOLUTION: A growth source region 2, a target region 3 provided away from it, an amorphous silicon path 4, which made of one bent part 4a, connects the growth source region 2 to the target region 3, and a peripheral amorphous silicon region 5 which encloses the growth source region 2, amorphous silicon path 4, and target region 3, are formed by patterning an amorphous silicon film. Nickel is added to only the surface of the growth source region 2 using a mask, which is heated in an electric furnace, so that the crystal grain generated in the growth source region 2 crystallizes into the target region 3. Then, the target region 3 and the peripheral amorphous silicon region 5 are irradiated with a laser beam, so that the crystal grain of the target region 3 is made to melt and recrystallize.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor thin film formed on a substrate having an insulating surface, and more particularly, to forming an amorphous silicon film on a substrate having an insulating surface. The present invention relates to a method of manufacturing a semiconductor thin film by applying energy such as heat, light, or charged particles to an amorphous silicon film to obtain a crystalline semiconductor thin film.

[0002]

2. Description of the Related Art In recent years, thin film transistors (hereinafter referred to as TFTs) have been developed.
) Is attracting attention. According to the method of manufacturing a thin film semiconductor element, a semiconductor thin film having a thickness of several tens nm to several hundreds nm is formed on a substrate having an insulating surface by a CVD method or the like, and the semiconductor thin film is used as an active layer to form an insulated gate field effect semiconductor device or a diode. And so on. As an application field of the semiconductor thin film, an active matrix type liquid crystal electro-optical device is known. In this technique, one or more TFTs are arranged on each of several hundred thousand or more pixel electrodes arranged in a matrix, and electric charges supplied to the pixel electrodes are controlled by the TFTs.

As a semiconductor thin film used for a TFT,
Although it is simple to use an amorphous silicon film, there is a problem that electrical characteristics such as low mobility are low. TFT
In order to improve the characteristics, a silicon thin film having crystallinity may be used. A crystalline silicon film is called polycrystalline silicon, microcrystalline silicon, or the like. In order to obtain a silicon film having this crystallinity, an amorphous silicon film is first formed, and then crystallized by applying energy.

In Japanese Patent Application Laid-Open No. 6-244103, a catalyst for promoting crystallization of silicon is added to the surface of an amorphous silicon film, and then the amorphous silicon film is crystallized by annealing. A method for obtaining rubber has been proposed. However, in the method proposed in Japanese Patent Application Laid-Open No. 6-244103, crystallization occurs at an arbitrary position on the surface of the amorphous silicon film. It is inevitable that a plurality of crystal grain boundaries are arranged in the layer. In the electrical characteristics of a TFT in which an active layer is formed at a boundary between a plurality of crystal grains, problems such as low mobility and large off current occur, and the TFT is substantially manufactured by the method disclosed in JP-A-6-244103. It is difficult to fabricate a TFT having good electrical characteristics and small variation in characteristics with the manufactured crystallized silicon film.

[0005] 1999 United States Material Research Societ
y (MRS) At the Spring Meeting (A18.6), the catalyst addition region and the transistor fabrication region were separated by patterning, and the two regions were connected by an amorphous silicon path with two bends. It was announced that it was possible to make a single crystal grain grow into a region. That is, the crystal grains that grow at the two bent portions are selected as one, and grow into the transistor fabrication region, and the other crystal grains cannot pass through the path.

[0006]

In order to increase the density of a semiconductor device and stabilize the electrical characteristics of the device, it is essential to manufacture a TFT in a single crystal grain. Further, in order to improve the TFT characteristics, an amorphous silicon film is crystallized using a catalyst which promotes crystallization of silicon, and then energy is applied by excimer laser irradiation or the like.
What is necessary is just to perform a melting recrystallization process, maintaining the state of a single crystal grain.

[0007] The amorphous silicon thin film on the insulating transparent substrate is patterned into a shape as disclosed in the US MRS, a catalyst for promoting crystallization of silicon is added, and a crystallization annealing treatment is performed. The fabrication region can be a single crystal grain.

However, even when the silicon thin film is formed on a transparent substrate and patterned into a shape as disclosed in the above-mentioned MRS, and the patterned silicon thin film is irradiated with an excimer laser, the patterned silicon thin film can be patterned. Since the periphery of the silicon thin film is transparent, laser light of a wavelength that is generally used is hardly absorbed by materials other than the silicon thin film. It is difficult to convert. Therefore, if the energy density is increased, it becomes possible to melt silicon, but since the temperature rise rate and the temperature fall rate are different between the central portion and the edge portion of the patterned silicon thin film, the crystallinity is significantly different depending on the position. Depending on the laser irradiation conditions, the film thickness differs between the edge portion and the center portion.

Further, in order to simplify the manufacturing process, the treatment for removing the catalyst which promotes the crystallization of silicon is not performed.
If laser irradiation is performed while the catalyst remains in the silicon thin film, the catalyst moves in the transistor fabrication region and aggregates at a high concentration anywhere in the transistor fabrication region. Aggregation at a high concentration may significantly reduce TFT electrical characteristics.

As described above, as a result of the research by the inventor, it is possible to fabricate a TFT within a single crystal grain by using an amorphous silicon film patterned into a shape as described in the US MRS. However, it has been found that there is a problem that crystal grains having good crystallinity cannot be obtained even if energy applying treatment such as laser irradiation is performed to obtain better crystal grains.

An object of the present invention is to provide a method of manufacturing a semiconductor thin film capable of obtaining crystal grains having good crystallinity.

[0012]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor thin film according to the present invention comprises the steps of: forming an amorphous silicon film on a substrate having an insulating surface; A source region, a target region which is isolated from the growth source region and to which no catalyst is added, and to which crystal grains generated in the growth source region are to be directed, and the growth source region and the target region. An interconnecting amorphous silicon pathway;
Patterning the amorphous silicon film by surrounding the target region with a gap therebetween and forming a surrounding amorphous silicon region not connected to the target region; A step of adding a catalyst that promotes crystallization of crystalline silicon, and applying a first energy to the growth source region, thereby causing crystal grains generated in the growth source region to pass through the amorphous silicon path. Crystal growth in the target region by applying second energy to the target region and the surrounding amorphous silicon region to melt and recrystallize crystal grains grown in the target region. And characterized in that:

[0013] In the method of manufacturing a semiconductor thin film having the above-described structure, by applying a first energy to the growth source region,
Crystal grains generated in the growth source region are grown on the target region via the amorphous silicon path. Then, by applying a second energy to the target region and the surrounding amorphous silicon region, the crystal grains grown in the target region are melted and recrystallized. At this time, the surrounding amorphous silicon region surrounds the target region with a gap therebetween, so that the temperature rising rate and the temperature decreasing rate of each part of the target region become uniform. As described above, since the melt recrystallization process is performed on the crystal grains in the target region in a state where the temperature rising rate and the temperature decreasing rate of each part of the target region are uniform, good crystal grains can be obtained. Moreover, the thickness of each part of the crystal grains can be made uniform.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor thin film, comprising the steps of: forming an amorphous silicon film on a substrate having an insulating surface; A target region to which crystallites generated in the growth source region should be directed, and an amorphous region connecting the growth source region and the target region. Surrounding the silicon path with a gap with respect to most of the target area, and
Forming a peripheral amorphous silicon region connected to a part of the target region by patterning the amorphous silicon film, and promoting crystallization of the amorphous silicon only in the growth source region. Adding a catalyst to the growth source region and applying a first energy to the growth source region to grow crystal grains generated in the growth source region on the target region through the amorphous silicon path. And a step of applying second energy to the target region and the surrounding amorphous silicon region to recrystallize crystal grains grown in the target region.

[0015] In the method of manufacturing a semiconductor thin film having the above structure, the first energy is applied to the growth source region.
Crystal grains generated in the growth source region are grown on the target region via the amorphous silicon path. Then, by applying a second energy to the target region and the surrounding amorphous silicon region, crystal grains grown in the target region are recrystallized. At this time, since the surrounding amorphous silicon region surrounds most of the target region with a gap, the temperature rising rate and the temperature decreasing rate of each part of the target region become uniform. As described above, since the melt recrystallization process is performed on the crystal grains in the target region in a state where the temperature rising rate and the temperature decreasing rate of each part of the target region are uniform, good crystal grains can be obtained. Moreover, the thickness of each part of the crystal grains can be made uniform.

Further, since a part of the target region is connected to the surrounding amorphous silicon region, the catalyst diffuses from the target region to the surrounding amorphous silicon region, and a catalyst that deteriorates the TFT characteristics is required. It can be prevented from remaining in the target area.

Also, by connecting a part of the target region and the surrounding amorphous silicon region, the effect of widening the range of energy application conditions for making the temperature rise rate and the temperature decrease rate uniform in each part of the target region was also confirmed. Have been.

In one embodiment of the present invention, an end of the target region opposite to the amorphous silicon path is connected to the surrounding amorphous silicon region.

The method for manufacturing a semiconductor thin film according to the above embodiment is as follows.
Promoting crystal growth in the target region with a catalyst,
In addition, from the viewpoint that a catalyst that deteriorates TFT characteristics is not left in the target region, it is preferable that the end of the target region opposite to the amorphous silicon path be connected to the surrounding amorphous silicon region.

In one embodiment of the present invention, a method of manufacturing a semiconductor thin film includes the steps of: forming an element forming region located on the side of the amorphous silicon path in the target region; The distance between them is 30 μm or more and 100 μm or less.

According to the method of manufacturing a semiconductor thin film of the above embodiment, when the distance between the element formation region included in the target region and the end of the target region opposite to the amorphous silicon path is smaller than 30 μm, the catalyst Is diffused into the surrounding amorphous silicon region more than necessary, and the amount of catalyst in the target region becomes too small, and it becomes difficult to promote crystallization of all the necessary regions. On the other hand, if the distance between the element formation region included in the target region and the end of the target region opposite to the amorphous silicon path is larger than 100 μm, after the second energy is applied, the catalyst will be in the element formation region of the target region. The high concentration is contained in the region other than the region, and the catalyst that deteriorates the TFT characteristics does not remain in the element formation region. Therefore, the effect of connecting a part of the target region, the surrounding amorphous silicon region, and the end of the element forming region is substantially eliminated. That is, even if a part of the target region is not connected to the surrounding amorphous silicon region, a catalyst that deteriorates the TFT characteristics does not remain in the element formation region. As described above, when a part of the target region is connected to the surrounding amorphous silicon region, the distance between the element forming region included in the target region and the end of the target region opposite to the amorphous silicon path is set to 100 μm.
If it is larger than m, the target area becomes unnecessarily large, which increases the manufacturing cost.

Therefore, when a part of the target region is connected to the surrounding amorphous silicon region, an element forming region located on the amorphous silicon path side in the target region;
The distance between the amorphous silicon path and the opposite end in the target region is preferably 30 μm or more and 100 μm or less.

In one embodiment of the present invention, the gap between the target region and the surrounding amorphous silicon region is 0.1 μm or more and 20 μm or less.

According to the method of manufacturing a semiconductor thin film of the above embodiment, when the gap between the target region and the peripheral amorphous silicon region is smaller than 0.1 μm, the target region and the peripheral amorphous silicon region are formed. Is very difficult to perform. On the other hand, if the gap between the target region and the surrounding amorphous silicon region is larger than 20 μm, it is very difficult to make the temperature rising rate and the temperature decreasing rate of each part of the target region uniform when the second energy is applied. Therefore, it is difficult to obtain good crystal grains. Therefore, the gap between the target region and the surrounding amorphous silicon region is preferably 0.1 μm or more and 20 μm or less.

In one embodiment of the present invention, the amorphous silicon path has at least one bent portion.

According to the method of manufacturing a semiconductor thin film of the embodiment, crystal grains generated in the growth source region grow from the growth source region to the target region via the amorphous silicon path. At this time, only the crystal grain that has reached the bent portion earliest is selected and occupies the amorphous silicon path after the bent portion. Therefore, the crystal grains to be grown from the growth source area to the target area can be selected individually by passing through the bent portion, so that the target area can be completely composed of a single crystal grain.

In one embodiment of the method of manufacturing a semiconductor thin film, the catalyst is Fe, Co, Ni, Ge, Ru, Rh, P
At least one element among d, Os, Ir, Pt, Cu, Au and Ge.

According to the method of manufacturing a semiconductor thin film of the embodiment, the catalyst may be Fe, Co, Ni, Ge, R
When at least one of u, Rh, Pd, Os, Ir, Pt, Cu, Au and Ge is used, crystallization of amorphous silicon can be effectively promoted.

In one embodiment of the present invention, a method of manufacturing a semiconductor thin film includes adding at least one of the silicon nitride film, the silicon oxide film, and the silicon carbide film to add the catalyst only to the growth source region.
A step of forming a mask having a thickness of 50 nm or more of different types on the surface of the region other than the growth source region.

According to the method of manufacturing a semiconductor thin film of the above embodiment, a mask of at least one of a silicon nitride film, a silicon oxide film and a silicon carbide film having a thickness of 50 nm or more is formed on the surface of the region other than the growth source region. Form. Thereafter, a catalyst is added only to the growth source region, and a first energy is applied to the growth source region. At this time, the mask is made of at least one of a silicon nitride film, a silicon oxide film, and a silicon carbide film, and has a thickness of 50 nm or more. Do not reach the area other than the area. That is, it is possible to prevent the catalyst on the mask from contaminating regions other than the growth source region.

The mask is in direct contact with the target region, but does not contain impurities or the like that adversely affect the TFT characteristics. Therefore, even if a TFT is manufactured using the target region, the TFT characteristics do not deteriorate.

In one embodiment of the present invention, when the catalyst is added to the surface of the growth source region, the surface concentration of the catalyst in the growth source region is 1 × 10 ¹¹ a.
toms / cm ² or more 1 × ¹⁰ 16 atoms / cm ²
It is as follows.

According to the method of manufacturing a semiconductor thin film of the embodiment, when the catalyst is added to the surface of the growth source region by, for example, a sputter deposition method or application of a chemical solution, the surface concentration of the catalyst in the growth source region is 1 × 10 5 Control is performed so as to be in a range of ¹¹ atoms / cm ² or more and 1 × 10 ¹⁶ atoms / cm ² or less. When the surface concentration of the catalyst is 1 × 10 ¹¹ at
If it is less than oms / cm ² , crystal growth is very unlikely or does not occur at all. On the other hand, when the surface concentration of the catalyst is 1
If it exceeds × 10 ¹⁶ atoms / cm ² , a large amount of the catalyst remains in the crystallized silicon, so that it is difficult to remove the catalyst from the silicon after crystallization, and the time required for the removal is low. It becomes longer, which is not preferable as a manufacturing process.

Therefore, when the catalyst is added to the surface of the growth source region, the surface concentration of the catalyst in the growth source region is set to 1 × 10 ¹¹ atoms / cm ² or more and 1 × 10 ¹⁶ at.
oms / cm ² or less.

In one embodiment of the present invention, when the catalyst is injected into the growth source region, the concentration of the catalyst in the growth source region is 2 × 10 ¹⁶ atoms.
/ Cm ³ or more and 2 × 10 ²¹ atoms / cm ³ or less.

According to the method of manufacturing a semiconductor thin film of the embodiment, when the catalyst is injected into the growth source region by, for example, an ion implantation method, the concentration of the catalyst in the growth source region becomes 2%.
× 10 ¹⁶ atoms / cm ³ or more 2 × 10 ²¹ atoms
Control is performed so as to be in the range of ms / cm ³ or less. When the concentration of the catalyst is lower than 2 × 10 ¹⁶ atoms / cm ³ , crystal growth is very unlikely to occur or does not occur at all. On the other hand, when the concentration of the catalyst is 2 × 10 ²¹ atom
If it is higher than ms / cm ³ , a large amount of the catalyst remains in the crystallized silicon, so that it is difficult to remove the catalyst from the silicon after crystallization, and the time required for the removal becomes long. It is not preferable as a manufacturing process.

Therefore, the catalyst is injected into the growth source region.
, The concentration of the catalyst in the growth source region is 2 × 10
¹⁶atoms / cm³More than 2 × 10²¹atoms /
cm ³It is preferable to set the following.

In one embodiment of the method of manufacturing a semiconductor thin film, the application of the first energy is performed using an electric furnace at 400 ° C. or more and 800 ° C. or less.

According to the method of manufacturing a semiconductor thin film of the embodiment, after the catalyst is added only to the growth source region, first energy such as heat, light, or charged particles is applied to the growth source region. Thus, crystal grains generated in the growth source region are grown to the target region via the amorphous silicon path. At this time, when the first energy is applied using an electric furnace, the set temperature of the electric furnace is set to 400.
If the temperature is lower than 0 ° C., the crystallization rate becomes extremely slow, which is not preferable as a production process. On the other hand, when the set temperature of the electric furnace is higher than 800 ° C., a large number of crystal grains not depending on the catalyst are generated at any place other than the growth source region. Therefore, many microcrystalline silicon films are formed in the target region. A TFT manufactured using the microcrystalline silicon film in the target region has poor electrical characteristics such as low mobility.

Therefore, when the first energy is applied using an electric furnace, the set temperature of the electric furnace is 4
It is preferable that the temperature is not lower than 00 ° C and not higher than 800 ° C.

In one embodiment of the present invention, the application of the second energy is performed by laser irradiation.

According to the method of manufacturing a semiconductor thin film of the above embodiment, after the crystal growth by the first energy application, the second energy application is performed for melt recrystallization. This second energy application is performed, for example, at a wavelength of 400 n.
Irradiation with an excimer laser of m or less is simple and preferable. The energy density of this laser irradiation cannot be mentioned because the optimum value varies depending on the film thickness of the target region, but if the film thickness of the target region is in the range of 10 nm to 200 nm, it is 250 mJ / cm ^{2 to} 400 mJ / cm.
It is often in the range of ² . By providing the surrounding amorphous silicon region, the energy absorption efficiency of the target region is good, and the rate of temperature rise and fall of each part of the target region is uniform, but if the second energy is too small. In addition, melting and recrystallization do not occur, and even if a TFT is manufactured using the target region, the TFT characteristics are not improved. On the other hand, if the second energy is too large, the first energy
A single crystal grain obtained by the application of the energy is completely melted to produce fine polycrystalline silicon. Even if a TFT is manufactured using this fine polycrystalline silicon, the TFT characteristics are significantly reduced.

[0043]

(First Embodiment) FIG. 1 (a)
2A to 2C are process diagrams of a method for manufacturing a semiconductor thin film according to the first embodiment of the present invention, and FIG. 2 is a schematic plan view showing one process of the method for manufacturing a semiconductor thin film.

Hereinafter, a method of manufacturing the semiconductor thin film according to the first embodiment will be described.

First, as shown in FIG. 1A, an amorphous silicon film having a thickness of, for example, 50 nm is formed on a quartz substrate 1 as a substrate having an insulating surface by a low-pressure CVD method using Si ₂ H ₆ gas. The film 100 is laminated.

Next, with respect to the amorphous silicon film 100,
Normal photo processes of resist application, exposure, and development are sequentially performed to pattern the amorphous silicon film 100.
As shown in (b), a patterned amorphous silicon film 101 is formed on the substrate 1. As shown in FIG. 2, the patterned amorphous silicon film 101 includes a growth source region 2, a target region 3 isolated from the growth source region 2, a growth source region 2 and a target region 3. And an amorphous silicon path 4 having one bent portion 4a, a growth source region 2, an amorphous silicon path 4 and a target region 3
And surrounding amorphous silicon region 5. The surrounding amorphous silicon region 5 has a gap between each of the growth source region 2, the amorphous silicon path 4 and the target region 3, and the growth source region 2, the amorphous silicon path 4 and It is not connected to any of the target areas 3.

The growth source region 2 is a region to which a catalyst for promoting crystallization of silicon is to be added, and a region where crystal nuclei are generated by applying the first energy, and is, for example, 10 μm × 10 μm. It's square.

The target region 3 is a region in which crystal grains generated in the growth source region 2 are to be directed via the amorphous silicon path 4, and has a rectangular shape of, for example, 10 μm × 150 μm. The gap between target region 3 and surrounding amorphous silicon region 5 is set to 1 μm. The end of the target region 3 on the side of the amorphous silicon path 4 is, for example, an element forming region 3a for actually forming a transistor. The element forming region 3a is a portion from the junction between the target region 3 and the amorphous silicon path 4 (the end 3b of the target region 3 on the amorphous silicon path 4 side) to the dotted line in FIG. The length from the end 3b of the target region 3 on the amorphous silicon path 4 side to the dotted line in FIG.
m. That is, L1 in FIG. 2 is 30 μm. The distance from the end (dotted line in FIG. 2) of the element formation region 3a opposite to the amorphous silicon path 4 to the end 3c of the target region 3 opposite to the amorphous silicon path 4 is 120 μm. I have. That is, L2 in FIG.
0 μm.

The amorphous silicon path 4 has a path width of, for example, 8 μm and extends from the growth source region 2 to the target region 3. In the amorphous silicon path 4, the length Lb from the end of the growth source region 2 on the side of the amorphous silicon path 4 to the bent portion 4 a is 15 μm.
a to end 3b of target region 3 on the side of amorphous silicon path 4
The length Ld up to this is 8 μm.

Next, on the quartz substrate 1 and the patterned amorphous silicon film 101, an S
A 200 nm SiO ₂ film is deposited using iH ₄ gas and O ₂ gas. Then, a photo process of resist application, exposure, and development is performed on the SiO ₂ film, thereby forming a mask 103 having a thickness of, for example, 200 nm as shown in FIG. The mask 203 has a square opening (a so-called catalyst addition window) 7 of 9 μm × 9 μm. Thereby, only a part of the growth source region 2 is exposed from the opening 7. In the development, for example, 10: 1 BHF
(Buffered hydrofluoric acid) for etching.

Next, nickel (N) as a catalyst is deposited on the surface of the growth source region 2 through the opening 7 by sputtering.
i) is vapor-deposited so that the surface concentration of nickel in the growth source region 2 is 1 × 10 ¹³ atms / cm ² . At this time, the surface of the region other than the exposed growth source region 2 is masked.
3 is covered, the catalyst is added only to the exposed surface of the growth source region 2.

Thereafter, in order to apply heat as the first energy to the growth source region 2, a heat treatment at, eg, 600 ° C. is performed in a nitrogen atmosphere using an electric furnace. Then, a plurality of crystal grains are generated in the growth source region 2, and some of them near the amorphous silicon path 4 grow toward the bent portion 4 a. At this time, the crystal grain that has reached the bent portion 4a earliest occupies the amorphous silicon path 4 after the bent portion 4a. This allows only a single grain to
It passes through the bent portion 4 a and grows to the target region 3. When the heat treatment is performed for 3 hours, the target region 3 is crystallized from the end 3b on the side of the amorphous silicon path 4 to a position of about 60 μm in the longitudinal direction.

After the heat treatment, XeCl (xenon) having a wavelength of 308 nm and an energy density of 350 mJ / cm ² is applied to irradiate the target region 3 and the surrounding amorphous silicon region 5 with a laser beam as the second energy. Chlorine) excimer laser is used. When excimer laser irradiation by this XeCl excimer laser is performed, the surrounding amorphous silicon region 5 surrounds the target region 3 with a gap therebetween, so that the vicinity of the interface between the target region 3 and the quartz substrate 1 in the target region 3 Heating rate other than
The high temperature rate becomes uniform, melt recrystallization occurs and single grains are obtained.

As described above, in a state where the rate of temperature rise and the rate of high temperature are uniform except for the vicinity of the interface between the target region 3 and the quartz substrate 1 in the target region 3, a single crystal grain of the target region 3 is removed. Since the melt recrystallization treatment is performed, good single crystal grains can be obtained, and the thickness of each part of the crystal grains can be made uniform.

Further, from the end (dotted line in FIG. 2) of the element forming region 3a opposite to the amorphous silicon path 4, the end 3 of the target region 3 opposite to the amorphous silicon path 4 is formed.
Since the length L2 up to c is 120 μm, after irradiation with an excimer laser for melting and recrystallization, nickel as a catalyst is contained in a high concentration in a region other than the element formation region 3a of the target region 3. And does not remain in the nickel element formation region 3a so as to deteriorate the TFT characteristics.

The target area 3 is 10 μm ×
Since the area is as large as 150 μm, the energy absorption efficiency of the target region 3 is improved at the time of excimer laser irradiation for melt recrystallization. Accordingly, it is possible to widen the range of the energy application condition in which the temperature rising rate and the temperature falling rate of each part of the target region 3 are made uniform.

Although the quartz substrate 1 is used in the first embodiment, any other substrate having an insulating surface may be used.

The gap between the target region 3 and the surrounding amorphous silicon region 5 was 1 μm, but was 0.1 μm.
It may be within the range of not less than μm and not more than 20 μm.

Although the amorphous silicon path 4 has one bent portion 4a, it may have a plurality of bent portions. Further, the amorphous silicon path 4 may not have a bent portion. In this case, the target region 3 can be composed of a single crystal grain by making the path width of the amorphous silicon path 4 extremely narrow.

As a catalyst for promoting crystallization of amorphous silicon, Fe, Co, Ni, Ge, Ru, Rh, Pd,
At least one element of Os, Ir, Pt, Cu, Au and Ge may be used. By using at least one of these elements, crystallization of amorphous silicon can be effectively promoted.

Although the mask 103 made of the SiO ₂ film is used, a mask made of at least one of a silicon nitride film, a silicon oxide film, and a silicon carbide film may be used.
Although the film thickness of the mask 103 was 200 nm,
nm or more.

The surface concentration of nickel in the growth source region 2 was 1 × 10 ¹³ atoms / cm ² , but 1 × 10 ¹¹ atoms / cm ² or more and 1 × 10 ¹⁶ or more.
It may be within the range of atoms / cm ² or less.

Although the catalyst has been added to the surface of the growth source region 2, the catalyst may be injected into the growth source region 2 by using, for example, an ion implantation method. In this case, the concentration of the catalyst in the growth source region 2 is 2 × 10 ¹⁶ atoms / c.
It may be in the range of m ³ or more and 2 × 10 ²¹ atoms / cm ³ or less.

The temperature of the electric furnace is 600 ° C., but may be in the range of 400 ° C. to 800 ° C.

The growth source region 2 may be irradiated with, for example, light, an ion beam, an electron beam, or the like to generate crystal grains in the growth source region 2.

Further, a single crystal grain in the target region 3 is irradiated with laser light to melt and recrystallize the crystal grain. The crystal grains may be melted and recrystallized by irradiation with a beam or an electron beam.

(Second Embodiment) FIGS. 3A to 3C
FIG. 4 is a process diagram of a method for manufacturing a semiconductor thin film according to a second embodiment of the present invention, and FIG. 2 is a schematic plan view of one process of the method for manufacturing a semiconductor thin film.

Hereinafter, a method for manufacturing a semiconductor thin film according to the second embodiment will be described.

First, as shown in FIG. 3A, a 50 nm-thick amorphous silicon film is formed on a quartz substrate 21 as a substrate having an insulating surface by a low pressure CVD method using Si ₂ H ₆ gas. The film 200 is laminated.

Next, with respect to the amorphous silicon film 200,
Normal photo steps of resist application, exposure, and development are sequentially performed to pattern the amorphous silicon film 200.
As shown in (b), a patterned amorphous silicon film 201 is formed on the substrate 21. As shown in FIG. 4, the patterned amorphous silicon film 201 includes a growth source region 22, a target region 23 isolated from the growth source region 22, a growth source region 22, and a target region 23. And the surrounding amorphous silicon region 2 surrounding the growth source region 22, the amorphous silicon passage 24 and the target region 23.
5 is comprised. This surrounding amorphous silicon region 25
Has a gap with respect to each of the growth source region 22 and the amorphous silicon path 24, and is not connected to the growth source region 22 and the amorphous silicon path 24. The surrounding amorphous silicon region 25 has a gap with respect to most of the target region 23, and is connected to a part of the target region 23. Specifically, the target area 23
Is connected to the surrounding amorphous silicon region 25 only at the end 23c opposite to the amorphous silicon path 24.

The growth source region 22 is a region to which a catalyst for promoting crystallization of silicon is to be added, and a region where crystal nuclei are generated by applying first energy.
For example, it is a square of 10 μm × 10 μm.

The target region 23 is a growth source region 2
2 is a region where crystal grains generated in Step 2 are to be directed via the amorphous silicon path 24, and has a rectangular shape of, for example, 10 μm × 60 μm. The gap between target region 23 and surrounding amorphous silicon region 25 is set to 2 μm. The end of the target region 23 on the side of the amorphous silicon path 24 is used, for example, as an element formation region 23a for actually forming a transistor. This element formation region 23a is formed by the target region 23 and the amorphous silicon path 2.
4 (the amorphous silicon path 2 in the target region 23).
4 to the dotted line in FIG. 4.
End 2 of this target region 23 on the amorphous silicon path 24 side
The length from 3b to the dotted line in FIG. 4 is 25 μm. That is, L21 in FIG. 4 is 25 μm. Also,
From the end (dotted line in FIG. 4) of the element forming region 23a opposite to the amorphous silicon path 24, the target region 23
Is 35 μm up to the end 23 c opposite to the amorphous silicon path 24 in FIG. That is, L22 in FIG.
μm.

The amorphous silicon path 24 is, for example, 5 μm
From the growth source region 2 to the target region 2
It extends to three. In the amorphous silicon channel 24, the length Lb from the end of the growth source region 22 on the amorphous silicon channel 24 side to the bent portion 24a is 10 μm. The length Ld up to the end 23b on the side of the amorphous silicon path 24 is 5 μm.

Next, a 200 nm thick SiO ₂ film is formed on the quartz substrate 21 and the patterned amorphous silicon film 201 by a normal pressure CVD method using SiH ₄ gas and O ₂ gas.
accumulate. Then, a photo process of resist application, exposure, and development is performed on the SiO ₂ film to form a mask 203 having a thickness of, for example, 200 nm, as shown in FIG. The mask 203 has a 9 μm × 9 μm square opening (a so-called catalyst addition window) 27. As a result, only a part of the growth source region 22 is exposed from the opening 27. In the development, for example, 10:
Etching is performed using 1BHF.

Next, nickel as a catalyst is ion-implanted from above the mask 203 into the growth source region 22. Specifically, 1 × 10 ¹⁵ ions / cm ² of Ni ⁺ is implanted into the growth source region 22 at an acceleration energy of 50 keV. At this time, since the region other than the exposed growth source region 22 is covered with the mask 203, N ⁺ does not reach the region other than the growth source region 22, and as a result, Ni ⁺ is contained only in the growth source region 22. It has been injected. The ion implantation is performed when the nickel concentration in the growth source region 22 is 2 × 10 ¹⁶ a.
It is performed so that the density is not less than toms / cm ^{3 and not} more than 2 × 10 ²¹ atoms / cm ³ .

Thereafter, in order to apply heat as the first energy to the growth source region 22, a heat treatment at, eg, 580 ° C. is performed in a nitrogen atmosphere using an electric furnace. Then, a plurality of crystal grains are generated in the growth source region 22, and some of them near the amorphous silicon path 24 grow crystal toward the bent portion 24a. At this time, the crystal grain that has reached the bent portion 24a earliest occupies the amorphous silicon path 24 after the bent portion 24a. As a result, only a single crystal grain passes through the bent portion 24 a and grows into the target region 23. Then, when the heat treatment is performed for 10 hours, the entire target region 23 is crystallized. That is, the target region 23 is composed of a single crystal grain. According to observations made by the present inventors, the crystallization ended at the end 23c of the target region 23 opposite to the amorphous silicon path 24, and the surrounding amorphous silicon region 25 remained amorphous. This is because nickel, which is a catalyst, rapidly diffused from the target region 23 into the peripheral amorphous silicon region 25 having a large area, so that the nickel concentration required to promote crystallization in the peripheral amorphous silicon region 25 was reduced. Because they couldn't keep it. Further, since nickel diffused into the surrounding amorphous silicon region 25, TF
Nickel does not remain enough to deteriorate the T characteristic.

After the heat treatment, the target region 23 and the surrounding amorphous silicon region 25 are irradiated with a laser beam as the second energy to have a wavelength of 308 nm.
A XeCl excimer laser having an energy density of 350 mJ / cm ² is used. When excimer laser irradiation by the XeCl excimer laser is performed, since the surrounding amorphous silicon region 25 surrounds most of the target region 23 with a gap, the target region 23 and the quartz The rate of temperature rise and the rate of high temperature other than near the interface with the substrate 21 become uniform, and melting and recrystallization occur, thereby obtaining a single crystal grain.

As described above, a single crystal grain of the target region 23 is formed in the target region 23 in a state where the heating rate and the high temperature rate are uniform except for the vicinity of the interface between the target region 23 and the quartz substrate 21. Since the melt recrystallization treatment is performed, good single crystal grains can be obtained, and the thickness of each part of the crystal grains can be made uniform.

The end 23c of the target region 23
Is connected to the surrounding amorphous silicon region 25, nickel serving as a catalyst diffuses from the target region 23 to the surrounding amorphous silicon region 25, and nickel enough to deteriorate the TFT characteristics is deposited in the target region 23. It can be prevented from remaining.

The end 23c of the target region 23
And the surrounding amorphous silicon region 25 are connected, so that the range of energy application conditions for making the temperature rising rate and the temperature falling rate of each part of the target region 23 uniform can be widened.

In the second embodiment, the quartz substrate 21
However, any substrate having an insulating surface may be used.

Although the gap between the target region 23 and the surrounding amorphous silicon region 25 was 2 μm,
What is necessary is just to be in the range of 0.1 μm or more and 20 μm or less.

Although the amorphous silicon path 24 has one bent portion 24a, it may have a plurality of bent portions. Further, the amorphous silicon path 24 may not have a bent portion. In this case, the target region 23 can be composed of a single crystal grain by making the path width of the amorphous silicon path 24 extremely narrow.

As a catalyst for promoting crystallization of amorphous silicon, Fe, Co, Ni, Ge, Ru, Rh, Pd,
At least one element of Os, Ir, Pt, Cu, Au and Ge may be used. By using at least one of these elements, crystallization of amorphous silicon can be effectively promoted.

Although the mask 203 made of a SiO ₂ film is used, a mask made of at least one of a silicon nitride film, a silicon oxide film, and a silicon carbide film may be used.
The thickness of the mask 203 was 200 nm,
nm or more.

Further, nickel as a catalyst is deposited in the growth source region 2.
Although ions are implanted into the region 2, the ions may be added to the surface of the growth source region 22 by, for example, sputter deposition or coating. In this case, the surface concentration of nickel in the growth source region 22 is 1 × 10 ¹¹ atoms / cm ² or more and 1 × 10 ¹⁶ a.
It suffices if it is within the range of toms / cm ² or less.

The temperature of the electric furnace was 580 ° C., but may be in the range of 400 ° C. to 800 ° C.

The growth source region 22 may be irradiated with, for example, light, an ion beam, an electron beam, or the like to generate crystal grains in the growth source region 22.

Further, a single crystal grain in the target region 23 is irradiated with a laser beam to melt and recrystallize the crystal grain.
For example, the crystal grains may be melted and recrystallized by irradiation with an ion beam or an electron beam.

Also, from the end (dotted line in FIG. 4) of the element forming region 23a opposite to the amorphous silicon path 24,
The length of the target region 23 up to the end 23c on the opposite side to the amorphous silicon path 24 was 25 μm, but it prevents nickel as a catalyst from diffusing into the surrounding amorphous silicon region 25 more than necessary. From the viewpoint of preventing the target region 23 from becoming unnecessarily large, the thickness is preferably in the range of 30 μm or more and 100 μm or less.

[0091]

As is apparent from the above description, the method of manufacturing a semiconductor thin film of the present invention has a structure in which the surrounding amorphous silicon region surrounds the target region with a gap therebetween. With the temperature decreasing rate being uniform, the crystal grains in the target region are subjected to a melt recrystallization treatment, whereby good crystal grains can be obtained, and the thickness of each part of the crystal grains can be made uniform.

In the method of manufacturing a semiconductor thin film according to the present invention, since the surrounding amorphous silicon region surrounds most of the target region with a gap therebetween, the rate of temperature rise and fall of each part of the target region is uniform. In such a state, the crystal grains in the target region are subjected to the melt recrystallization treatment, whereby good crystal grains can be obtained, and the thickness of each part of the crystal grains can be made uniform.

Further, since a part of the target region is connected to the surrounding amorphous silicon region, the catalyst diffuses from the target region to the surrounding amorphous silicon region, and a catalyst that deteriorates the TFT characteristics is required. It is possible to prevent the resin from remaining in the target region, and it is possible to widen the range of energy application conditions for making the rate of temperature rise and fall of each part of the target region uniform.

According to one embodiment of the method of manufacturing a semiconductor thin film, from the viewpoint that the crystal growth in the target region is promoted by the catalyst and the catalyst that deteriorates the TFT characteristics does not remain in the target region. Is preferably connected to the surrounding amorphous silicon region.

According to one embodiment of the method of manufacturing a semiconductor thin film, when a part of the target region is connected to the surrounding amorphous silicon region, the element forming region located on the amorphous silicon path side in the target region. And the distance between the end opposite to the amorphous silicon path in the target region is 30 μm
Since the thickness is 100 μm or less, crystallization of all necessary regions can be promoted, and a catalyst enough to deteriorate TFT characteristics can be prevented from remaining in the element formation region.

According to one embodiment of the method of manufacturing a semiconductor thin film, the gap between the target region and the peripheral amorphous silicon region is 0.1 μm or more and 20 μm or less. Patterning for forming a region can be easily performed, and the rate of temperature rise and the rate of temperature fall of each part of the target region can be easily made uniform.

In one embodiment of the method of manufacturing a semiconductor thin film, since the amorphous silicon path connecting the growth source region and the target region has at least one bent portion, the growth from the growth source region to the target region is performed. The crystal grains to be formed can be selected individually by passing through the bent portion, so that the target region can be completely constituted by a single crystal grain.

In one embodiment, the method for producing a semiconductor thin film includes Fe, Co, and Co as catalysts for promoting crystallization of amorphous silicon.
Ni, Ge, Ru, Rh, Pd, Os, Ir, Pt, C
Since at least one element of u, Au and Ge is used, crystallization of amorphous silicon can be effectively promoted.

In one embodiment of the present invention, the method for manufacturing a semiconductor thin film includes the step of adding at least one of the silicon nitride film, the silicon oxide film and the silicon carbide film to add the catalyst only to the growth source region.
Since a mask having a thickness of 50 nm or more is formed on the surface of the region other than the growth source region, the first mask for the growth source region is formed.
When the energy is applied, the catalyst on the mask can be prevented from contaminating regions other than the growth source region.

Although the mask is in direct contact with the target region, it does not contain impurities or the like which adversely affect the TFT characteristics. Therefore, even if a TFT is manufactured using the target region, the TFT characteristics are not reduced. Can be prevented.

In one embodiment of the present invention, when the catalyst is added to the surface of the growth source region, the surface concentration of the catalyst in the growth source region is set to 1 × 10 ^{11 at.}
Since it is not less than ms / cm ^{2 and not} more than 1 × 10 ¹⁶ atoms / cm ² , crystal growth can be reliably caused in the growth source region, and a large amount of catalyst is prevented from remaining in the crystallized silicon. be able to.

In one embodiment of the present invention, when the catalyst is injected into the growth source region, the concentration of the catalyst in the growth source region is set to 2 × 10 ¹⁶ atoms.
/ Cm ³ or more and 2 × 10 ²¹ atoms / cm ³ or less, crystal growth can be reliably caused in the growth source region, and a large amount of catalyst is prevented from remaining in the crystallized silicon. Can be.

In one embodiment of the method of manufacturing a semiconductor thin film, since the application of the first energy is performed using an electric furnace at a temperature of 400 ° C. or more and 800 ° C. or less, it is possible to prevent the crystallization speed from becoming extremely slow. At the same time, it is possible to prevent a large number of crystal grains not depending on the catalyst from being generated at any place other than the growth source region.

In one embodiment of the method of manufacturing a semiconductor thin film, the application of the second energy is performed by laser irradiation.
Crystal grains grown in the target region can be easily melted and recrystallized.

[Brief description of the drawings]

FIGS. 1A to 1C are process diagrams of a method for manufacturing a semiconductor thin film according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing one step of the method for manufacturing a semiconductor thin film according to the first embodiment.

FIGS. 3A to 3C are process diagrams of a method for manufacturing a semiconductor thin film according to a second embodiment of the present invention.

FIG. 4 is a schematic plan view showing one step of a method for manufacturing a semiconductor thin film according to the second embodiment.

[Explanation of symbols]

 1,21 quartz substrate 2,22 growth source region 3,23 target region 4,24 amorphous silicon path 2,25 surrounding amorphous silicon region 100,200 amorphous silicon film

Continued on the front page (72) Inventor Yasuyuki Umenaka 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 5F052 AA02 AA03 AA04 AA11 AA17 BB07 DA02 DB02 FA03 FA06 FA19 JA01 5F110 DD03 GG02 GG13 GG25 GG47 PP01 PP03 PP08 PP10 PP23 PP29 PP34

Claims (12)

[Claims] A step of forming an amorphous silicon film on a substrate having an insulating surface; a growth source region to which a catalyst is to be added; And a target region to which the crystal grains generated in the growth source region should go,
An amorphous silicon path connecting the growth source region and the target region, and a surrounding amorphous silicon region surrounding the target region with a gap therebetween, and not connected to the target region. Forming a film by patterning, adding a catalyst that promotes crystallization of amorphous silicon only to the growth source region, and applying a first energy to the growth source region, Crystal growing the crystal grains generated in the growth source region on the target region via the amorphous silicon path; and applying a second energy to the target region and the surrounding amorphous silicon region. Melting and recrystallizing crystal grains grown in the target region. A step of forming an amorphous silicon film on a substrate having an insulating surface; a growth source region to which a catalyst is to be added; And a target region to which the crystal grains generated in the growth source region should go,
An amorphous silicon path connecting the growth source region and the target region, and surrounding amorphous silicon surrounding a portion of the target region with a gap therebetween, and connected to a part of the target region. Forming a region by patterning the amorphous silicon film; adding a catalyst that promotes crystallization of amorphous silicon only to the growth source region; Crystal growth of the crystal grains generated in the growth source region on the target region via the amorphous silicon path by applying the energy of Applying a second energy to melt and recrystallize crystal grains grown in the target region. 3. The method for manufacturing a semiconductor thin film according to claim 2, wherein an end of the target region on the side opposite to the amorphous silicon path is connected to the surrounding amorphous silicon region. A method for manufacturing a semiconductor thin film. 4. The method of manufacturing a semiconductor thin film according to claim 3, wherein an element forming region located on the amorphous silicon path side in the target region and an opposite side of the target region in the target region from the amorphous silicon path. 30μm between the edges
A method for producing a semiconductor thin film, wherein the thickness is not less than 100 μm. 5. The method for manufacturing a semiconductor thin film according to claim 1, wherein a gap between the target region and the surrounding amorphous silicon region is 0.1 μm or more and 20 μm or less. A method for manufacturing a semiconductor thin film, comprising: 6. The method of manufacturing a semiconductor thin film according to claim 1, wherein said amorphous silicon path has at least one bent portion. 7. The method of manufacturing a semiconductor thin film according to claim 1, wherein the catalyst is Fe, Co, Ni, Ge, Ru, Rh, P
A method for producing a semiconductor thin film, wherein the method is at least one of d, Os, Ir, Pt, Cu, Au, and Ge. 8. The method of manufacturing a semiconductor thin film according to claim 1, wherein the catalyst is added only to the growth source region, so that the silicon nitride film, the silicon oxide film, and the silicon carbide film are formed. Forming a mask having a thickness of 50 nm or more of at least one type on a surface of a region other than the growth source region. 9. The method of manufacturing a semiconductor thin film according to claim 1, wherein when the catalyst is added to a surface of the growth source region, a surface concentration of the catalyst in the growth source region is reduced. 1 × 10 ¹¹
atoms / cm ² or more and 1 × 10 ¹⁶ atoms / cm
^{2. A} method for producing a semiconductor thin film, wherein the number is ² or less. 10. The method according to claim 1, wherein
In the method of manufacturing a semiconductor thin film according to claim 1, wherein the catalyst is injected into the growth source region,
The concentration of the catalyst in the source region is 2 × 10¹⁶atom
s / cm³More than 2 × 10²¹atoms / cm ³Below
A method for manufacturing a semiconductor thin film, comprising: 11. The method for manufacturing a semiconductor thin film according to claim 1, wherein the application of the first energy is performed at 400 ° C. to 800 ° C.
A method for producing a semiconductor thin film, which is performed using the following electric furnace. 12. The method of manufacturing a semiconductor thin film according to claim 1, wherein the application of the second energy is performed by laser irradiation.