KR20020035909A - Manufacturing Process of Polycrystalline Silicon Thin Film Transistor - Google Patents

Abstract

PURPOSE: A method of fabricating a polysilicon thin film transistor is provided to increase the grain size of polysilicon forming a channel of a polysilicon thin film transistor to reduce grain boundary density. CONSTITUTION: An amorphous silicon thin film is formed on a wafer on which an oxide layer is formed or a glass substrate, and patterned to form an amorphous silicon thin film active region. A photoresist pattern is formed on the amorphous silicon thin film, and a nickel thin film is formed on the silicon thin film and photoresist pattern. The photoresist pattern and the nickel thin film are removed by lift-off to form a nickel pattern. The amorphous silicon thin film is annealed to form a polysilicon thin film. Excimer laser is irradiated on the polysilicon thin film. The nickel thin film is removed, and then a silicon oxide layer is deposited. A gate electrode pattern is formed on the polysilicon thin film and silicon oxide layer, and the silicon oxide layer formed between the polysilicon thin film and gate electrode pattern is patterned and the photoresist pattern is removed. The polysilicon thin film is doped with ions to form gate, source and drain electrodes and the doped ions are activated.

Description

Manufacturing Process of Polycrystalline Silicon Thin Film Transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor. In particular, the grain size of a polycrystalline silicon thin film is performed by performing excimer laser annealing by including a metal element such as nickel (Ni) in a polycrystalline silicon (poly-Si) thin film. It relates to a method of manufacturing a polycrystalline silicon thin film transistor to increase the.

Polycrystalline Silicon Thin Film Transistors (poly-Si TFTs) are widely used as switching elements in Active Matrix-Liquid Crystal Displays (AM-LCDs) because of their excellent current driving capability and high operating speed. There is a lot of research being done.

As a method of fabricating a polycrystalline silicon thin film transistor, a process of crystallizing an amorphous silicon thin film is added to a method of manufacturing an amorphous silicon thin film transistor (a-Si TFT), and a heat treatment method and an excimer laser are used for this crystallization process. This can be used.

As a specific example of a method of manufacturing a polycrystalline silicon thin film transistor using a heat treatment method, Korean Patent Laid-Open Publication No. 99-009393 relates to a method of manufacturing a polycrystalline silicon thin film transistor using a metal induced side crystallization method. A method of manufacturing a polycrystalline silicon thin film transistor in which a metal layer thin film is deposited only in a region except for a source / drain junction portion and then induces crystallization of an amorphous silicon thin film is disclosed.

In the polycrystalline silicon thin film crystallized through the method of manufacturing a polycrystalline silicon thin film transistor using the above heat treatment method, since the amorphous silicon thin film is crystallized in the solid state without undergoing a phase change to the liquid state, a large amount of polycrystalline silicon thin film is formed in the polycrystalline silicon crystal structure. It will include crystal defects. These crystal defects reduce the carrier mobility of the polycrystalline silicon thin film transistor, thereby reducing the current driving ability, and cause a leakage current when a strong horizontal electric field is applied. Therefore, the heat treatment method is difficult to apply to the pixel switching element and the panel driving circuit of the LCD.

In order to solve the above problems, an annealing method using an excimer laser is mainly used. The excimer laser annealing is a method of irradiating an amorphous silicon thin film with a laser beam having a high energy, and crystallization occurs by instantaneous heating of several tens of nsec. Therefore, there is an advantage in that the amorphous silicon thin film is melted without causing damage to the glass substrate to cause a phase change to a liquid state.

The polycrystalline silicon thin film fabricated using the excimer laser is rearranged in the form of grains with excellent crystallinity when silicon atoms are solidified into a solid state after melting the amorphous silicon thin film by excimer laser irradiation (Appl Phys. Lett. Vol. 63, no. 14, p. 1969, 1993) have excellent electrical properties. In the case of the amorphous silicon thin film transistor, the electrical mobility of the carrier is about 1 to 2 cm ² / Vsec, and the electrical mobility of the polycrystalline silicon thin film transistor manufactured by the general heat treatment method is about 10 to 50 cm ² / Vsec. The electrical mobility of the polycrystalline silicon thin film transistor fabricated using is greater than 100 cm ² / Vsec.

However, although the device made of polycrystalline silicon has higher electrical mobility than the device made of amorphous silicon thin film, it has lower electrical mobility than the device made of monocrystalline silicon because of the grain boundary between grains constituting the polycrystalline silicon thin film. This is because h interferes with the flow of carriers and the field effect mobility becomes small. The grain boundary of the polycrystalline silicon thin film is a state in which the bond between the silicon atoms is broken or incompletely bonded, thereby preventing the electrons from moving.

A fundamental way to solve the problem of polycrystalline silicon described above is to increase the grain size to lower the density of grain boundaries in question. A common way to increase grain size is to increase laser energy or heat the substrate, but not enough to bring about dramatic improvements in thin film properties.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to include a metal element such as nickel in a polycrystalline silicon thin film and excimer laser annealing to form a channel of a polycrystalline silicon thin film transistor. It is to provide a method for manufacturing a polycrystalline silicon thin film transistor that increases the size of the grain boundary to reduce the density of grain boundaries.

1 is a schematic diagram of a conventional general excimer laser annealing method.

2 is a planar transmission electron micrograph of the grain structure of a polycrystalline silicon thin film produced by a conventional general excimer laser annealing method.

3 is a schematic diagram of an excimer laser annealing method using a Ni thin film pattern.

4 is a schematic diagram of a structure in which a polycrystalline silicon thin film is observed in cross section after an excimer laser annealing is performed using a Ni thin film pattern.

5 is a planar transmission electron micrograph of the grain structure of a polycrystalline silicon thin film after performing excimer laser annealing using a Ni thin film pattern.

6 is a process chart showing a method for producing a polycrystalline silicon thin film according to the present invention.

7 is a schematic diagram of an excimer laser annealing method according to the present invention.

8 is a planar transmission electron micrograph of the grain structure of a polycrystalline silicon thin film according to the present invention.

9 is a graph showing the concentration distribution of nickel with depth in a MIC polycrystalline silicon thin film.

10 is a graph showing the concentration distribution of nickel with depth in a MILC polycrystalline silicon thin film.

11 is a manufacturing process diagram of a single channel polycrystalline silicon thin film transistor according to the present invention.

12 is a manufacturing process diagram of a polycrystalline silicon thin film transistor having a long channel structure according to the present invention.

In order to achieve the above object, the present invention provides a method for forming an amorphous silicon thin film on a wafer or glass substrate on which an oxide film is formed, and (2) an active region on the amorphous silicon thin film using a photo process and an etching process. (3) forming a photoresist pattern by covering the photoresist film on the amorphous silicon thin film by a photo process, and (4) depositing a nickel thin film on the amorphous silicon thin film and the photoresist film, followed by a lift-off process. Removing the photoresist film and the nickel thin film on the photoresist film to form a nickel pattern, (5) annealing the amorphous silicon thin film at a temperature of about 500 ° C. to crystallize to form a polycrystalline silicon thin film, (6 Irradiating an excimer laser on the polycrystalline silicon thin film; and (7) removing the nickel thin film on the polycrystalline silicon thin film. Depositing a silicon oxide film, (8) depositing a gate electrode material on the polycrystalline silicon thin film and the silicon oxide film, and then patterning the gate electrode material using a photo process and an etching process, and (9) the polycrystal described above. Patterning a silicon oxide film between the silicon thin film and the gate electrode material and removing the photoresist; and (10) activating the implanted ion after doping ions into the polycrystalline silicon thin film to form a gate, source, and drain electrode It provides a method of manufacturing a polycrystalline silicon thin film transistor, characterized in that made.

At this time, in the case of a thin film transistor having a long channel structure having a channel length of 3 μm or more, an ion implantation process of Group 3 elements such as boron or Group 5 elements such as phosphorus and arsenic is performed between steps (3) and (4). Can be added.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a conventional general excimer laser annealing method, Figure 2 is a planar transmission electron microscopy (TEM) of the grain structure of a polycrystalline silicon thin film produced by a conventional general excimer laser annealing method.

In the excimer laser annealing of an amorphous silicon thin film, a phenomenon in which nickel helps grain growth will be described.

3 is a schematic diagram of a structure in which a Ni thin film pattern of several nm thickness is further formed in a conventional general excimer laser annealing method. 4 is a schematic diagram of a structure in which a polycrystalline silicon thin film is observed in cross section after an excimer laser annealing is performed on the thin film layer having the structure of FIG. 3. 5 is a planar TEM photograph in which growth of polycrystalline silicon thin film grains is promoted by a nickel thin film pattern.

In FIG. 4, in the amorphous silicon thin film not covered with the Ni thin film, small grains are formed by excimer laser annealing, whereas the Ni thin film pattern is present so that large grains are grown in the silicon thin film region including Ni component during excimer laser annealing. From the upper left part of FIG. 5, the area | region shown by the strip | belt shape of the diagonal direction which consists of large polycrystalline silicon grain which connects the lower right part is formed. It can be seen from the results of FIG. 5 that the Ni component promotes polycrystalline silicon grain growth in the excimer laser annealing process of amorphous silicon.

Looking at the manufacturing method of the polycrystalline silicon thin film transistor according to the present invention.

As a first step (1), as shown in Figs. 11A and 12A, the amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). It deposits on the wafer in which the oxide film about 5000 micrometers thick is formed, or the glass substrate in which the oxide film about 5000 micrometers thick is formed. At this time, the thickness of the amorphous silicon thin film is set to a value between 300 mW and 2000 mW as necessary. Since the amorphous silicon thin film deposited by PECVD contains a large amount of hydrogen, the dehydrogenation process should be performed by annealing at a temperature of about 400 ° C. for about 2 hours after deposition.

Since the amorphous silicon thin film deposited in the second step (2) is an active layer to be used as a channel, a source, and a drain of the TFT, the active region is patterned by photo-lithography and etching.

In a third step (3), a photo-resist (PR) is covered by the photolithography process on the amorphous silicon thin film to form a photoresist pattern as shown in FIGS. 6A, 11B, and 12B through exposure and development operations. 11 is a manufacturing process sequence of a short channel thin film transistor having a channel length of 3 μm or less, and FIG. 12 is a manufacturing process flowchart of a thin film transistor having a channel length of 3 μm or more. In the fabrication process of FIG. 12, one or more photoresist patterns may be formed according to the channel length as shown in FIG. 12B.

As a fourth step (4), as shown in FIGS. 6B, 11C, and 12E, a Ni thin film having a thickness of about 50 microseconds is deposited by thermal evaporation or electron-gun evaporation and lift-off. The Ni pattern is formed as shown in FIGS. 6C, 11D, and 12F by removing the photoresist film and Ni on the photoresist film together by a (lift-off) process.

In the fifth step (5), the annealing is performed at a temperature of about 500 ° C., whereby the amorphous silicon is crystallized while the Ni component is diffused into the silicon thin film. At this time, polycrystalline silicon of metal induced crystallized (MIC) having high Ni content is formed under the Ni pattern, and metal induced side crystallized (MIC) having low Ni content next to the Ni pattern. Polycrystalline silicon of is formed as shown in Figs. 11E and 12G. MIC polycrystalline silicon and MILC polycrystalline silicon formed in step (5) have a large number of crystal defects and generally have inferior electrical characteristics as compared with excimer laser annealing polycrystalline silicon.

In a sixth step (6), excimer laser annealing is performed as shown in FIGS. 11F and 12H. As shown in FIG. 7, polycrystalline silicon grains are grown from the MIC polycrystalline silicon region to the MILC polycrystalline silicon region by an excimer laser annealing process to form a polycrystalline silicon active region as shown in FIGS. 11G and 12I. At this time, the laser energy conditions vary depending on the thickness of the silicon thin film, but about 250 to 400 mJ / cm ² is suitable for a silicon thin film having a thickness of about 800 GPa.

A description of the excimer laser annealing method for inducing horizontal growth of grain is as follows. 9 and 10 show the results of Ni concentration distribution according to depth in MIC polycrystalline silicon and MILC polycrystalline silicon thin films, respectively, by secondary ion mass spectrometry (SIMS). In the MIC polycrystalline silicon absorbing excimer laser energy, as shown in the results of FIG. 9, since the Ni concentration is very high, 10 ²¹ cm ^-3 or more, the silicon thin film is rapidly melted even at low temperature, and is used for recrystallization of molten silicon. Seed formation and recrystallization are also very fast. On the other hand, in the MILC polycrystalline silicon, the concentration of Ni is as low as 10 ¹⁸ cm ^-3 as shown in the result of FIG. Therefore, nucleation for recrystallization of molten silicon is relatively slow. At this time, the MIC polycrystalline silicon is crystallized and recrystallized for a very short time, and the MILC polycrystalline silicon is not formed and there is a moment in which it remains in a molten state, and the recrystallized MIC polycrystalline silicon region is in a molten state. As a nucleus of the MILC polycrystalline silicon, silicon grains are greatly horizontally grown into the MILC polycrystalline silicon region as shown in FIG. 7.

FIG. 8 is a photograph of the grain structure of the polycrystalline silicon thin film after the excimer laser process according to the present invention using a transmission electron microscope, and it can be seen that the silicon grain has grown to a maximum of 1.3 μm. The grain size of the polycrystalline silicon thin film according to the present invention was increased by several orders of magnitude compared with the average size of the polycrystalline silicon grains produced by the conventional general excimer laser annealing method shown in FIG. 2.

The best method for fabricating a thin film transistor device with a polycrystalline silicon thin film according to the present invention is to arrange the channel direction of the thin film transistor in parallel with the growth direction of the horizontal growth grain as shown in FIG. 11G. When the channel direction of the thin film transistor is arranged in parallel with the grain growth direction, when a current is applied by applying a voltage between the source and the drain of the thin film transistor, moving carriers pass through only one grain boundary, so that the general thin film transistor element In comparison, the field effect mobility of the carrier and the driving current characteristics of the thin film transistor element may be improved as compared with a conventional thin film transistor element.

However, the above method can be used for the production of polycrystalline silicon thin film transistors having a channel length of 3 μm or less. In the case of manufacturing a thin film transistor having a long channel length of 3 μm or more, as shown in FIG. 12I, there is an active thin film region composed of small silicon grains. There is this. In order to solve the above disadvantages, as shown in FIGS. 12C and 12D, a group 3 element or phosphorus such as boron or the like may be formed between forming the photoresist pattern on the amorphous silicon thin film (3) and depositing the Ni thin film (4). An ion implantation process of a Group 5 element such as arsenic can be added to dope the polycrystalline silicon thin film region formed of small grains.

In the seventh step (7), the Ni thin film is removed using an acid such as hydrochloric acid or sulfuric acid, and as shown in FIGS. 11H and 12J, a silicon oxide film is formed on the polycrystalline silicon thin film using a plasma chemical vapor deposition method as a gate insulating film. Deposit. At this time, the thickness of the silicon oxide film is suitably about 300 Pa to 1000 Pa.

As an eighth step (8), as shown in FIGS. 11I and 12K, as a gate electrode material, an amorphous silicon thin film having a thickness of about 2000 to 4000 kV is deposited or sputtered by using plasma chemical vapor deposition or low pressure chemical vapor deposition. To deposit an aluminum thin film having a thickness of about 2000 kPa to 4000 kPa. The photoresist film is covered on the gate electrode material by a photo process, and the photoresist pattern of the gate electrode pattern is formed as shown in FIGS. 11J and 12L through exposure and development operations. Using the patterned photoresist as a mask, the gate electrode material is etched and patterned as shown in FIGS. 11K and 12M.

In the ninth step 9, the silicon oxide film serving as the gate insulating film is etched and patterned using the photoresist pattern as a mask. Subsequently, the photosensitive film is removed to fabricate the structures shown in FIGS. 11L and 12N.

In the tenth step 10, as shown in FIGS. 11M and 12O, a group III element such as boron or a group 5 element such as phosphorus or arsenic is doped into the polycrystalline silicon thin film using an ion implantation process or an ion shower process. Gate, source, and drain electrodes are formed. Excimer laser annealing or heat treatment is performed as shown in FIGS. 11N and 12P to activate the implanted Group 3 or 5 elements. Through the annealing, the polycrystalline silicon thin film transistors of FIGS. 11O and 12Q are finally completed.

As described above, the density of grain boundaries in the polycrystalline silicon thin film can be significantly reduced by increasing the grain size of the conventional polycrystalline silicon thin film of about several hundred nm to about several micrometers. Accordingly, by smoothing the flow of electrons in the polycrystalline silicon thin film transistor, the current driving characteristics of the polycrystalline silicon thin film transistor element can be improved, and the application area of the polycrystalline silicon thin film transistor element can be expanded.

Claims (3)

(1) forming an amorphous silicon thin film on a wafer or glass substrate on which an oxide film is formed, (2) patterning the amorphous silicon thin film active region using a photolithography process and an etching process, and (3) the amorphous (4) depositing a nickel thin film on the amorphous silicon thin film and the photosensitive film, and then removing the nickel thin film on the photosensitive film and the photosensitive film by a lift-off process. (5) annealing the amorphous silicon thin film at a temperature of about 500 ° C. to form a polycrystalline silicon thin film, and (6) irradiating an excimer laser on the polycrystalline silicon thin film. (7) removing the nickel thin film on the polycrystalline silicon thin film and then depositing a silicon oxide film, and (8) the Depositing a gate electrode material on the polycrystalline silicon thin film and the silicon oxide film, and then patterning the gate electrode material using a photolithography process and an etching process, (9) patterning the silicon oxide film between the polycrystalline silicon thin film and the gate electrode material; Removing the photoresist film; and (10) forming a gate, a source, and a drain electrode by doping ions into the polycrystalline silicon thin film, and then activating the implanted ions. Manufacturing method. The method of claim 1, Irradiating an excimer laser on the polycrystalline silicon thin film (6) is performed at 250-400mJ / cm ² . The method of claim 1, An ion doping process is added between steps (3) and (4) when the channel length of the thin film transistor is 3 µm or more.