JPS63291178A - Digital signal processor - Google Patents

Abstract

PURPOSE:To execute a high speed picture processing by providing a function for simultaneously loading a program in plural memories and processing the respective picture elements of a picture signal in parallel. CONSTITUTION:The titled processor is provided with a local picture shift register 2, the plural picture memories 4-1-4-4 for storing the contents of the shift register 2, plural arithmetic blocks 1-1-1-4 for processing the picture based on the data of the picture memories 4-1-4-4, plural program memories and controllers 5-1-5-4 for controlling the arithmetic blocks 1-1-1-4 and the function for simultaneously loading the program in the plural program memories 5-1-5-4. The respective picture elements of the picture signal are processed in parallel. Since this is the parallel processing for every picture element of the picture signal, a higher instruction such as a condition jump instruction or the like can be executed in a next instruction cycle without a waiting time. Thereby, a more complicate picture processing can be realized at high speed and a real time processing is easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing device that can perform image signal processing and the like in parallel at high speed.

Conventional technology Ultra LSI (large 5cale integ)
Compact, high-speed processors and memories are used for various signal processing using rated circuit technology.

DSP (dj4i
A processor called a talsignal processor is used. This is mulu (arit
In addition to the hmetic logic unit, it also has a dedicated multiplier, etc., and can process data at high speed.

At present, signals in the audio band can be processed in real time using these processors.

The average instruction cycle of a DSP is about 100 ns. If the audio sampling i is 20 KHz, then 1
Since the sampling time is 60 μs, the number of instructions that can be processed within this time is 500. If this number of commands is possible, it will be possible to perform a large number of commands, and it will be possible to perform real-time processing such as speech recognition and synthesis, and various band compressions for digital transmission.

On the other hand, in the case of 9 image processing such as medical use and pattern recognition, money is considered. For audio signals the sampling is at most 50 KHz, for image signals the sampling is 10-20 M
High as Hz. Therefore, when performing image processing in real time, a processing speed of two orders of magnitude or more is required compared to audio signal processing. For example, if a video signal is sampled at 10 MHz, even if the number of processing steps is less than that for an audio signal, 10 MHz will be processed within this sampling time.
Processing of 0 or more instructions is required. In other words, real-time processing cannot be performed unless the instruction cycle time is 1n8 or less.

One possible way to achieve all of this is to improve device performance. Since the current DSP is composed of MO8 type LSI, this DSP-i bipolar type LSI
You can increase the speed by doing this. A system as seen in Japanese Patent Application No. 59-118484 has already been proposed. In addition to the original DSP configuration, this is equipped with a register to which local image data can be input at any time to increase speed, and is also equipped with a program memory for high-speed program execution. If this system is made into a bipolar LSI, it will be possible to achieve a high-speed performance that is about one order of magnitude higher than that of the conventional 115P.

Problems to be Solved by the Invention However, the above system is only about one order of magnitude faster than conventional DSPs. Even bipolar LSIs are limited by device speed.

Also, although this system has been speeded up with a new system configuration, there are limits to this as well. In view of these conventional drawbacks, the present invention provides a digital signal processing device that enables more advanced real-time image signal processing through parallel signal processing of image data for each pixel.

Means for solving all problems A local image shift register, a plurality of image memories that store the contents of this shift register, a plurality of operation blocks that perform image processing using all the data in this image memory, and these operations. Equipped with multiple program memories and controllers that control blocks, and a function to load all programs into these multiple memories at the same time.
The present invention provides a digital signal processing device that can perform high-speed image processing by processing each pixel of an image signal in parallel.

According to this configuration, high-speed operation exceeding the high-speed limit of the device is possible. Compared to conventional parallel processing or pipeline processing, since the image signal is processed in parallel for each pixel, more advanced instructions such as conditional jump instructions can be executed in the next instruction cycle without waiting time. Furthermore, since the processing for each pixel is the same, the program to be loaded into the program memory can be the same and can be easily input using a single program loader.

In addition, even with MOS devices that have a slow calculation speed but are suitable for highly integrated semiconductor integrated circuits, if this system configuration is used, it is possible to construct a high-speed system that requires less money and power than a semiconductor integrated circuit that uses fast bipolar devices. be able to.

Embodiment FIG. 1 shows an embodiment of the present invention. 1-1 to 1-4 are calculation blocks that perform calculations such as addition and subtraction, and logical operations 9 and multiplication; 2
is a register block that sequentially shifts local image data such as 3 x 3, 3-1.3-2 is a play line that delays the entire line of image data, and 4-1 to 4-4 are local blocks that are 3 x 3 etc. A memory that stores image data during the calculation of one pixel.
6-1 to 6-4 are program memories for storing instructions and their control blocks, 6 is a program loader, 1 is a data register for inputting data from the outside, and 8 is an output circuit for switching all outputs. 9 is an image data input terminal, 10
1 is an output terminal for processed image data, 11 is an input terminal for program data, and 12 is an input terminal for data.

The image processing program input to the terminal 11 is stored in the program memories 5-1 to 5-4 under the control of the program loader 6. At this time 6-1~
The same program is simultaneously written into the memories 5-4. On the other hand, image data is input through terminal 9 and passed through local image shift register 2. In this embodiment, since four pixels are processed in parallel as local image data 3×3, two local image registers have the configuration shown in FIG. Numeral 21 is one register, which is connected in cascade in six stages, and is outputted to a one-line shift register 3-1 through all n shift registers. If the number of pixels in the horizontal direction of the image is 512, the number of stages of the 1-line shift register 3-1 may be 512-6=506 stages.

The output of this 1-line shift register 3-1 is input to the second-stage shift register of the local image shift register 2, and is similarly output to the 1-line shift register 3-2 through the 6-stage shift register. . The 1-line shift register 3-2 has the same number of stages as the 1-line shift register 3-1, and the output is input to the third stage shift register of the local image shift register 2. By combining the outputs of these 18 registers, data for four 3×3 local images shown in FIG. 3 is obtained. This data is sent to image memories 4-1 to 4-4. Note that if the total number of bits of pixel data is 8 bits, the number of these shift registers in the depth direction is eight.

The data stored in the image memories 4-1 to 4-4 are selected by the program and output to the calculation blocks 1-1 to 1-4. The calculation block is human LU (Mrithma)
It consists of a tic Logic Unit), a multiplier, a register, a data memory, etc., and performs edge detection for each pixel,
Processes such as noise removal are executed according to programs stored in the memories in 6-1 to 5-2. For commands such as jump, the calculation results of calculation blocks 1-1 to 1-4 are checked by all controller units 6-1 to 5-4, and the command is executed.

External data input used for calculations is input from terminal 12 and input to each calculation block via 7 data registers. The processed image data is controlled by the output circuit 8 and output from the terminal 1o in order.

In this embodiment, four stages of parallel processing have been described, but it goes without saying that this can be changed depending on the required speed. Also, the number of pixels of image data is determined by one line shift register (3-1~
Needless to say, the number of stages in step 3-2) can be controlled, and the size of the local image can also be made larger, such as 6×6.

Further, although the calculation programs for each calculation block are all the same in the embodiment, it is also possible to perform separate image processing by changing the programs stored in the individual memories in 5-1 to 5-4.

In this embodiment, the image memory is divided into 4-1 to 4-4, but most of the data for the four 3×3 local images is the same, so they can be shared. FIG. 4 shows an example of a memory configuration in which image data is shared. 41-
1.41-2 is dual port memory, 42-1 to 42
-4 is a memory address decoder. The four blocks of image memory in FIG. 1 become two blocks, and one image memory stores 4×3 local image data. In the decoder 42-1, 3× corresponding to the image memory 4-1 in FIG.
The decoder 42-2 outputs all 3×3 image data corresponding to the image memory 4-2. The same applies to image memo 1J41-2. By using this dual port memory, the total number of memories can be reduced from 3×3×4=36 to 4×3×2=24.

Effects of the Invention According to the present invention, unlike conventional parallel calculations and pipeline processing, parallel image processing is performed for each pixel, so even complex image processing can be performed at high speed. The higher the number of parallel stages, the higher the speed and the easier real-time processing.

Although bipolar devices are used for high-speed image processing, MOS devices can also be used in this parallel system, making it possible to realize high-speed, low-power semiconductor integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the digital signal processing device of the present invention, FIG. 2 is a detailed configuration diagram of the local image shift register, FIG. 3 is an explanatory diagram of the local image area, and FIG. 4 is another configuration of the image memory. It is a diagram. 1... Arithmetic block, 2... Local image shift register, 4... Image memory, 5...
...Program memory and controller.

Claims (1)

[Claims] a local image shift register; a plurality of image memories that store the contents of the shift register; a plurality of calculation blocks that perform image processing based on data in the image memory; a plurality of program memories that control the calculation blocks; A digital signal processing device comprising a controller and a function of simultaneously loading a program into the plurality of program memories, and processing each pixel of an image signal in parallel.