JPS63288036A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63288036A JPS63288036A JP62123292A JP12329287A JPS63288036A JP S63288036 A JPS63288036 A JP S63288036A JP 62123292 A JP62123292 A JP 62123292A JP 12329287 A JP12329287 A JP 12329287A JP S63288036 A JPS63288036 A JP S63288036A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- metal base
- hole
- fitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000000919 ceramic Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 230000017525 heat dissipation Effects 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 23
- 229910001080 W alloy Inorganic materials 0.000 claims description 3
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004931 aggregating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はガリウムヒ素等からなる素子のように、高速か
つ高集積度の化合物半導体素子を用いるマルチチップの
半導体装置に関し、特に高速度の信号処理に用いられる
ものである。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to multi-chip semiconductor devices using high-speed, highly integrated compound semiconductor devices such as devices made of gallium arsenide, etc. It is used for processing.
（従来の技術）
高周波帯域、特にＧＨｚ帯での高速信号処理に適した半
導体装置として、ガリウムヒ素を用いる半導体装置が多
用されている。このようなガリウムヒ素による半導体装
置における従来の実装形態を、チップキャリアを例とし
て第３図に示す。(Prior Art) Semiconductor devices using gallium arsenide are often used as semiconductor devices suitable for high-speed signal processing in high frequency bands, particularly in the GHz band. A conventional mounting form of such a semiconductor device using gallium arsenide is shown in FIG. 3 using a chip carrier as an example.
第３図（ａ）は従来のガリウムヒ素による半導体装置の
、第１の例の構成を示す断面図である。FIG. 3(a) is a sectional view showing the structure of a first example of a conventional semiconductor device using gallium arsenide.
図示の通り、アルミナ等のセラミックス類のベース１の
中央部には凹部２が形成され、この凹部２にはガリウム
ヒ素チップ３が載置して固着されている。このガリウム
ヒ素チップ３上の電極（図示せず。）とベース１の凹部
２の周囲に形成された厚膜印刷配線４とは、金、アルミ
ニウム等の金属配線５により接続されている。しかしな
がらこの従来装置では、セラミックスの表面は凹凸が多
く、高精度の配線は困難である。このため、厚膜印刷配
線４は例えば最小幅１００μｍ程度であり、高密度の実
装は不可能である。特に、グランド配線の形成が困難で
あることからインピーダンス整合を行なえず、配線パタ
ーンの自由度が少ない。As shown in the figure, a recess 2 is formed in the center of a base 1 made of ceramics such as alumina, and a gallium arsenide chip 3 is placed and fixed in the recess 2. The electrode (not shown) on the gallium arsenide chip 3 and the thick film printed wiring 4 formed around the recess 2 of the base 1 are connected by a metal wiring 5 made of gold, aluminum, or the like. However, in this conventional device, the ceramic surface has many irregularities, making it difficult to perform highly accurate wiring. For this reason, the thick film printed wiring 4 has a minimum width of, for example, about 100 μm, making high-density packaging impossible. In particular, since it is difficult to form ground wiring, impedance matching cannot be performed, and there is little freedom in wiring patterns.
第３図（ｂ）は従来の他の実装形態を示ず断面図である
。図示の通り、平坦なセラミックス類のベース１１の上
面に薄膜配線１２が形成され、中央部にダイボンディン
グされたガリウムヒ素デツプ１３との間で、金属配線（
ワイヤ）１４により接続がなされている。しかしながら
この場合にも、ベースにセラミックスを用いているため
、ｗＪ膜配線であっても最小幅１０μ■程度の配線が可
能であるに過ぎず、多層配線も不可能であるので高密度
実装には適していなり。FIG. 3(b) is a sectional view showing another conventional mounting form. As shown in the figure, a thin film wiring 12 is formed on the upper surface of a flat ceramic base 11, and a metal wiring (
The connection is made by a wire) 14. However, even in this case, since ceramics are used for the base, wiring with a minimum width of about 10μ■ is only possible even with wJ film wiring, and multilayer wiring is not possible, so high-density mounting is not possible. Not suitable.
第３図（Ｃ）は更に伯の従来の実装形態を示す断面図で
ある。図示の通りこの場合には、表面に薄膜配線層２２
を形成したシリコン基板２１上の中央部に、ガリウムヒ
素チップ２３がダイボンディングされ、これと薄膜配線
層２２との間で金属配線２４による接続がなされている
。この場合には、シリコン基板を採用したことにより表
面の平坦度が大幅に改善されるため、最小幅３μｍ程度
の薄膜配線層の形成が可能である。FIG. 3(C) is a sectional view showing a further conventional mounting form. As shown in the figure, in this case, there is a thin film wiring layer 22 on the surface.
A gallium arsenide chip 23 is die-bonded to the center of the silicon substrate 21 on which the gallium arsenide chip 23 is formed, and a connection is made between the gallium arsenide chip 23 and the thin film wiring layer 22 by a metal wiring 24. In this case, since the surface flatness is greatly improved by employing a silicon substrate, it is possible to form a thin film wiring layer with a minimum width of about 3 μm.
一方、高度の情報処理等を行うためには、多数のチップ
を高密度に実装する必要があり、マルチチップパッケー
ジ化が要求されている。On the other hand, in order to perform advanced information processing, etc., it is necessary to mount a large number of chips at high density, and multi-chip packaging is required.
（発明が解決しようとする問題点）
しかしながら、前述したいずれの場合も放熱特性が良好
ではなく、マルチチップパッケージには適さない。一般
に、５００ＭＨｚ以上の高速動作をする半導体装置では
発熱が多く、従来の半導体装置では十分な放熱ができな
いために動作に悪影響を与え、高速動作には適さない。(Problems to be Solved by the Invention) However, in any of the cases described above, the heat dissipation characteristics are not good, making them unsuitable for multi-chip packages. Generally, semiconductor devices that operate at high speeds of 500 MHz or higher generate a lot of heat, and conventional semiconductor devices cannot dissipate heat sufficiently, which adversely affects operation and is not suitable for high-speed operation.
そして、このような半導体装置の集合体（マルチチップ
の半導体装置）では、ざらに放熱が困難となる。In such an assembly of semiconductor devices (multi-chip semiconductor devices), it becomes difficult to dissipate heat.
そこで本発明は、高密度配線が可能で放熱特性に優れ、
かつ高速動作特性にもすぐれた半導体装置を提供するこ
とを目的とする。Therefore, the present invention enables high-density wiring and has excellent heat dissipation characteristics.
It is an object of the present invention to provide a semiconductor device which also has excellent high-speed operation characteristics.
本発明に係る半導体装置は、少なくとも表面に配線が形
成されると共に中央部に第１の孔部が形成されたシリコ
ン配線板を、放熱用の金属ベース上に載置固着し、第１
の孔部に化合物半導体チップをはめ込んで金属ベースに
固着し、シリコン配線板と半導体チップをワイヤで接続
した複数個の半導体装置サブアセンブリを備えており、
これらをセラミックスベースの第２の孔部にはめ込んで
、更にシリコン配線板とセラミックスベースの多層配線
をワイヤにより接続したことを特徴としている。In the semiconductor device according to the present invention, a silicon wiring board on which wiring is formed at least on the surface and a first hole formed in the center is placed and fixed on a metal base for heat dissipation,
It is equipped with multiple semiconductor device subassemblies in which a compound semiconductor chip is fitted into the hole and fixed to a metal base, and the silicon wiring board and the semiconductor chip are connected with wires.
These are fitted into the second holes of the ceramic base, and the silicon wiring board and the ceramic-based multilayer wiring are further connected by wires.
本発明に係る半導体装置は、以上のように構成されるの
で、各化合物半導体チップで発生した熱は金属ベースに
流れて良好な放熱が行われる。また、各化合物半導体チ
ップの周囲では、シリコン基板による薄膜の精密な配線
が行われるため、高密度の配線が可能となり、多数のチ
ップの集合により全体として高密度の配線が可能となる
。ざらに、コンデンサや抵抗等をシリコン上に作り込む
ことも可能であり、態化を増強できる。Since the semiconductor device according to the present invention is configured as described above, the heat generated in each compound semiconductor chip flows to the metal base, and good heat radiation is performed. In addition, around each compound semiconductor chip, precise thin film wiring is performed using a silicon substrate, so high-density wiring is possible, and by aggregating a large number of chips, high-density wiring is possible as a whole. Furthermore, it is also possible to fabricate capacitors, resistors, etc. on silicon, which can enhance the implementation.
（実施例）
以下、添附図面を参照して、本発明の一実施例を説明す
る。なお、図面の説明において同一の要素には同一の符
号を付し、重複する説明を省略する。(Example) Hereinafter, an example of the present invention will be described with reference to the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.
第１図は実施例に係る半導体装置の外観を示す斜視図で
ある。図示の通り、セラミックスベース５１に形成され
た４つの矩形の孔部（第２の孔部）５２に、例えばタン
グステン２０％、銅８０％の銅タングステン合金より成
る放熱用の金属ベース６１がはめ込まれるようになって
おり、この金属ベース６１の上にシリコン配線板７１が
載置固着されている。セラミックスベース５１は多層配
線を有しており、例えば配線導体５３はセラミックスベ
ース５１の外側面のメタライズ層５４に接続されている
。FIG. 1 is a perspective view showing the appearance of a semiconductor device according to an example. As shown in the figure, a metal base 61 for heat dissipation made of, for example, a copper-tungsten alloy of 20% tungsten and 80% copper is fitted into four rectangular holes (second holes) 52 formed in the ceramic base 51. A silicon wiring board 71 is placed and fixed on top of this metal base 61. The ceramic base 51 has multilayer wiring, and for example, a wiring conductor 53 is connected to a metallized layer 54 on the outer surface of the ceramic base 51.
シリコン配線板７１の表面には引出し用の配線パターン
７２が形成されると共に、中央部には矩形の孔部（第１
の孔部）７３が形成されている。A wiring pattern 72 for drawing out is formed on the surface of the silicon wiring board 71, and a rectangular hole (first
A hole (hole portion) 73 is formed.
そして、この孔部７３内には素子が形成されたガリウム
ヒ素チップ８１が配置され、金属ベース６１に直接固着
されている。また、ガリウムヒ素チップ８１の電極（図
示せず。）と配線パターン７２はワイヤ８２により接続
され、シリコン配線板７１上の配線パターン７２とセラ
ミックスベース５１上の配線導体５３とはワイヤ７５に
より接続されている。A gallium arsenide chip 81 on which an element is formed is disposed within the hole 73 and is directly fixed to the metal base 61. Further, the electrodes (not shown) of the gallium arsenide chip 81 and the wiring pattern 72 are connected by a wire 82, and the wiring pattern 72 on the silicon wiring board 71 and the wiring conductor 53 on the ceramic base 51 are connected by a wire 75. ing.
なお、銅タングステン合金はその熱膨張率が６．９Ｘ１
０’°ｃ−１であってガリウムヒ素のそれとほぼ等しく
、また熱伝導率は２．８Ｗ／ｃｍ″Ｃであって十分に大
きいので、本発明に特に適している。この様な構成では
、ガリウムヒ素チップ５２は直接金属ベース５１に取付
けられているため、発生した熱は高効率で放出されるこ
とになる。また、シリコン配線板には高密度の配線形成
が可能であるので、ワイヤボンディングの限界まで配線
密度を上げることができる。In addition, the coefficient of thermal expansion of copper-tungsten alloy is 6.9X1
Since the thermal conductivity is 0'°c-1, which is almost equal to that of gallium arsenide, and the thermal conductivity is 2.8 W/cm''C, which is sufficiently large, it is particularly suitable for the present invention.In such a configuration, Since the gallium arsenide chip 52 is directly attached to the metal base 51, the generated heat can be dissipated with high efficiency.In addition, since high-density wiring can be formed on the silicon wiring board, wire bonding is possible. Wiring density can be increased to the limit of .
次に、第１図に示す半導体装置の製造工程を説明する。Next, the manufacturing process of the semiconductor device shown in FIG. 1 will be explained.
第２図は第１図の構成を得るための製造工程を示す工程
別断面図であり、ガリウムヒ素チップの中央で切断した
様子を示すものである。FIG. 2 is a cross-sectional view showing the manufacturing process for obtaining the configuration shown in FIG. 1, and shows a gallium arsenide chip cut at the center.
まず、所定領域が孔部５２となるように、積層による多
層配線技術によって配線５３を形成したセラミックスベ
ース５１をＱ備する（第２図（ａ））。このセラミック
スベース５１としては、まずベースの仝休を形成してお
き、次に所定領域をエツチング除去して形成してもよい
。First, a ceramic base 51 is provided with a wiring 53 formed thereon by a multilayer wiring technique using lamination so that a predetermined region becomes a hole 52 (FIG. 2(a)). The ceramic base 51 may be formed by first forming a rest area of the base and then removing a predetermined area by etching.
次に、表面が結晶方位（１００）面となっており、あら
かじめ表面あるいは内層に所定のパターンで配線を形成
したシリコン配線板７１の上に、３ｉ０２あるいはＳｉ
Ｎなどからなるマスク９１をパターニングして形成しく
第２図（ｂ））、このマスク９１を介してエチレンジア
ミン、ピロカテコール、水の混合液によるエッチャント
を用いてエツチングを行う。すると、水平面に対して５
４．７°の角度をなす結晶方位（１１１）の側壁７４を
有する孔部７３が形成される（第２図（Ｃ））。Next, a 3i02 or Si
A mask 91 made of N or the like is patterned and formed (FIG. 2(b)), and etching is performed through this mask 91 using an etchant containing a mixture of ethylenediamine, pyrocatechol, and water. Then, 5 for the horizontal plane
A hole 73 is formed having a side wall 74 with a (111) crystal orientation forming an angle of 4.7° (FIG. 2(C)).
次に、このようにして得られたシリコン配線板７１の孔
部７３を通して、ガリウムヒ素チップ８１を金属ベース
６１上に公知の方法でダイボンドし、半導体装置サブア
センブリを形成する（第２図（ｄ））。なお、この実施
例の場合には、ガリウムヒ素チップ５２の厚さとシリコ
ン配線板７１の厚さはほぼ等しくなってあり、両者の表
面は同一面をなしているため、後続のワイヤボンディン
グを行いやすく、また、ワイヤーを短かくできインダク
タンスを減らせるという利点がある。Next, a gallium arsenide chip 81 is die-bonded onto the metal base 61 by a known method through the hole 73 of the silicon wiring board 71 obtained in this way to form a semiconductor device subassembly (FIG. 2(d) )). In the case of this embodiment, the thickness of the gallium arsenide chip 52 and the thickness of the silicon wiring board 71 are almost equal, and their surfaces are the same, making it easier to perform subsequent wire bonding. Another advantage is that the wire can be shortened and inductance can be reduced.
次に、上記のサブアセンブリをセラミックスベース５１
の孔部５２にはめ込み、低融点金属や接着剤等により固
着する。しかる後、ガリウムヒ素チップ８１上の電極（
図示せず。）とシリコン配線板７１上の配°線をワイヤ
８２によって接続し、シリコン配線板７１上の配線とセ
ラミックスベース５１の配線５３とをワイヤ７５により
接続する。Next, the above subassembly is attached to the ceramic base 51.
It is fitted into the hole 52 and fixed with a low melting point metal, adhesive, or the like. After that, the electrode on the gallium arsenide chip 81 (
Not shown. ) and the wiring on the silicon wiring board 71 are connected by a wire 82, and the wiring on the silicon wiring board 71 and the wiring 53 of the ceramic base 51 are connected by a wire 75.
以上の工程により、マルチチップ半導体装置が完成する
。Through the above steps, a multi-chip semiconductor device is completed.
本発明は上記実施例に限定されるものではなく、種々の
変形が可能である。The present invention is not limited to the above embodiments, and various modifications are possible.
例えば、シリコン配線板に凹部を形成するためのエツチ
ングでは、エチレンジアミン系のエッチャントに限らず
、例えばヒドラジンの水溶液や水酸化カリウム水溶液を
用いてもよい。また、放熱用の金属ベースとしては実施
例で述べたちの以外に、熱伝導率が′大きいものであれ
ば、いかなるものでも使用することができる。そして、
熱膨張率がガリウムヒ素等と近似したものであれば、よ
り信頼性が向上する。For example, in etching for forming recesses in a silicon wiring board, not only an ethylenediamine-based etchant but also an aqueous solution of hydrazine or an aqueous potassium hydroxide solution may be used. Further, as the metal base for heat dissipation, any metal base other than those mentioned in the embodiments can be used as long as it has a high thermal conductivity. and,
If the coefficient of thermal expansion is similar to that of gallium arsenide or the like, reliability will be further improved.
ざらに、シリコン配線板は上記実施例では単に配線を形
成したに過ぎないものであったが、キャパシタや抵抗等
の受動素子、あるいはトランジスタ等の能動素子を形成
したものであってもよい。In general, although the silicon wiring board merely formed wiring in the above embodiment, it may also have passive elements such as capacitors and resistors, or active elements such as transistors formed thereon.
また、シリコン板の配線は表面層に限らず、多層配線と
なっていてもよい。逆に、セラミックスベースの配線は
表面層だけに形成されていてもよい。Furthermore, the wiring on the silicon board is not limited to the surface layer, but may be multilayer wiring. Conversely, ceramic-based wiring may be formed only on the surface layer.
ざらにまた、シリコン配線板の表面は（１００）面に限
られるものではなく、例えば表面が（１１０）面であれ
ば、水平面と９０°の角度をなす側壁がエツチングによ
り形成される。Furthermore, the surface of the silicon wiring board is not limited to the (100) plane; for example, if the surface is the (110) plane, side walls forming an angle of 90° with the horizontal plane are formed by etching.
以上、詳細に説明した通り、本発明に係る半導体装置に
よれば、放熱用金属ベース上に配線の形成されたシリコ
ン板を固着し、そのシリコン板に設けられた孔部内に化
合物半導体チップをはめ込んで放熱用金属ベースに固着
し、これらによってサブアセンブリを形成し、このよう
なサブアセンブリをセラミックスベースにはめ込んでい
るので、化合物半導体チップからの放熱特性が良好とな
る。As described above in detail, according to the semiconductor device of the present invention, a silicon plate on which wiring is formed is fixed onto a metal base for heat dissipation, and a compound semiconductor chip is fitted into a hole provided in the silicon plate. Since the compound semiconductor chip is fixed to a metal base for heat dissipation to form a subassembly, and such a subassembly is fitted into the ceramic base, the heat dissipation characteristics from the compound semiconductor chip are improved.
また、シリコン板には高密度の配線を形成することがで
きるため、非常に高密度のガリウムヒ素チップから、あ
まり高密度の配線ができないセラミックスの多層配線へ
の引出しを、上記シリコン板を介して円滑に行うことが
できるという効果がある。In addition, since high-density wiring can be formed on a silicon plate, it is possible to connect a very high-density gallium arsenide chip to ceramic multi-layer wiring, where high-density wiring cannot be formed, through the silicon plate. This has the effect of being able to be carried out smoothly.
ざらに、良品のサブアセンブリを選択して使用すること
ができるので、マルチチップ半導体装置の全体としての
歩留りを向上させることができる効果がある。In other words, since it is possible to select and use subassemblies of good quality, there is an effect that the overall yield of the multi-chip semiconductor device can be improved.
第１図は本発明に係る半導体装置の実施例を示す斜視図
、第２図は本発明に係る半導体装置の製造工程を示す工
程別断面図、第３図は従来のガリウムヒ素半導体装置の
構成を示す素子断面図である。
１．１１・・・セラミックス基板、２１．・・・シリコ
ン基板、３，１３，２３．８１・・・ガリウムヒ素チッ
プ、５１・・・セラミックスベース、５２・・・孔部（
第２の孔部）、６１・・・金属ベース、７１・・・シリ
コン配線板、７３・・・孔部（第１の孔部）、７５．８
２・・・ワイヤ。
特許出願人 住友電気工業株式会社
代理人弁理士 長谷用 芳 樹第２図FIG. 1 is a perspective view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the present invention, and FIG. 3 is a configuration of a conventional gallium arsenide semiconductor device. FIG. 1.11... Ceramic substrate, 21. ...Silicon substrate, 3,13,23.81...Gallium arsenide chip, 51...Ceramics base, 52...Hole (
2nd hole), 61... Metal base, 71... Silicon wiring board, 73... Hole (first hole), 75.8
2...Wire. Patent Applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney Yoshiki Hase Figure 2
Claims (1)
て固着され、少なくとも表面に配線が形成されると共に
、中央部に第１の孔部が形成されたシリコン配線板と、
前記孔部にはめ込まれて前記金属ベースに固着されると
共に、前記配線とワイヤで接続された化合物半導体チッ
プとを有する複数個の半導体装置サブアセンブリと、 前記金属ベースがはめ込まれる第２の孔部を複数個有す
ると共に、多層配線が形成されたセラミックスベースと
を備え、 前記複数の第２の孔部内に前記複数の半導体装置サブア
センブリがそれぞれはめ込まれ、前記シリコン配線板上
の配線と前記セラミックスベースの多層配線がワイヤに
より接続されたことを特徴とする半導体装置。 ２、前記化合物半導体がガリウムヒ素であることを特徴
とする特許請求の範囲第１項記載の半導体装置。 ３、前記金属ベースがガリウムヒ素と近似した熱膨脹係
数を有するもので形成されていることを特徴とする特許
請求の範囲第２項記載の半導体装置。 ４、前記金属ベースが銅タングステン合金で形成されて
いることを特徴とする特許請求の範囲第３項記載の半導
体装置。 ５、前記第１の孔部の側壁が水平面に対して５４．７°
の角度をなす結晶方位（１１１）面であることを特徴と
する特許請求の範囲第１項記載の半導体装置。 ６、前記シリコン配線板の一辺の長さが前記セラミック
ス配線板の第２の孔部の一辺の長さよりも短いことを特
徴とする特許請求の範囲第１項記載の半導体装置。[Claims] 1. A metal base for heat dissipation, and silicon placed and fixed on the metal base, with wiring formed on at least the surface and a first hole formed in the center. wiring board and
a plurality of semiconductor device subassemblies each having a compound semiconductor chip fitted into the hole and fixed to the metal base and connected to the wiring with a wire; and a second hole into which the metal base is fitted. and a ceramic base on which multilayer wiring is formed, and each of the plurality of semiconductor device subassemblies is fitted into the plurality of second holes, and the wiring on the silicon wiring board and the ceramic base are respectively fitted into the plurality of second holes. A semiconductor device characterized in that multi-layer wiring is connected by wires. 2. The semiconductor device according to claim 1, wherein the compound semiconductor is gallium arsenide. 3. The semiconductor device according to claim 2, wherein the metal base is made of a material having a coefficient of thermal expansion similar to that of gallium arsenide. 4. The semiconductor device according to claim 3, wherein the metal base is made of a copper-tungsten alloy. 5. The side wall of the first hole is at an angle of 54.7° with respect to the horizontal plane.
2. The semiconductor device according to claim 1, wherein the semiconductor device has a crystal orientation (111) plane forming an angle of . 6. The semiconductor device according to claim 1, wherein the length of one side of the silicon wiring board is shorter than the length of one side of the second hole of the ceramic wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62123292A JPS63288036A (en) | 1987-05-20 | 1987-05-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62123292A JPS63288036A (en) | 1987-05-20 | 1987-05-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63288036A true JPS63288036A (en) | 1988-11-25 |
Family
ID=14856934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62123292A Pending JPS63288036A (en) | 1987-05-20 | 1987-05-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63288036A (en) |
-
1987
- 1987-05-20 JP JP62123292A patent/JPS63288036A/en active Pending
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