JPS63287889A - Display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to graph ink display devices and displays for workstations and other OA and FA applications, and in particular, to a display with a graph ink display function capable of displaying multiple windows. This invention relates to a device that enables display.

[Summary of the invention]

The present invention synchronizes the display positions of a plurality of windows on a display, the display priority of each window, and the generation of a read address for reading display information from an image memory with the scan cycle of the display. By doing this, it is now possible to display multiple windows.

[Conventional technology]

With the recent development of graph ink display devices, several windows are prepared on the screen of the display device, and it is possible to proceed with the processing of several display devices simultaneously on one display device. Window systems have come into use.

The currently mainstream multi-window systems use software to create a multi-window display state by using the overwriting effect of image memory on an image memory that corresponds one-to-one with the screen, and then display This is achieved by reading out all the information in the image memory and displaying it as the device scans.

[Problem that the invention seeks to solve]

When realizing multi-windows using the conventional method, if the priority order or display position of the currently displayed window is changed, the window information in the image memory must be rewritten. Therefore, the load on the processor increases and the processing capacity decreases.
This results in a decrease in responsiveness. Furthermore, in order to prevent image disturbance during the rewriting period, it is necessary to rewrite the image outside the display period. Normally, the time outside the display period of a CRT is as short as about 16 m5, so if you try to rewrite during this period, the rewriting period will become redundant, which is not preferable. A double buffer method has already been implemented as a method for shortening this period, but since it is necessary to prepare double the image memory, the amount of hardware increases.

Therefore, it is necessary to provide a multi-window system that has less influence on the processor load and has good responsiveness.

[Means for solving problems]

In order to solve the conventional problems, the present invention provides a display device with means for storing the display positions of a plurality of windows and generating the display timing of the windows in synchronization with the scanning of the display; means for generating an address for each window on the image memory in which display information for each window is stored in synchronization with timing; Means for selecting the display timing of the window with the highest priority according to the priority order, and selecting an address corresponding to the window with the highest priority from the addresses of each of the above-mentioned windows according to the above-mentioned display timing. means for generating an interrupt request signal for the image memory based on the display timing of the window; means for controlling the phase of the latched address and the interrupt request signal; means for storing a microprogram for controlling operations of a series of units; and means for controlling and reading addresses of the microprogram;
The configuration includes means for controlling transmission of control information to each unit.

[Effect]

The window display timing generation means described above generates display timing for each of a plurality of overlapping windows, and the window address generation means described above includes:
The means for generating an address on the image memory in which the display information of each window is stored in synchronization with the display timing of the window, and for selecting the display timing of the window, is configured for each of the plurality of windows. The means for selecting the display timing of the window with the highest priority from the display timings of the window and latching the address described above selects the display timing of the window with the highest priority from the display timings of the respective windows by the display timing selection means. , the means for generating the above-mentioned interrupt request by selecting or timing, generates a read request signal for the image memory from the display timing of the window, and the means for performing the above-mentioned phase control includes the above-mentioned latch. The above-mentioned microprogram storage means controls the phase of the received address and the above-mentioned interrupt request signal, and
A microprogram for controlling the operations of the series of units is stored, and the address control and control information transmission means described above controls the read address of the microprogram and transmits the control information of the series of units.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure shows a configuration diagram of a display device according to the present invention.

In the figure, control line a is a data bus that exchanges data between the graphics processor that controls the entire display system of the graph ink display and this unit, and reads and writes from and to the registers and memory inside this unit. be exposed. The register write control device 1 controls writing of a program to the control program memory 2, read control, and initialization of each register inside the window timing generation device 4, window priority control device 6, and address generation device 5. Do it via

ttdl? Wholesale program memory 2 transmits a control program to sequencer 3 via bus d. The sequencer 3 inputs a read address to the control program memory 2 through a control line e according to the status inputs inputted as control lines c, t, and u, and also inputs a read address to the control program memory 2 through a control line e, and also inputs a window timing generator 4, a window priority controller 6, and a window priority controller 6. , an execution control signal is input to the read request signal generator 9 and the address generator 5 through control lines e and f. The window timing generator 4 calculates parameters stored in internal registers according to execution control instructions from the sequencer 3, generates window display timing, and transmits the window timing to the sequencer 3 and window priority controller 6 through a control line C. introduce.

The address generator 5 calculates the parameters stored in the internal register according to the execution control command from the sequencer 3, generates a read address for the image information in the window, and transmits the address to the address latch 7 via the bus i. . The window priority control device 6 generates a new window display timing according to the display timing generated by the window timing generation device 4 and the window priority stored in the internal register, and sends a control line g to the read request signal generation device 9. Enter through.

It also generates a window address latch timing and inputs it to the address latch 7 via the control line g. The address latch 7 latches the address generated by the address generator 5 in accordance with the address latch timing generated by the window priority control device 6. The output of the latch is transmitted to pipeline register 8 through bus j. The read request signal generating device 9 generates a read request according to the display timing generated by the window priority control device 6, and transmits the read request to the image memory control device 10 through the control line l. Pipeline register 8 controls the phase of the read request signal generated by read request signal generator 9 and the address from address latch 7 . The address output after phase control is input to the image memory control device 10 via bus k. The image memory control device 10 receives the read request signal and the read address and outputs the read address for the image memory 11 through the control line n. The image memory 11 reads the image data at the address indicated by the read address and inputs it to the read shift register 12 via the control line O. The shift register 12 converts the image data read out in parallel from the image memory 11 into serial data and stores it in a lookup table (hereinafter referred to as LUT).
)13.

The LUT 13 adds information such as color and brightness to the input image data and inputs the data to the CRT 13 via the signal line q. The CRT 13 displays image data.

An example of multi-window display on the display screen of CRT13 with the above configuration, parameters for generating window timing, horizontal synchronization signal (hereinafter referred to as Hsync) and vertical synchronization signal (hereinafter referred to as Vsync), which are the basic signals for display display timing. Figure 2 shows the relationship between The figure shows four windows W1 to W on the display area.
4 is the priority W1 >W2 >W3 >W4 (> is
(The left side has higher priority than the right side.) This is a multi-window display. Parameter VDW
I to VDW4 set the number of rasters from the rise of Vsync to the raster immediately before the display start scanning line (hereinafter referred to as raster) of each window. Since the vertical back porch is given as a raster number, it is included in the parameters.

HDWI to HDW4 set the number of words from the rise of Hsync to the display start position of each window. The bank pouch on the horizontal side can be divided into words. In this example, 32 pixels are calculated as one word, and 60H
Since a no-increase display device is used, the pixel display rate is 9.3 nsec/pixel.
This was realized at a speed of approximately 300IIIB/word.

It goes without saying that this is possible even if the pixel rate changes. The parameter W1y=W4y sets the vertical display width of each window in terms of the number of rasters. Parameters Wlx-W4x set horizontal parameters of each window in word units.

For the sake of simplicity, we will focus on one window W1 and explain how to control parameters for displaying the window. Each parameter is loaded in advance into the window timing generator 4 and the address generator 5 from a microprocessor through the hash a during the Vsync period.

Furthermore, a microprogram for controlling each internal block is loaded from a microprocessor or the like into the control program memory 2 through bus a before the apparatus starts operating.

For the sake of simplicity, we will focus on one window W1 and explain the parameter control method for displaying the window. In Figure 2,
After the vertical synchronization signal Vsync rises, set VDWI to H.
Countdown is performed once every time during the sync "L" period. This is the control of the loop 4.5 in FIG. When VDWI becomes zero, HDWI is counted down once every l word cycle from the next rising edge of Hsync. This is the control of the loop in FIG.
When D W'l becomes zero, Wlx is counted down by 1 every word cycle from the next word cycle. This is the control of the loop in FIG. 311. Wl
While x is being counted down, the window flag of window W1 is output. This is the control shown in FIG. 310. When Wlx becomes zero, calculations regarding the parameters of window W1 are not performed until the next Hsync. Hsyn
Wly is counted down by 1 while c is L, and Hsy
The same processing as described above is performed from the rise of nc to the rask where w1y=o with respect to HDWI, WIX, and window flags. This series of control is the control shown by the loops in FIGS. 7 to 10.

The above processing is executed by the window timing generator 4 shown in FIG. Further, the above parameter processing is shown in the flowchart of FIG. 3 as described above, and the two items of loading VDWI and Wly in the flowchart are
This figure shows the loading of parameters from registers to counters that count down parameters in the window flagging generator 4 shown in the figure.

The address generator 5 shown in FIG. 1 is loaded and stored in advance with the word-by-word address of the image memo January 1 in which data to be displayed in the first word of the window is stored. This address is called the window start address WSI. In the parameter processing in the window timing generator 4, the WS1
is incremented by 1 per word and output. When the window flag output stops, address calculation and output also stop. Furthermore, the first address on the next rask is calculated and held while the next Hsync is at L.

This address is incremented and output once per word during the window flag output period from the next cycle when HDWI becomes zero. By repeating the above processing until the rask where W1y becomes zero, all word addresses to be displayed on the window flag are generated and output in synchronization with raster scanning, and the image memory control device 10 and image memo are shifted from January 1 Register 12, LUT1
3, a window W1 is displayed on the CRT. Here, the image memory display device 1k shift register 1
2. The operations of the LUT 13, CRT, etc. are based on conventional techniques, so detailed explanations will be omitted.

Next, the operation of this device when the number of windows to be displayed becomes four will be explained. Internal clock generator 15 in FIG.
DCI and DC2 shown in FIG. 4 are outputted from. DCI is
This is the basic cycle of processing performed inside this device, and D
C2 is twice that cycle. DCI, DC2 is the first
The window timing generation bag M is output to the control line S in the figure.
4. Input to address generator 5, sequencer 3, etc.

Each window Wl, W2, W3 displayed in Figure 2
．． W4 consists of four cycles S1. S2. It is assigned to S3 and S4 and is processed in the same cycle every time. In this device, the fourth
As shown in the figure, Wl is assigned to Sl, W2 to S2, W3 to S3, and W4 to S4. The window timing generator 4 shown in FIG. 1 outputs a flag for the window that has become zero when the parameters that control the display position of each window, VDW and HDW shown in FIG. 2, become zero.

As for the flag of each window, Wl is WIF.

W2 is output as W2F, W3 as W3F, and W4 as W4F, as shown in FIG. 4, and their states are maintained during the display period on the scan line of the window. When the flag is output as shown in FIG. 4, it is a case where four windows are set to be displayed from the same position on the scan line. The window flag is notified to the sequencer 3 and the window priority control device 6 through the control line C. The sequencer 3 refers to the window flag input through the control line C and the control command notified from the control program memory 2 through the control line d, and generates the address generator 5.
-15= Notify the control command through the control line e. The address generator 5 generates a read address for the image memo January 1 in accordance with the control command input through the control line e and the control timing input through the control line S, DCI and DC2 in FIG. Generation of read addresses for each window is also allocated to four cycles determined by DCI and DC2. In this device, as shown in FIG. 4, the address processing cycle of W1 is AD1, and the address processing cycle of W2 is AD2. W3 is AD3. W4 is assigned to AD4, and in each cycle, the read address of the window corresponding to each cycle is calculated and output to the control line i. The output timing is shown in FIG. 4 ADEXC. The window priority control device 6 in FIG. 2 refers to the priority written in advance from the register write control device 1 through the control line and the window flag input from the control line C, Determine which window has the highest priority among the windows. Further, the device 6 generates an address latch signal for the determined window and notifies the address latch 7 through the control line e.

As shown in FIG. 4, the address latch signals are WILE for Wl, W2LE for W2, W3LE for W3,
In the case of W4, it becomes W4LE. One signal from each of these signals is output to the control line G in FIG. 3, and the address latch 7 receives the addresses ADI, AD2, . AD3. A.D.
Only the address of the window with the highest priority among the four is latched and output.

In FIG. 4, the address latch state is shown when Wl is the window with the highest priority. The ADL pline register 8 controls the timing of outputting the address input from the control line i to the image memory control device 10. A read request generating device 10 in FIG. 1 generates an image memory read request signal by referring to a window display start signal sent from a window priority control device 6 through a control line V, and controls the image memory through a control line l. Notify the device 10. The image memory control device IQ, the image memory If, the shift register 12, and the LUT 13 read out the information of the read address sent through the control line k according to the conventional technology, and notify it to the CRT 14 through the control line P.
displayed on the screen.

Multi-window display is realized by repeating the above process until the horizontal width WX and vertical width of each window, that is, the number Wy of scan lines included in the window, become zero.

The window timing generator 4 and the address generator 5 have Wl, W2 . W3. It has means for independently storing the timing and address of each W4, and each has an independent cycle as shown in Figure 4, so even if the windows overlap, they will not affect each other. Multi-window display can be achieved without any problems.

〔Effect of the invention〕

By using the multi-window generation means described above, the contents of the window can be generated as in the prior art.

Multi-window display is easily possible without rewriting the contents of the image memory every time the size, position, priority, etc. are changed. Thereby, the CPU load can be greatly reduced compared to the conventional technology.

In addition, by controlling the generation of each window independently, even when large and small windows overlap as shown in Figure 1, and a small window is included in a large window, the size of several Rosemeadows, Since the display position etc. can be changed, the time required to rewrite the parameters is short, and since rewriting is possible regardless of the display period or non-display period, the software load is further reduced.

In addition, as mentioned above, the processing cycle for each window is divided and the independent storage of parameters eliminates the need to store addresses for hidden window parts and recalculate addresses, making the H/W itself complicated. This will help reduce problems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a display example of the present invention and the relationship between parameters and display windows used in the embodiment, and FIG. FIG. 4 is a flowchart showing the operation sequence in the case of only window W1, and FIG. 4 is a timing chart of main signals related to window control of this device. ■...Register write control device 2...Control program memory 3...Sequencer 4...Window timing generator 5...Address generator 6...Window priority control device 7...Address latch 8... Pipeline register 9... Read request signal generator 10... Image memory control device 11... Image memory 12... Shift register 13... LUT (lookup table) 14...
・CRT I5...Internal clock generator or higher

Claims (1)

[Claims] The content of the image memory that stores and holds various display information is read out in synchronization with the scanning cycle of the display, and the display positions of a plurality of windows are stored on the display. means for generating a display timing for the window in synchronization with the scanning of the display; and each window on the image memory, in which display information for each window is stored in synchronization with the display timing of the window. means for generating an address of the window; means for holding the priorities of the plurality of windows and selecting the display timing of the window with the highest priority according to the display timing of the windows and the priority; means for latching an address corresponding to the window with the highest priority from the window address according to the display timing described above; means for generating a read request signal for the image memory from the display timing of the window; means for controlling the phase of the latched address of the latched address and the aforementioned interrupt request signal; means for storing a microprogram for controlling the operations of the aforementioned series of units; and means for controlling the address of the microprogram, reading and , means for controlling transmission of control information to each unit, and a display device characterized in that it is capable of performing multi-window display control in synchronization with the scanning cycle of the display.