JPS63287825A - Active matrix substrate plate - Google Patents

Active matrix substrate plate

Info

Publication number
JPS63287825A
JPS63287825A JP62123511A JP12351187A JPS63287825A JP S63287825 A JPS63287825 A JP S63287825A JP 62123511 A JP62123511 A JP 62123511A JP 12351187 A JP12351187 A JP 12351187A JP S63287825 A JPS63287825 A JP S63287825A
Authority
JP
Japan
Prior art keywords
wiring
wirings
transparent conductive
active matrix
matrix substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62123511A
Other languages
Japanese (ja)
Inventor
Mutsumi Matsuo
睦 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62123511A priority Critical patent/JPS63287825A/en
Publication of JPS63287825A publication Critical patent/JPS63287825A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the correct decision of a short circuiting portion by constituting one sides of a 1st and a 2nd wirings of an electrically transparent conductive film in the neighbourhood of the crossing part of the 1st and the 2nd wiring respectively. CONSTITUTION:The 1st wiring is constituted of a timing line 2 and a common film 3 for building image element capacity, and the 2nd wiring is constituted of a video wiring. The 2nd wiring is arranged at an upside of the 1st wiring, and is composed of the transparent electrode film in the neighbourhood of the crossing part to facilitate an appearance inspection from the surface of a substrate. Accordingly, the video wiring 2 is constituted of two layer structures of the electrically transparent conductive film 15 and a metallic thin film 16. Thus, the appearance inspection about whether the short circuiting of the 1st and the 2nd wirings occurs in the crossing part of said wirings or not, or what place the short circuiting occurs, is easily effected, without remarkably reducing the wiring resistance of the title plate, by constituting at least one side of the 1st and the 2nd wirings of the electrically transparent conductive film in the neighbourhood of the crossing part respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁基板上に薄膜トランジスターを形成した
アクティブマトリックス基板の構造に閃する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to the structure of an active matrix substrate in which thin film transistors are formed on an insulating substrate.

〔従来の技術〕[Conventional technology]

近年、絶縁基板上に堆積した半導体薄膜を、能動領域と
して用いたMO3型薄膜トランジスターは、液晶パネル
の光シヤツターのスイッチとして用いられている。
In recent years, MO3 type thin film transistors, which use a semiconductor thin film deposited on an insulating substrate as an active region, have been used as optical shutter switches for liquid crystal panels.

第3図は、従来の薄膜トランジスターを用いたアクティ
ブマトリックス基板の模式図である。1(S−、St・
・・)は、データ線、2 (G、、G。
FIG. 3 is a schematic diagram of an active matrix substrate using conventional thin film transistors. 1 (S-, St.
) is the data line, 2 (G,,G.

・・・)はタイミング線である。3 (C,、C,・・
・)は、画素容量作り込み用コモン腺であり、液晶がつ
くる画素容量が少ない場合、画素容量に付加的容量をつ
けて、保持特性を改善することを目的とする定電位線で
ある。データ線1の信号は、タイミング腺2の信号によ
り、薄膜トランジスター4を介して、各画素電極5に書
き込まれる。
) is a timing line. 3 (C,,C,...
・) is a common gland for building pixel capacitance, and is a constant potential line that aims to add additional capacitance to the pixel capacitance and improve retention characteristics when the pixel capacitance created by the liquid crystal is small. The signal on the data line 1 is written to each pixel electrode 5 via the thin film transistor 4 in accordance with the signal on the timing line 2 .

第4図は、前記アクティブマトリックス基板の一部の構
造平面図であり、第5図は、第4図のb−b’の構造断
面図である。
FIG. 4 is a structural plan view of a part of the active matrix substrate, and FIG. 5 is a structural cross-sectional view taken along line bb' in FIG. 4.

薄膜トランジスター4は、透明ガラス基板6上に多結晶
シリコン薄膜7を堆積してパターン形成する工程、ゲー
ト絶縁膜8、ゲート金属薄膜を堆積し、ゲート電極9及
びタイミング!!i!2をパターン形成する工程、前記
ゲート電極9をマスクにしてP型あるいはN型不純物の
イオン打込みをしてソース領域10、ドレイン領域11
を形成する工程、層間絶縁膜12を堆積する工程、金属
薄膜を堆積して画素容量作り込み用コモン腺3をパター
ン形成する工程、画素容量作り込み川の絶縁膜13を積
層し、コンタクトポール14を形成する工程、透明導電
膜を被着し、画素電極4をパターン形成する工程、金属
薄膜を堆積し、データ1illをパターン形成する工程
とからなる。
The thin film transistor 4 consists of a process of depositing and patterning a polycrystalline silicon thin film 7 on a transparent glass substrate 6, depositing a gate insulating film 8, a gate metal thin film, a gate electrode 9, and timing! ! i! 2, using the gate electrode 9 as a mask, ions of P-type or N-type impurities are implanted to form a source region 10 and a drain region 11.
a step of depositing an interlayer insulating film 12; a step of depositing a metal thin film and patterning the common gland 3 for forming the pixel capacitance; laminating the insulating film 13 for forming the pixel capacitor; , a step of depositing a transparent conductive film and patterning the pixel electrode 4, and a step of depositing a metal thin film and patterning the data 1ill.

〔発明が解決しようとする問題点〕 しかし、前述の従来技術により作製したアクティブマト
リックス基板において、欠陥f22iT%をレーザーに
よって修正する場合、次のような不具合を生ずる。
[Problems to be Solved by the Invention] However, when the defect f22iT% is repaired using a laser in the active matrix substrate manufactured by the above-mentioned conventional technique, the following problems occur.

第1は、データ線1とタイミング線2の短絡による欠陥
の修正の場合である。 その要因としては、データ、I
IIとタイミング線2の交差部の層間絶縁膜にピンホー
ルがあって短絡する場合と、薄膜トランジスター3のソ
ース領域10とゲート電極9の間のゲート絶縁膜8がピ
ンホールや静電破壊等により短絡する場合が考えられる
。そこでどちらのモードで不良になっているかは、顕微
鏡による外観検査で判断する必要がある。このとき薄膜
トランジスターの弱い静電破壊や、層間絶縁膜の小さな
ピンホール、特に、段差部でのクラックによるデータ!
1とタイミングil!i!2の短絡等は、データ線、タ
イミング線が共に金属配線のとき見つけにくいため、適
切な判断ができないという問題点を有する。
The first case is the correction of a defect due to a short circuit between the data line 1 and the timing line 2. The factors include data, I
A short circuit may occur due to a pinhole in the interlayer insulating film at the intersection of II and the timing line 2, and a pinhole or electrostatic breakdown in the gate insulating film 8 between the source region 10 and gate electrode 9 of the thin film transistor 3 may cause a short circuit. A short circuit may occur. Therefore, it is necessary to determine which mode is causing the defect through an external inspection using a microscope. At this time, data is caused by weak electrostatic discharge damage in thin film transistors, small pinholes in interlayer insulating films, and especially cracks at stepped areas!
1 and timing il! i! It is difficult to detect a short circuit or the like in No. 2 when both the data line and the timing line are metal wiring, so there is a problem that an appropriate judgment cannot be made.

第2は、データ線1と画素容量作り込み用コモ/腺3の
短絡による欠陥の修正の場合である。画素容量作り込み
用コモン!!!3は一定電位であるため、データ、II
Iとどの交差部で短絡しているかを見つけるのは電気的
に、困難であり、データ線にそって短絡箇所を見つけ出
す必要がある。この場合も、小さなピンホール等による
短絡は、データ線・タイミング線が共に金属配線のとき
見つけにくいという問題点を有する。
The second case is the case of correcting a defect due to a short circuit between the data line 1 and the pixel capacitance building connector 3. Common for building pixel capacitance! ! ! 3 is a constant potential, so data, II
It is electrically difficult to find out which intersection with I is short-circuited, and it is necessary to find the short-circuit location along the data line. In this case as well, short circuits due to small pinholes etc. are difficult to detect when both the data line and the timing line are metal wiring.

そこで本発明は、とのような問題点を解決するもので、
その目的とするところは、短絡箇所を正しく判別できる
アクティブマトリックス基板を提供するところにある。
Therefore, the present invention solves the following problems.
The purpose is to provide an active matrix substrate that can correctly identify short circuit locations.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のアクティブマトリックス基板は、複数本の平行
な第1の配線と直交する複数本の平行な第2の配線を有
し、前記第1と第2の配線の交差部近傍に、各画素電極
を駆動する薄膜トランジスターを配置したアクティブマ
トリックス基板において、前記第1と第2の配線の少な
くとも一方の配線を、前記第1と第2の配線の交差部、
近傍で透明導電膜とすることを特徴とする。
The active matrix substrate of the present invention has a plurality of parallel second wirings orthogonal to a plurality of parallel first wirings, and each pixel electrode is provided near the intersection of the first and second wirings. In an active matrix substrate on which a thin film transistor for driving is arranged, at least one of the first and second wirings is connected to an intersection of the first and second wirings;
It is characterized by a transparent conductive film in the vicinity.

〔作用〕[Effect]

本発明の上記の構成によれば、第1の配線と、第2の配
線の少なくとも一方が、交差部近傍で透明導電膜からな
っているため、顕微鏡による外観検査により、交差部の
居間絶縁膜に小さな異常があれば、容易に不良箇所を同
定できる。外観検査は、第1の配線が第2の配線よりも
下側にあって第2の配線の一部が透明導電膜からなる場
合、基板の表側から観察し、第1の配線の一部が透明導
電膜からなる場合は、基板の裏側から観察すればよい。
According to the above configuration of the present invention, since at least one of the first wiring and the second wiring is made of a transparent conductive film near the intersection, it is possible to detect that the living room insulating film at the intersection is visually inspected by a microscope. If there is a small abnormality, the defective location can be easily identified. When the first wiring is located below the second wiring and a part of the second wiring is made of a transparent conductive film, the appearance inspection is performed by observing from the front side of the substrate and checking whether a part of the first wiring is If it is made of a transparent conductive film, it may be observed from the back side of the substrate.

〔実施例〕〔Example〕

第1図は本発明のアクティブマトリックス基板の一部の
構造平面図であり、第2図は、第1図の1−a′の構造
断面図である。
FIG. 1 is a structural plan view of a part of the active matrix substrate of the present invention, and FIG. 2 is a structural cross-sectional view taken along line 1-a' in FIG.

第1の配線は、タイミング線2及び画素容量作り込み用
コモン腺3であり、第2の配線は、ビデオ線である。本
実施例では第2の配線は、第1の配線よりも上側にあり
、基板表面より外観検査しやすいように第2の配線を交
差部近傍で透明電極膜とした。したがってビデオ線2は
、透明導電膜15と金属薄膜16の二層構造からなって
いる。
The first wiring is a timing line 2 and a common gland 3 for building pixel capacitance, and the second wiring is a video line. In this example, the second wiring is located above the first wiring, and a transparent electrode film is formed on the second wiring near the intersection so that the appearance can be inspected more easily than the substrate surface. Therefore, the video line 2 has a two-layer structure of a transparent conductive film 15 and a metal thin film 16.

具体的には、第2の配線層として透明導電膜とモリブデ
ンあるいはクロム等の金属を薄膜を二層に積層して、フ
ォトリソグラフィーでビデオ線を2層同時にパターン形
成した後、第1の配線の上に位置する金属薄膜を再度フ
ォトリングラフイーで除去すれば、容易にできる。他の
方法としては、透明導電膜を堆積してフォトリソグラフ
ィーでビデオ線をパターン形成した後、ビデオ線上で、
金属薄膜を堆積したい部分のみレジストを除去し金属簿
膜を堆積した後レジストはくすしてパターン形成するり
フトオフ法や、透明導電膜を堆積してフォトリソグラフ
ィーでビデオ線をパターン形成した後、絶縁膜を堆積し
、金属薄膜を堆積したい部分のみ絶縁膜を除去し、無電
解メッキ法によりニッケル等のメッキ膜を透明導電膜上
に付着させるメッキ法が考えられる。
Specifically, a transparent conductive film and a thin film of metal such as molybdenum or chromium are laminated in two layers as the second wiring layer, and the video lines are patterned in the two layers simultaneously using photolithography, and then the first wiring layer is formed. This can be easily done by removing the overlying metal thin film again using photophosphorography. Another method is to deposit a transparent conductive film and photolithographically pattern the video lines, and then
After removing the resist only in the area where the metal thin film is desired to be deposited and depositing the metal film, the resist is wiped off to form a pattern, or a transparent conductive film is deposited and video lines are patterned using photolithography, and then insulated. A plating method may be considered in which a film is deposited, the insulating film is removed only from the portion where the metal thin film is desired to be deposited, and a plating film of nickel or the like is deposited on the transparent conductive film by electroless plating.

逆に、第1の配線の一部を透明導電膜とする場合には、
前述と同様な方法で第一の配線を形成すると共に、基板
裏面より外観検査をすればよい。
Conversely, when a part of the first wiring is made of a transparent conductive film,
The first wiring may be formed in the same manner as described above, and the appearance may be inspected from the back surface of the substrate.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、第1と第2の配線の
少なくとも一方の配線を、交差部近傍で透明導電膜とす
ることで、配線抵抗を著しく低下せずに、かつ第1の配
線と第2の配線の短絡が、交差部であるか否か、あった
場合にはどの位置かを外観検査にて容易に判断できるた
め、レーザーによる欠陥修正が、適切にできるという効
果を有する。特に、液晶パネルに組んでからレーザー修
正をする場合、通常データ線及びタイミング線に対向す
る対向基板上に、遮光層があるため、交差部近傍は、対
向基板側から外観検査ができない。
As described above, according to the present invention, at least one of the first and second wirings is made of a transparent conductive film in the vicinity of the intersection. It is possible to easily determine by visual inspection whether a short circuit between the wiring and the second wiring is at an intersection, and if so, where it is located, so that defects can be corrected appropriately using a laser. . In particular, when performing laser correction after assembly into a liquid crystal panel, there is usually a light-shielding layer on the counter substrate facing the data lines and timing lines, so it is impossible to visually inspect the vicinity of the intersection from the counter substrate side.

そのためアクティブマトリックス基板の裏面から外観検
査する必要があり、第1の配線が第2の配線より下に位
置するときは、第1の配線の交差部近傍を透明導電膜と
すると、不良箇所の同定が、はっきりできるという長所
がある。
Therefore, it is necessary to conduct a visual inspection from the back side of the active matrix substrate, and when the first wiring is located below the second wiring, if a transparent conductive film is used near the intersection of the first wiring, it is possible to identify the defective location. However, it has the advantage of being clear.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明のアクティブマトリックス基板の一部
の構造平面図であり、第2図は、第1図a−a’の構造
断面図である。 第3図は、従来の薄膜トランジスターを用いたアクティ
ブマトリックス基板の模式図である。 第4図は、従来のアクティブマトリックス基板の一部の
構造平面図であり、第5図は、第4図b−b’の構造断
面図である。 1・・・データ線 2・・・タイミング線 3・・・画素容量作り込み用コモン腺 4・・・薄膜トランジスター 5・・・画素電極 6・・・透明ガラス基板 7・・・多結晶シリコン薄膜 8・・・ゲート絶縁膜 9・・・ゲート電極 10・・・ソース領域 11・・・ドレイン領域 12・・・層間絶縁膜 13・・・画素容量作り込み用絶縁膜 14・・・コンタクトホール 15・・・透明導電膜 16・・・金属薄膜 以  上
FIG. 1 is a structural plan view of a part of the active matrix substrate of the present invention, and FIG. 2 is a structural cross-sectional view taken along line aa' in FIG. FIG. 3 is a schematic diagram of an active matrix substrate using conventional thin film transistors. FIG. 4 is a structural plan view of a part of a conventional active matrix substrate, and FIG. 5 is a structural cross-sectional view taken along line bb' in FIG. 1... Data line 2... Timing line 3... Common gland for building pixel capacitance 4... Thin film transistor 5... Pixel electrode 6... Transparent glass substrate 7... Polycrystalline silicon thin film 8... Gate insulating film 9... Gate electrode 10... Source region 11... Drain region 12... Interlayer insulating film 13... Insulating film for building pixel capacitance 14... Contact hole 15 ...Transparent conductive film 16...Metal thin film or more

Claims (3)

【特許請求の範囲】[Claims] (1)複数本の平行な第1の配線と直交する複数本の平
行な第2の配線を有し、前記第1と第2の配線の交差部
近傍に、各画素電極を駆動する薄膜トランジスターを配
置したアクティブマトリックス基板において、前記第1
と第2の配線の少なくとも一方の配線を、前記第1と第
2の配線の交差部近傍で透明導電膜とすることを特徴と
するアクティブマトリックス基板。
(1) A thin film transistor having a plurality of parallel second wirings orthogonal to a plurality of parallel first wirings, and driving each pixel electrode near the intersection of the first and second wirings. In the active matrix substrate on which the first
An active matrix substrate characterized in that at least one of the first and second wirings is made of a transparent conductive film near the intersection of the first and second wirings.
(2)前記第1と第2の配線は、データ線とタイミング
線であることを特徴とする特許請求の範囲第一項記載の
アクティブマトリックス基板
(2) The active matrix substrate according to claim 1, wherein the first and second wirings are a data line and a timing line.
(3)前記第1と第2の配線は、データ線とタイミング
線のどちらか一方と、画素容量作り込み用コモン線であ
ることを特徴とする特許請求の範囲第一項記載のアクテ
ィブマトリックス基板。
(3) The active matrix substrate according to claim 1, wherein the first and second wirings are one of a data line and a timing line, and a common line for building pixel capacitance. .
JP62123511A 1987-05-20 1987-05-20 Active matrix substrate plate Pending JPS63287825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62123511A JPS63287825A (en) 1987-05-20 1987-05-20 Active matrix substrate plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62123511A JPS63287825A (en) 1987-05-20 1987-05-20 Active matrix substrate plate

Publications (1)

Publication Number Publication Date
JPS63287825A true JPS63287825A (en) 1988-11-24

Family

ID=14862420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62123511A Pending JPS63287825A (en) 1987-05-20 1987-05-20 Active matrix substrate plate

Country Status (1)

Country Link
JP (1) JPS63287825A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453856A (en) * 1992-12-10 1995-09-26 Goldstar Co., Ltd. Liquid crystal display with gate lines connected with a doped semiconductor layer where they cross data lines

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453856A (en) * 1992-12-10 1995-09-26 Goldstar Co., Ltd. Liquid crystal display with gate lines connected with a doped semiconductor layer where they cross data lines

Similar Documents

Publication Publication Date Title
KR100244449B1 (en) Liquid crystal display having shorting bar for testing thin-film transistor and manufacturing method thereof
JP2001059976A (en) Liquid crystal display device and its manufacturing method
JP2000162647A (en) Thin-film transistor substrate for liquid crystal display device and its production
KR0139319B1 (en) Liquid crystal display device having double line and multi-transistor in one pixel
KR20020004253A (en) Liquid crystal display device and method for forming an array substrate
US6924852B2 (en) Thin film transistor array substrate for preventing static electricity and manufacturing method thereof
EP0605176B1 (en) An active matrix type liquid crystal display panel and a method for producing the same
CN101615594A (en) The manufacture method of thin-film transistor array base-plate
JPS61249078A (en) Matrix type display unit
US5466620A (en) Method for fabricating a liquid crystal display device
KR100686235B1 (en) A panel for liquid crystal display
CN101236953A (en) Thin film transistor array base plate and its making method
JPS63287825A (en) Active matrix substrate plate
CN103605242A (en) Array substrate, method for manufacturing same and display device
KR20070036915A (en) Liquid crystal display, thin film transistor panel and fabricating method of the same
JPH03171034A (en) Liquid crystal display device and production thereof
JP3929564B2 (en) Liquid crystal display panel and manufacturing method thereof
JP2000241833A (en) Matrix type wiring board
JPH01134345A (en) Active matrix substrate
JPH01303415A (en) Liquid crystal display device
KR100318540B1 (en) Liquid Crystal Display and a Manufacturing Method thereof
KR100719916B1 (en) Tft-lcd with means for repairing line open and interlayer short
JPH022522A (en) Manufacture of tft panel
JPH0259727A (en) Active matrix substrate
JPH02264224A (en) Manufacture of active matrix substrate capable of spot defect detection and repair