JPS63287128A - Ds 3-interface circuit for digital cross connection - Google Patents

Abstract

PURPOSE:To miniaturize the device while eliminating the need for a spatial switch by applying stuff synchronization to a digital signal of an asynchronous system at a cross connection level respectively and multiplexing the result to the high order group again in the unit of frames. CONSTITUTION:A DS3 signal sent from a signal input line 1 of a transmission line is branched into 7 DS2 signals by a separation circuit 10 and subjected to destuff processing. Then the DS2 signals are inputted to separation circuits 20-1-20-7, where the signals are subjected to destuff processing into 28 DS1 signals. Moreover, the DS1 signals separated into 28 signals are subjected to stuff synchronization in the unit of each DS1 by a multiplex circuit 30, and 28 data are arranged in the unit of one stuff frame length at every DS1 serially and the result is outputted to a signal output line 2 as a DS3' signal. Moreover, since the synchronizing clock DS3' CLK is synchronized with other interface circuit, it is supplied from a common clock source.

Description

[Detailed description of the invention] [Industrial application field] The present invention is a cross-connect system for digital transmission.

D for digital cross-connect for establishing synchronization between digital signals, especially when interconnecting time-division multiplexed digital signal transmission lines.
Regarding the S3 interface circuit.

[Conventional technology]

In recent years, with the expansion of the application area of digital communications, cross-connect methods have been developed to perform initial route settings for digital transmission lines, addition of lines in operation, service changes, and route changes in response to failures. In response, there are increasing demands in many aspects, such as miniaturization of equipment scale, reduction of line concentration space, labor saving in connection work, and diversification of switchable hierarchy levels (for example, compatibility with DS3 signals of North American digital hierarchy). There is.

This type of conventional cross-connect system for digital transmission uses a distribution rack equipped with a group of switches that change the interconnection (cross-connect) of multiple signal lines (for example, coaxial cables), and the switches are manually operated. This is a method that switches connections depending on the situation. There are two types of digital signals on the transmission line: synchronous signals that are synchronously multiplexed and asynchronous signals that are stuffed multiplexed.For asynchronous digital signals, a time switch is used to switch connections by switching time slots. Since there is no applicable technology, space switches that interconnect signal lines are used as the switch group of the distribution rack.

[Problem that the invention seeks to solve]

The above-mentioned conventional cross-connect system for digital transmission uses a space switch as a switching means for interconnecting transmission lines, which reduces the size of the device.

There is a problem in that it is impossible to fully meet the demands of saving line concentration space and diversifying switching units. In other words, while one-hour switches can be easily miniaturized by integrating circuits, There are limits to the miniaturization of switches. Furthermore, in order to multiplex switching units, it is necessary to decompose a high-order group into its component lower-order groups and switch connections in units of lower-order groups.In the conventional method using space switches,
The high-order group digital signal is decomposed into low-order groups by a separator and then guided to the distribution rack.The distribution rack exchanges the interconnections between the low-order groups, and then the low-order groups are converted into higher-order groups by the multiplexer. There is no choice but to adopt a multiplexed configuration.

As a result, it is necessary to provide a multiplexing device and a demultiplexing device in addition to the distribution rack, and the number of signal lines increases in order to guide the decomposed low-order group digital signals. Space savings become impossible.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems by performing stuff synchronization on asynchronous digital signals at the cross-connect level, and then multiplexing them into higher-order groups on a frame-by-frame basis. It is an object of the present invention to provide an interface circuit which can be applied and which can reduce the device size and wire concentration space compared to conventional ones.

Measures to solve problem C] According to the DS3 interface circuit of the present invention.

On the receiving side of the DS3 signal, once the 28
The DSI signals are separated into four main DSI signals, and each DSI level is stuff-synchronized again using an internal high-order group clock, and 28 pieces of data are arranged in series in units of 1 stuff frame length for each DS1. It is characterized by performing operations in the opposite direction.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, seven DS2 (6,312Mb/s
) is separated into signals and distuffed ≧.

Next, each DS2 signal is an M12DM of 20-1 to 20-7.
UX (separation circuit) K input, DSI (1,544M
b/s) and separated into 28 signals. In addition, 30 (Z
) Ml 3' MUX (Multiple circuit) each D81
Stuff is synchronized in units, and 28 pieces of data are arranged in series in units of 1 stuff frame length for each ID51.
It is output to the signal output line 2 as a D S 3' signal.

Further, the synchronization clock D S 3' CLK is supplied from a common clock source via the clock input line 3 in order to synchronize with other interface circuits. DS3
The signal sending circuit is constructed as a reverse circuit of FIG.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, D
81 units of stuff synchronized signals for every 1DS1
By arranging 28 pieces of data in series in units of stuff frame length and converting them to DS3' signals, it is possible to input them to the time division switch in units of DS3 and enable cross-connection at the DSI level. This reduces the equipment size and line concentration, and has a significant effect in making the equipment more compact and economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure, 1 is a signal input line. 2 is a signal output line, 3 is a clock input line, 10 is M23
DMUX, 20-1 to 20-7 are M12 DMUX
. 30 is M13'MUX.

Claims (1)

[Claims] 1. Suitable for interconnecting time-division multiplexed digital signal transmission lines and for establishing mutual synchronization of DS3 signals.
In the S3 interface circuit, on the receiving side of the DS3 signal, the DS3 signal is once separated into 28 DS1 signals by an M23 demultiplexing circuit and an M12 demultiplexing circuit, and stuff synchronized to each DS1 level again by an internal high-order group clock. , 28 pieces of data are arranged in series in units of 1 stuff frame length for each DS1, and DS3
A digital cross-connect DS characterized in that, on the signal sending side, the operation is opposite to that on the receiving side.
3 interface circuit.