JPS63285947A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63285947A JPS63285947A JP62121829A JP12182987A JPS63285947A JP S63285947 A JPS63285947 A JP S63285947A JP 62121829 A JP62121829 A JP 62121829A JP 12182987 A JP12182987 A JP 12182987A JP S63285947 A JPS63285947 A JP S63285947A
- Authority
- JP
- Japan
- Prior art keywords
- mark
- positioning
- semiconductor device
- semiconductor
- positioning mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 abstract description 4
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置製造に係り、特に感光性樹脂の焼き
付は露光工程に於いて使用される縮小投影型露光装置を
用いた半導体装置の製造方法に関するものである。Detailed Description of the Invention [Industrial Field of Application] The present invention relates to the manufacture of semiconductor devices, and in particular, the printing of photosensitive resin is applied to semiconductor devices using a reduction projection type exposure apparatus used in the exposure process. This relates to a manufacturing method.
従来、半導体装置製造に使用される縮小投影型露光装置
に於ける半導体基板の位置決め方法は、第２図に示すよ
うに半導体装置素子片間１０に配置されている位置決め
マーク６、７．８．９にレーザ光を当て反射光を検出す
る事により位置決めマーク部の位置を換算し半導体基板
の位置合せを行う方式であった。Conventionally, a method for positioning a semiconductor substrate in a reduction projection type exposure apparatus used for manufacturing semiconductor devices is to use positioning marks 6, 7, 8, . In this method, the position of the positioning mark portion is calculated by applying a laser beam to the laser beam 9 and detecting the reflected light, thereby aligning the semiconductor substrate.
′上述した従来の縮小投影型露光装置の位置合せマーク
検出方法では、半導体装置素子片間に配置された位置決
めマークに対して、数１０ミクロン離れた位置より、レ
ーザー光をスキャンさせ、位置決めマークの反射光を受
光し、半導体基板の位置合せを行うが、この場合、半導
体装置素子片間の下地状態が悪く数ケ所の反射光を発生
させたシ、あるいは、位置決めマーク近傍にある半導体
装置素子分離枠等のパターンを位置決めマークと誤認識
したりして半導体装置製造のフォ） ＩＪソグラフィ技
術に於いて、パターンの重ね合せ精度にばらつきを生じ
させ、作業能率を低下させたりしていた。'In the alignment mark detection method of the conventional reduction projection type exposure apparatus described above, a laser beam is scanned from a position several tens of microns away from a positioning mark placed between semiconductor device element pieces, and the positioning mark is detected. The reflected light is received and the semiconductor substrate is aligned, but in this case, the underlying condition between the semiconductor device element pieces is poor and the reflected light is generated in several places, or the semiconductor device element separation near the positioning mark is detected. In IJ lithography technology for manufacturing semiconductor devices, patterns such as frames may be mistakenly recognized as positioning marks, causing variations in pattern overlay accuracy and reducing work efficiency.
又、半導体装置素子片内へと位置合せマークを配置させ
ている半導体装置もあるが、佐々進行する半導体装置の
高集積化に伴危い、半導体装置素子片１個当りの面積も
１縮小化され、数工程に及ぶ工程の位置合せマークすべ
てを半導体素子片内へと配置するのは困難となって来た
。In addition, some semiconductor devices have alignment marks placed inside semiconductor device chips, but as semiconductor devices become increasingly highly integrated, the area of each semiconductor device chip is reduced by 1. As a result, it has become difficult to arrange all the alignment marks for several steps into a semiconductor chip.
本発明の縮小投影露光装置を用いた半導体装置の製造方
法は、半導体装置素子片内に配置された基点となる第■
の位置決めマークと半導体装置素子片間に配置された第
■の位置決めマークとの距離を記憶回路に記憶させ基点
となる第■の位置決めマークを検出した後、記憶された
第■、第■の位置決めマークの距離分だけステージ移動
させ、第■の位置決めマークを検出する事により半導体
基板の位置決めを行う事である。A method for manufacturing a semiconductor device using the reduction projection exposure apparatus of the present invention includes
The distance between the positioning mark and the second positioning mark placed between the semiconductor device element pieces is stored in the memory circuit, and after detecting the second positioning mark, which is the reference point, the stored positioning of the first and third positions is performed. The semiconductor substrate is positioned by moving the stage by the distance of the mark and detecting the second positioning mark.
〔実施例〕 次に本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を説明する為の半導体装置上
に描かれた位置決めマークの平面図である。FIG. 1 is a plan view of positioning marks drawn on a semiconductor device for explaining one embodiment of the present invention.
本実施例の半導体装置の製造方法は、特にレーザー光を
半導体基板上の位置決めマークへと照射し、前記位置決
めマークからの反射光を検出して半導体基板の位置決め
を行う縮小投影露光装置を用いた半導体装置の製造方法
に係シ、半導体装置素子片内Ａに配置された基点とがる
第■の位置決めマーク１と、半導体素子片間Ｂに配置さ
れた第■の位置決めマーク２との距離を予め記憶回路へ
と記憶させ、基点となる第■の位置決めマーク１を検出
した後、記憶された第■及び第■の位置決めマークの距
離分だけ移動させ、第■の位置決めマーク２を検出する
事で半導体基板の位置決めを行う方法である。The method for manufacturing a semiconductor device of this embodiment uses a reduction projection exposure apparatus that irradiates a laser beam onto a positioning mark on a semiconductor substrate and detects reflected light from the positioning mark to position the semiconductor substrate. Regarding the method of manufacturing a semiconductor device, the distance between the positioning mark 1 having a pointed base point and the positioning mark 2 located between the semiconductor device pieces B is determined. After storing the positioning mark 1 in advance in the memory circuit and detecting the positioning mark 1 serving as the reference point, the positioning mark 2 is moved by the distance between the stored positioning marks 2 and 2, and the positioning mark 2 is detected. This is a method for positioning a semiconductor substrate.
以上説明した様に・本発明は基点となる位置決めマーク
１を半導体素子片内Ａに配置した事により、従来、半導
体装置素子片間Ｂに配置された位置決めマーク６〜９を
基点として検出する時（第２図）に生じる半導体装置素
子片間Ｂの下地荒れの状態による誤検出又、半導体装置
素子片間枠１０との間隔がせまい為に生じる誤検出を防
止する事ができ、位置決め精度の向上２作業効率の向上
に期待がもてる。又、半導体装置素子片内Ａに配置する
基点となる位置決めマーク１は１ケ所で良く、この位置
決めマーク】を基点とし半導体素子片間ＢＫ配装される
第■〜第■の位置決めマーク２〜５を検出させ、半導体
基板の位置決めを行えば良い訳であυ、今後の高密度化
高縮小化の支障とはならない。As explained above, the present invention arranges the positioning mark 1, which serves as a reference point, within the semiconductor element piece A, so that when conventionally, the positioning marks 6 to 9 placed between the semiconductor device element pieces B are used as the reference point for detection. It is possible to prevent erroneous detection due to the rough state of the ground between the semiconductor device element pieces shown in FIG. Improvement 2 We can expect an improvement in work efficiency. Further, the positioning mark 1 that serves as the reference point to be placed within the semiconductor device element piece A may be placed at one location, and the positioning marks 2 to 5 placed between the semiconductor element pieces BK with this positioning mark as the reference point. It is sufficient to detect this and position the semiconductor substrate υ, and this will not be a hindrance to future high-density and high-reduction efforts.
第１図は本発明の半導体装置上に描かれた位置決めマー
クの平面図であり、第２図は従来技術を説明する為の平
面図である。
面図に於いて。
１・・・・・・基点となる位置決めマーク２〜５・・・
・・・第■〜第■の位置決めマーク６〜９・・・・・・
従来技術の基点となる位置決めマーク１０・・・・・・
半導体装置素子片枠
Ａ・・・・・・半導体装置素子片内
Ｂ・・・・・・半導体装置素子片間
である。FIG. 1 is a plan view of a positioning mark drawn on a semiconductor device of the present invention, and FIG. 2 is a plan view for explaining the prior art. In the front view. 1...Positioning marks 2 to 5 that serve as base points...
... No. ■ to ■ positioning marks 6 to 9...
Positioning mark 10, which is the base point of the conventional technology...
Semiconductor device element piece frame A...Inside the semiconductor device element piece B...Between the semiconductor device element pieces.
Claims (1)
、前記位置決めマークからの反射光を検出して、半導体
基板の位置決めを行う縮小投影露光装置を用いた半導体
装置の製造方法において、レーザー光を照射し半導体基
板の位置決めを行うマークが半導体素子片内に配置され
、該位置決めマークを基点として検出した後に半導体装
置素子片間に配置された位置決めマークを検出させ、半
導体基板の位置決めを行う事を特徴とする半導体装置の
製造方法。In a method for manufacturing a semiconductor device using a reduction projection exposure apparatus that irradiates a positioning mark on a semiconductor substrate with laser light and detects reflected light from the positioning mark to position the semiconductor substrate, irradiation of laser light is performed. A mark for positioning the semiconductor substrate is placed within the semiconductor element piece, and after detecting the positioning mark using the positioning mark as a reference point, a positioning mark placed between the semiconductor device element pieces is detected to position the semiconductor substrate. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62121829A JPS63285947A (en) | 1987-05-18 | 1987-05-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62121829A JPS63285947A (en) | 1987-05-18 | 1987-05-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63285947A true JPS63285947A (en) | 1988-11-22 |
| JPH0571166B2 JPH0571166B2 (en) | 1993-10-06 |
Family
ID=14820959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62121829A Granted JPS63285947A (en) | 1987-05-18 | 1987-05-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63285947A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5716889A (en) * | 1996-05-29 | 1998-02-10 | Mitsubishi Denki Kabushiki Kaisha | Method of arranging alignment marks |
| US6005294A (en) * | 1996-05-29 | 1999-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method of arranging alignment marks |
-
1987
- 1987-05-18 JP JP62121829A patent/JPS63285947A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5716889A (en) * | 1996-05-29 | 1998-02-10 | Mitsubishi Denki Kabushiki Kaisha | Method of arranging alignment marks |
| US6005294A (en) * | 1996-05-29 | 1999-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method of arranging alignment marks |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0571166B2 (en) | 1993-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI644384B (en) | Laser engraving device | |
| JP5346759B2 (en) | Substrate positioning method | |
| JPH09189519A (en) | Pattern detection method and device for aligning positions of mask and work | |
| JPS63285947A (en) | Manufacture of semiconductor device | |
| EP1091255A2 (en) | Method of aligning mask and workpiece in exposure device | |
| JP3157751B2 (en) | Dicing method for semiconductor substrate | |
| JPH0443407B2 (en) | ||
| JPS6246239A (en) | Apparatus for inspecting surface foreign matter | |
| JPH0672766B2 (en) | Position detector | |
| JPH07219209A (en) | Photomask | |
| KR100596270B1 (en) | Alignment mark and aligning method | |
| KR100834222B1 (en) | pre-alignment method of exposure device for semiconductor wafer | |
| JPH04287909A (en) | Alignment method of wafer | |
| JPS60246645A (en) | Alignment method for semiconductor wafer chip | |
| JPS63307736A (en) | Method of processing by using ion beam | |
| JPS6369226A (en) | Particle-beam exposure device | |
| KR100596280B1 (en) | Apparatus and method for simplication of prealignment in overlay measurement | |
| JPS61256635A (en) | Manufacture of semiconductor device | |
| JPH02183511A (en) | Manufacture of semiconductor device | |
| KR0186077B1 (en) | External exposure method of semiconductor wafer | |
| JPS6490527A (en) | Manufacture of semiconductor device | |
| KR920006747B1 (en) | Lithography process | |
| JPH0565048B2 (en) | ||
| JPH0267717A (en) | Reduced projection type aligner | |
| JPS6188525A (en) | Manufacture of integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |