JPS63284675A - Vector data processor - Google Patents

Abstract

PURPOSE:To shorten the processing time of a mask register decoding instruction by counting the number of values of the mask bits requiring execution of arithmetic operation before this arithmetic operation is carried out. CONSTITUTION:The contents of vector registers 100-1-100-4 are successively read out in a vector register selecting circuit 101 and inputted to a comparison input register 102 to be compared with condition codes by a comparator 103. The results of said comparison are outputted from the comparator 103 and held by a mask register 200 as mask bits. At the same time, a '0' count circuit 303 counts the number of continuous values requiring no arithmetic operation which are included in those produced mask bits. While a '1' count circuit 305 counts the number of values requiring the operation. These counted pieces of value are inputted to a mask buffer 201, a '0' count buffer 300 and a '1' count buffer 301 respectively and then read out and used at the time of an operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector data processing device having a vector mask bit generation circuit.

[Conventional technology]

As the field of application of computers expands, the demand for high-speed data processing capabilities of computers is expanding without limit. Supercomputers are being actively developed to meet these demands in the field of scientific and technical computing. In a supercomputer, a huge amount of data to be processed is treated as vector data, that is, a collection of ordered one-dimensional data (element data), and a vector data processing device processes this at high speed.

Conventionally, this type of vector data processing device uses vector mask bits (
A mask register is provided to hold bits (hereinafter abbreviated as mask bits). Generation of mask bits is realized by executing a mask bit generation instruction having a designation of a vector register holding element data to be subjected to mask bit generation and a condition code designation for mask bit generation. The generated mask bit is originally a beep that indicates whether or not the operation is allowed, so if the value of the mask bit indicates that the operation is not necessary, there is no need to transfer the corresponding element data to the arithmetic unit. do not have. Therefore, before issuing an instruction to execute an operation, the instruction decodes the contents of the mask register and detects how many pieces of element data that do not need to be executed continue from the element data to be transferred to the arithmetic unit first. Something was being done.

Similarly, the number of pieces of element data that need to be executed has been detected by explaining the contents of a mask register using instructions.

[Problem that the invention seeks to solve]

In order to speed up calculations, decoding the contents of the mask register with an instruction prior to the instruction that executes the calculation itself achieves the purpose as a means of speeding up, but it is not possible to read the contents of the mask register. There is a drawback that it takes a long time to process an instruction to decode and detect the number of element data that does not need to be executed, and a long time to process an instruction to detect the number of element data that needs to be executed.

[Means for solving problems]

The apparatus of the present invention includes a plurality of vector storage means (hereinafter referred to as vector registers) holding ordered element data, and one of the plurality of vector registers according to an instruction.
mask bit storage means (hereinafter referred to as mask register) that selects one vector register and generates and stores mask bits from the condition code specified by the instruction; a first counting means for detecting a value and counting consecutive unoperable values from the first generated mask bit;
A second counting circuit detects the value of the mask bit generated by the instruction and counts only the value of the arithmetic unit in synchronization with the generation of the mask bit.
counting means (hereinafter referred to as a second counting circuit); first count value storage means (hereinafter referred to as a first buffer) for storing a plurality of outputs of the first counting circuit; and an output of the second counting circuit. It has a second count value storage means (hereinafter referred to as a second buffer) that stores a plurality of .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes vector registers 100-1 to 100-4 vector registers T each holding a plurality of ordered element data.
Select the element data -5~ output from oo-1~100-4 and input it to the comparison input register 102.
A comparator 103 that sequentially compares element data according to a condition code specified by a mask bit generation instruction that temporarily holds all selected element data and outputs the result. A register 200 that holds mask bits to be generated; a mask buffer 201 consisting of multiple words that holds the contents of this mask register 200; ), a 0" count circuit 303 counts how many consecutive bits there are, and a 1" count circuit 305 counts how many values (“1” in this example) that require operation to be performed in the generated mask bits. , an “O” count register 304 that holds the number of mask bits counted by the “0” count circuit 303, and a “1” count circuit 3.
Holds the number of mask bits counted in 05.
1” count register 306 and “0” count register 304 are stored in a plurality of words.
“Count buffer 300, “1” count register 3
"1" consisting of multiple words that holds the contents of 06
″Count buffer 301 and mask buffer 20
It consists of a 1, 0'' count buffer 300 and an address register 302 that holds the address to be read/written to the ``1''1'' count buffer 301.

Mask bit generation is performed by executing a mask bit generation instruction having the instruction format shown in FIG. 2(1). Field 1 is an instruction specification field,
Field 2 is a field that specifies the storage address of the mask buffer 201 that stores the generated mask, field 3 is a field that specifies the condition code for mask bit generation, and field 4 holds element data to be compared according to the condition code. This field specifies one of the vector registers 100-1 to 100-4.

Field 2 is mask buffer analyzer 01 Field 3 is 0
Condition code equal to (element data content = 0)
, when executing a mask bit generation instruction in which field 4 specifies vector register 100-1, first, a plurality of element data held in vector register 100-1 are sequentially read out, and vector register selection circuit 101 Output to. The vector register selection circuit 101 selects the vector register number specified in field 4 of the instruction, that is, the contents of the vector register 100-1, and sequentially outputs element data to the comparison input register 102. The output of the comparison input register 102 is input to the comparator 103, and the condition specified in field 3 of the instruction, that is, whether or not the content of the element data held in the comparison input register 102 is 0'' is sequentially compared. If the content of the element data is equal to 0'', the comparator 103 outputs the mask bit -P'1'', and if the content of the element data is not equal to 0'', the comparator 103 outputs the mask bit = ``O''. . The output of the comparator 103 is distributed to a mask register 200, a 0" count circuit 303, and a 1" count circuit 305.
In the mask register 200, element data is sequentially held at mask bit positions corresponding to the processing order. In addition, the vector register Zoo-
If the element data first output from 1 is not equal to "0", that is, the mask bit is - "0", the callantra starts until °°1" appears in the mask bit output from the comparator 103. Sequentially count up and store the count value "0" in the count register 304. Therefore, if the element data first output from the vector register Zoo-1 is equal to 0", that is, if the mask bit is -1", then " o″ count circuit 30
3 times are not activated and the count value = "0" is output. On the other hand, the 1" count circuit 305 sequentially counts up only when the mask bit output from the comparator 103 is "1", that is, counts the number of element data whose mask bit = 11" and sets the count value to "1". 1 @ counter 9 - Store in the count register 306. "o" Count circuit 3
03 and "■" count circuit 305 are both initialized to 0'' at the start of the mask bit generation instruction.

When the number of element data being processed reaches a predetermined vector length (not shown), the vector register 100-1
The reading operation of , the registration of mask bits in the mask register 200, and the counting operations of the 1o'' count circuit 303 and the ``1'' count circuit 305 are suppressed.

At the same time that the registration of the mask bit in the mask register 200 is suppressed, the contents of the mask register 200 are changed to the mask indicated by the address register 302 holding the storage address specified in field 2 of the mask bit generation instruction. It is stored in the +0 area of the buffer 201.

In addition, in synchronization with the suppression of the counting operations of the "0" count circuit 303 and the "o" count register 304, the "0" JO- count indicated by the address register 302 changes until the contents of the 0" count register 304 are suppressed. It is stored in the +O area of the buffer 300.

In addition, in synchronization with the inhibiting of the counting operations of the 1" count circuit 305 and the 1" count register 306, the contents of the 1" count register 306 are changed to +0 of the 11" count buffer 301 indicated by the address register 302.
stored in the area.

Mask buffer 2011″0″ count buffer 300
．． The contents held by the count buffer 301 are stored until the next mask bit generation instruction is executed, or from the mask buffer 201 to the mask register 20.
Transfer command to 0, “0” count buffer 300 to 1
It is held until either a 0 "transfer instruction to the count register 304" or a "1" transfer instruction from the count buffer 301 to the count register 306 is executed.

After mask bit generation, when performing an operation using the mask bits registered in the mask register 200, the element data that does not need to be executed is the element data that is transferred to the arithmetic unit first before the instruction that executes the operation. A method is used in which the number of consecutive instructions is detected using all instructions, and the time required for calculation is shortened without transferring the corresponding element data to the calculation unit. In a non-embodiment, this is realized by executing an instruction having the instruction format shown in FIG. 2 (2). Field 1 is an instruction specification field, and field 2 is ``0'' count register 30.
Refers to the destination register number (for example, a scalar register number) to which the contents of 4 are to be transferred.

The instruction format of this instruction is the same as before, but in the past, it first decoded how many "0゛°" continued from the mask bit position in the mask register corresponding to the element data to be transferred to the arithmetic unit. The value is transferred to the destination register specified by the instruction, but in the present invention, it is only necessary to transfer the count value held in the 0'' count register 304 to the destination register specified by the instruction.

Furthermore, a method has been used in the past in which the number of pieces of element data that need to be executed is detected prior to issuing an instruction to execute the operation.

This is also realized by executing another instruction having the instruction format shown in FIG. 2(2).

Conventionally, the mask register was decoded to detect how many pieces of element data that needed to be operated on existed, that is, how many 1 "j"s existed in the mask register, and that value was specified with an instruction. However, in this embodiment, it is only necessary to transfer the count value held in the 11'' count register 306 to the destination register specified by the instruction.

〔Effect of the invention〕

As explained above, the present invention executes a mask bit generation instruction to sequentially register mask bits '&: in a mask register, detects the value of a mask bit, and detects a mask bit with a designation that does not require operation. By counting the number of consecutive values of , and the number of mask bit values that specify that an operation needs to be performed, the contents of the mask register can be read prior to the instruction that executes the operation. This has the effect of greatly reducing the processing time for instructions to be decoded.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing an instruction format for operating the embodiment of FIG. In Figures 1 and 2, 100-1 to 100-4
...Vector register, 101...Hector register selection circuit, 102...Comparison input register, 103...Comparator, 200...
...Mask register, 201...Mask buffer, 300...''O'' count buffer, 30
1..."1" count buffer, 302...
...address register, 303..."0" count circuit, 304..."0" count register, 305..."1" count circuit, 306.
...@1″ count register.

Claims (1)

[Scope of Claims] A plurality of vector storage means for holding ordered element data; one of the plurality of vector storage means is selected by an instruction, and a mask bit is generated from a condition code specified by the instruction. a first mask bit storage means for detecting the value of the mask bit generated by the instruction in synchronization with the generation of the mask bit and counting successive unoperable values from the first generated mask bit; a counting means, and a second means for detecting the value of the mask bit generated by the instruction in synchronization with the generation of the mask bit and counting only the operable value.
counting means, a first count storage means for storing a plurality of outputs of the first counting means, and a second count storage means for storing a plurality of outputs of the second counting means. Characteristic vector data processing device.