JPS6328355B2 - - Google Patents

Description

[Detailed description of the invention] Technical field of invention The present invention relates to a method for manufacturing a charge coupled device.

TECHNICAL BACKGROUND OF THE INVENTION Conventionally, an embedded two-phase drive charge-coupled device for, for example, a CCD has been manufactured as shown in FIGS. 1a to 1d. First, for example, phosphorus ions (p ⁺³¹ ) are implanted into a p-type silicon substrate 1, and then a heat treatment is performed to form an n ⁺ -type semiconductor layer 2 on the substrate 1. Next, an insulating film such as a SiO ₂ film 3 is formed on this semiconductor layer 2.
form. Subsequently, after depositing, for example, a polycrystalline silicon film (not shown) on this SiO ₂ film 3,
Etching is performed using a resist pattern formed by photolithography as a mask to form a plurality of first polycrystalline silicon electrodes (first electrodes) 4 (as shown in FIG. 1A). Next, using the first electrodes 4 as a mask, the exposed SiO ₂ film 3 is removed by etching with ammonium fluoride or the like (as shown in FIG. 1B).
Subsequently, thermal oxidation is performed to form the first electrode 4...
A thermal oxide film 5 and a gate oxide film 6 are formed around the semiconductor layer 2 and on the semiconductor layer 2 exposed by the etching, respectively. Subsequently, using the first electrode 4 as a mask, boron ions (B ⁺¹¹ ) are implanted into the n ⁺ type semiconductor layer 2 and neutralized to form a low concentration n type semiconductor layer 2' (first Figure c). At this time, the intensity of ion implantation is adjusted so that boron ions are not implanted under the first electrode 4. Furthermore, after depositing a polycrystalline silicon film (not shown) on the entire surface, etching is performed using a resist pattern formed by photolithography as a mask, and a second polycrystalline silicon electrode (second polycrystalline silicon film) is formed on the gate oxide film 6. electrode)
7..., a part of which is connected to the first electrode 4 through the thermal oxide film 5.
Formed so that it partially overlaps with... Finally, the adjacent first and second electrodes 4..., 7... are connected by Al wiring or the like to form a _φ1 electrode and a _φ2 electrode to manufacture a desired charge-coupled device (as shown in FIG. 1d). ).

In the charge-coupled device manufactured in this way, when a predetermined voltage is applied to the φ ₁ electrode (or φ ₂ electrode), the portion of the n-type semiconductor layer 2 where boron is not implanted is highly concentrated, and the second Since the boron-implanted semiconductor layer 2' portion below the electrode 7 has a low concentration, the potential well below the first electrode 4 is the same as that of the second electrode 7.
...deeper than the potential well below. Therefore, for example, when a high level voltage is applied to the φ ₂ electrode and a low level voltage is applied to the φ ₁ electrode, a potential curve as shown in FIG. 2 is obtained.

Problems with the Background Art However, in the above manufacturing method,
When removing the SiO ₂ film 3 by etching with ammonium fluoride or the like, side etching occurs because the etching is isotropic. Electrode 4...
The gate oxide film 6 near both lower ends of the first electrode 4 becomes thicker, causing a phenomenon called lifting in which both ends of the first electrode 4 are lifted. In such a case, the lateral diffusion of the implanted boron becomes small, so that φ ₂
When a high-level voltage is applied to the electrode and a low-level voltage is applied to the _φ1 electrode, a potential stagnation called a potential pocket (arrow in FIG. 2) is created in the lifting area, which causes a deterioration in charge transfer efficiency.
Incidentally, the above-mentioned lifting phenomenon becomes noticeable when the amount of side etching is large. For more information on this lifting phenomenon, see IEEE
“The
Effect of Interpoly Structure Variation on
Charge Transfer Efficiency of A Buried
It is reported under the expression "Channel CCD".

Purpose of the Invention The present invention has been made in view of the above circumstances, and provides a charge coupled device that enables charge transfer driving without boron implantation and prevents the generation of potential pockets that cause deterioration of transfer efficiency. The purpose is to provide a manufacturing method.

Summary of the Invention The present invention employs boron implantation to provide a step in a potential well under a first and second electrode when manufacturing a charge-coupled device having a buried channel for transferring charge to the surface of a semiconductor substrate of one conductivity type. without doing it,
By sucking out the arsenic implant used to form the buried channel into the insulating film on the substrate, a step is created in the potential wells under the first and second electrodes in consideration of the temperature difference in the buried channel, and charge transfer drive is performed. This made it possible. In particular, it is important to ensure that the arsenic ions implanted into the substrate when forming the buried channel have an ion concentration peak on the substrate surface, and to ensure that the arsenic ions implanted during the formation of the semiconductor layer in the subsequent process are not sufficiently activated. The gist of the invention is heat treatment.

Embodiments of the Invention When the present invention is applied to the manufacture of an embedded two-phase drive charge-coupled device for a CCD, FIGS.
The explanation will be based on d.

[] First, in order to form an embedded CCD, arsenic ions are dosed into the p-type silicon substrate 11.
The ions were implanted at a concentration of about 1.0 to 5.0×10 ¹² cm ⁻² onto the surface of the substrate so as to have a peak in ion concentration. next,
A low-temperature oxide film (not shown) is deposited on the substrate 11, and heat treatment is performed at 1000°C in an _N2 atmosphere for several tens of minutes to several hours to the extent that the implanted arsenic ions are not sufficiently activated. An n ⁺ type semiconductor layer 12 was formed on the semiconductor layer 11 . Subsequently, after removing the low temperature oxide film to form a field region, a SiO ₂ film 13 was formed on the semiconductor layer 12. Next, the above-mentioned
A plurality of first polycrystalline silicon electrodes (first electrodes) 14 were formed on the SiO ₂ film 13 (as shown in FIG. 3A).

[] Next, using the first electrodes 14 as a mask, the exposed SiO ₂ film 13 was removed by etching with ammonium fluoride or the like (as shown in FIG. 3B). Subsequently, thermal oxidation is performed in DryO ₂ at 1000° C. to form thermal oxide films 15 and 15 on the surroundings of the first electrodes 14 and on the semiconductor layer 12 exposed by etching, respectively.
A gate oxide film 16 was formed (as shown in FIG. 3c).
Note that due to this thermal oxidation, the lower part of the first electrode 14...
The n ⁺ -type semiconductor layer 12 has a high concentration, and the portion where the second electrode is to be formed becomes a low-concentration n-type semiconductor layer 12'. Hereinafter, a second polycrystalline silicon electrode (second electrode) is prepared in the same manner as in the conventional example.
17..., a φ ₁ electrode, and a φ ₂ electrode to manufacture a desired charge-coupled device (as shown in FIG. 3d).

However, according to the above-mentioned manufacturing method, since arsenic ions, which have a much smaller diffusion coefficient than phosphorus ions, are used when forming the embedded CCD,
Even after the post-process heat treatment, diffusion does not progress much and the arsenic ions are deposited on the surface of the substrate 11, so the surface concentration of the substrate 11 does not change much compared to the initial stage of ion implantation.

Further, since the peak of the arsenic ion concentration implanted into the substrate 11 is located on the surface of the substrate 11 and the heat treatment is performed to such an extent that the arsenic ions are not sufficiently activated, the thermal oxide film 15 is formed on the first electrode 14.
In the step of forming the gate oxide film 16 between the first electrodes 14 , the n-type semiconductor layer portion exposed between the first electrodes 14 is formed between the first electrodes 14 .
Compared to the n ⁺ -type semiconductor layer 12 portion below, the amount of arsenic atoms sucked into the gate oxide film 16 is large, resulting in a low concentration n-type semiconductor layer 12'. As a result, a difference in ion concentration can be provided under the first and second electrodes 14..., 17..., and these electrodes 14..., 17...
When an equal voltage is applied to , a difference in potential of 2 to 4 V occurs. Therefore, as in the conventional case, the first and second electrodes 14
..., 17... There is no need to implant boron ions (B ⁺¹¹ ) to create a drop in the potential below, and the process can be shortened.

Furthermore, using the first electrodes 14 as a mask, SiO ₂
Even if side etching occurs when the film 13 is etched, the way arsenic ions are sucked out at the side etched portion changes gradually for the reasons described above. Therefore, in the charge coupled device shown in FIG. 3d, the first and second electrodes 14..., 1
7, there is no potential stagnation called a potential pocket as shown in the potential curve shown in FIG. 4, and no deterioration in transfer efficiency occurs due to this.

Note that in the above embodiment, the case of two-phase drive was described as the drive method, but the drive method is not limited to this, and single-phase,
The same applies to three-phase and four-phase drives.

Effects of the Invention As detailed above, according to the present invention, a highly reliable CCD that eliminates the boron implantation process, enables two-phase drive, prevents the occurrence of potential pockets, and prevents deterioration of transfer efficiency. The present invention provides a method for manufacturing a charge coupled device such as an embedded two-phase drive charge coupled device.

[Brief explanation of drawings]

Figures 1 a to d are cross-sectional views showing the conventional method for manufacturing a charge coupled device in the order of manufacturing steps, Figure 2 is a characteristic diagram showing the potential curve of the charge coupled device shown in Figure 1 d, and Figures 3 a to d 4 is a cross-sectional view showing the method for manufacturing a charge-coupled device according to the present invention in the order of manufacturing steps, and FIG. 4 is a characteristic diagram showing a potential curve of the charge-coupled device shown in FIG. 3d. 11... p-type silicon substrate, 12... n ⁺ type semiconductor layer, 12'... n-type semiconductor layer, 13...
...SiO ₂ film, 14... First polycrystalline silicon electrode (first electrode), 15... Thermal oxide film, 16... Gate oxide film, 17... Second polycrystalline silicon electrode (second electrode).

Claims (1)

[Claims] 1. In manufacturing a charge-coupled device having a buried channel for transferring charge to the surface of a semiconductor substrate of one conductivity type, a step of implanting arsenic ions into the substrate such that the ion concentration peaks at the surface of the substrate, forming a second conductivity type semiconductor layer on the substrate by performing heat treatment to such an extent that arsenic ions are not sufficiently activated; forming a plurality of first electrodes on the insulating film of the semiconductor layer; a step of etching the insulating film using the first electrode as a mask; a step of performing thermal oxidation to form a thermal oxide film on at least the exposed semiconductor layer; and forming a second electrode on the thermal oxide film; A method for manufacturing a charge coupled device, comprising the step of forming a first electrode so as to partially overlap the first electrode via the first electrode.