JPS63280367A - Multi-port memory controller - Google Patents

Abstract

PURPOSE:To permit same CPUs to shorten a queuing time when memory use request signals are generated again by testing the presence or absence of the memory use request signals on memory use request signals as groups consisting of (m)-number. CONSTITUTION:A titled controller consists of a circuit (A) for splitting a memory use request signal group from plural CPUs into the memory use request signals in groups, an unillustrated circuit (B) which generates memory approval signals with respect to the memory use request signals in the groups and an unillustrated circuit (C) which generates the memory use approval signals of respective CPUs with using the memory use approval signals in the groups. In the circuit (A), the memory use request signals 51-1-54-4 are splitted into the group consisting of four, and they are turned into the memory use request signals as the groups 51-54 through a wired OR circuit. The circuits (B) and (C) are similar to the convention example.

Description

[Detailed description of the invention] [Industrial application field] This invention is a multi-board memory controller.

In particular, it relates to a multi-board memory controller in a multi-CPU system that shares memory.

[Prior Art] Figures 2 and 3 show the multi-poling selection method used in line control, etc., as described in, for example, Iwao Hosaka, "Introduction to Data Communication Systems," published by Ohm Publishing, p. 118. FIG. 2 is a configuration diagram of a conventional multi-boat memory controller used for arbitration control of boat memories.

FIG. 2 is a configuration diagram showing an example of the configuration of a multi-CPU system showing the positioning of a multi-board memory controller. In FIG. 1, (1) is a group of CPUs;
+, cpu2+...-, cpun. (2
) is a multi-board memory controller whose input side and output side are connected to a CPU group (1) via a use request signal line group (5) and a use approval signal line group (6), respectively. (3) is a common memory, which is interconnected with the CPU group (1) via a shared bus (4).

FIG. 3 is a block diagram of a multi-boat memory controller in the case of 4 ports using the conventional polling method. In FIG. 0, (5a) to <5d) are memory use request signals input from each CPU, (6d) is a memory use approval signal to each CPU, (7) is an oscillation circuit that generates basic timing to test whether there is a memory use request from the CPU, and (8) is an oscillation circuit for turning on/off the basic timing signal. It is a gate circuit, and its input side is an oscillation circuit (7
) is connected to the output side of the 9) is a basic timing generation circuit whose input side is connected to the output side of the gate circuit (8), and sequentially tests whether there is a memory use request from the CPU based on the output of the gate circuit (8). Generate timing. (10) is a latch circuit,
One input side is a basic timing generation circuit (9),
The other input side is the memory use request signal (5a) to (5
It is connected to each line to which d) is applied, latches the memory use request status, and outputs it to the CPU as a memory use approval signal. (11) is an OR circuit.

Its input side is each line to which use approval signals (6a) to (6d) are applied, and its output side is a gate circuit (8).

They are connected to each other, and notify the off-state of basic timing generation to the gate circuit (8) while outputting a memory use approval signal.

The conventional multi-board memory controller is configured as described above, and when it becomes necessary to use the common memory (3), the CPU sends a message to the multi-board memory controller (2) through the memory use request signal line (5). A usage request is made. Multi-board memory controller (2)
) for this.

If the memory use is not approved, the gate circuit (8) and the basic timing generation circuit (9) sequentially generate CPLI, CPLI2, etc. using certain timing signals (12>, (13), (14), (15)).・We are testing the presence or absence of a usage request signal for the CPUI, and the latch circuit (10
) detects the presence of a memory use request signal, it immediately outputs a corresponding memory use approval signal (6), and the OR circuit (11) and gate circuit (8) turn off the memory use request signal on the CPtJ side. to.

The test for the presence of the next memory use request signal is being interrupted. When the access is completed in the CPU III and the memory use request signal is turned off, the latch circuit (10) turns off the corresponding use approval signal, and the OR circuit (11), gate circuit (8), and basic timing generation circuit ( 9), the test for the presence or absence of a memory use request signal is restarted.

[Problems to be Solved by the Invention] In the conventional multi-board memory controller as described above, in FIG.
) is approved and the memory use approval signal (6a) is output, the CPU access is completed, the memory use request signal (5a) is turned off, and the memory use request signal (5a) is output again.
) occurs, the memory use request signal (5b), (
5c) and (5d), the wait time will be three times the oscillation frequency time of one oscillation circuit in the worst case, and if the number of CPUs becomes n, , (n-1) times as long.

The present invention was made to solve this problem, and after the memory use request signal is approved, the memory use approval signal is output, and the CPU access is completed and the memory use request signal is turned off.

It is an object of the present invention to provide a multi-board memory controller capable of shortening the waiting time caused to test the presence or absence of another memory use request signal when the same CPU generates a use request signal again.

[Means for Solving the Problems] A multi-board memory controller according to the present invention is capable of dividing a group of memory use request signals from a plurality of CPUs into memory use request signals for each group in a multi-CPU system that shares memory. and a circuit that generates a memory use approval signal in response to a memory use request signal for each group.

A circuit for generating a memory use approval signal for each CPU using a memory use approval signal for each group.

[Operation] In this invention, since the presence or absence of a memory use request signal is tested for memory use request signals in groups of 1 m, the time required for the memory use and test when there is no request signal is This is 1/m compared to the case where the presence/absence of all m memory use request signals is tested.

[Embodiment] FIG. 1(a) is a circuit diagram showing an embodiment of the multi-board memory controller of the present invention, in which memory use request signals are divided into groups. In the figure, (51-1)+
..., (5, -,) are memory use request signals from each CPU, (5,), ..., (54) are group-specific memory use request signals, and the input is 16 Memory use request signals from each CPU (5+-1
,51-2,...,5. -4), the output is a memory use request signal divided into four groups (51°...
, 54).

FIG. 1(b) is a block diagram of a memory use approval signal generation circuit for each group showing an embodiment of the multi-board memory controller of the present invention.
This is an oscillator circuit that generates basic timing to test whether there is a memory use request from a computer, and outputs one oscillation frequency (f). (16) is a gate circuit and one oscillation circuit (7
) and turns the basic timing signal on/off.

(17) is a basic timing generation circuit, one input side of which is connected to the output side of the gate circuit (16). Memory use request signal (51, 5
2, 5-, 5-)).
24), (25), (26), and (27) are generated. (
18) is a latch circuit whose input side is connected to the basic timing generation circuit (17), latches the memory use request state, and outputs the memory use approval signal (5A + , 5 A 2 ) as a group.

5A3, 5A4). (One) is an OR circuit whose input side is the output side of the latch circuit.

The output side thereof is connected to the other input side of the gate circuit (16), and while the memory use approval signal is being output,
Notify the gate circuit (16) that basic timing generation is off. 1(C) is a block diagram of a memory use approval signal generation circuit for each CPU, showing an embodiment of the multi-board memory controller of the present invention. In the figure, (20) is a gate circuit that turns on/off the basic timing signal. (21) is a basic timing generation circuit whose input side is connected to a gate circuit (20), and the output of the gate circuit (20) generates memory use request signals (51-+, 51-+, 5 l-2,5,-,
5l-4) Timing for sequentially testing the presence or absence (31)
, (32), (33).

(34) is generated. (22) is an output circuit for the memory use approval signal of each CPU, whose input side is connected to the basic timing generation circuit (21), latches the memory use request state, and outputs the memory use approval signal (22) for each CPU. 6
l-+, 6 l-i, 6, -z, 6, -4). (23) is an OR circuit.

It is connected to this output circuit (22) and the gate circuit (
20), and notifies the basic timing generation off of the gate circuit (20) while outputting the memory use approval signal. Here, i=1.2°3.4.

In the multi-board memory controller configured as described above, when it becomes necessary to use the common memory (3) in FIG.
A memory use request is made for the combination of FIG. 1(a), FIG. 1(b), and FIG. 1(c)). In FIG. 1(a).

For convenience of explanation, this memory use request signal (51-1)
There are 16 +..., (5,,). These memory use request signals are divided into groups of four, and are passed through a wired OR circuit to become memory use request signals (5,), . . . (5,) as a group.

In FIG. 1(b), if the multi-board memory controller is not outputting the memory use approval signal, the gate circuit (16) and the basic timing generation circuit (17) are used to set certain timings (24), (25>, ( 26),
(27>, successive memory use request signal (51°52.5.
．． 5. ) is being tested for the presence or absence of the latch circuit (1
8), if the presence of the memory use request signal is detected, the corresponding memory use approval signal (5Al, 5
A2.5 A3.5 A4) is output.

These outputs are the memory use approval signals (5Al-1, 5Al-2, 5Ax-*, 5A+-4) of each CPU output in the same operation as in FIG. 1(b) in FIG. 1(c).
(i=1.2.3.4) is ANDed by the AND circuit in the output circuit (22), and the memory use approval signals (6l-1, 6l-2, 6, -3) corresponding to each CPU are
゜6 +-i> is output, and the test for the presence or absence of the next group's memory use request signal is suspended until the group's memory use request signal is turned off by the gate circuit (16) and OR circuit (19). . When each memory use request signal composing a group is turned off, it is turned off when all accesses of all the CPUs composing the group that have requested access have been completed), the latch circuit (18)
The memory use approval signal of the corresponding group is turned off, and the test for the presence or absence of the memory use request signal of the group is restarted through the OR circuit (19), the gate circuit (16), and the basic timing generation circuit (17). ing.

In the above embodiment, for convenience of explanation, the number of CPUs is set to 1.
Although six pieces are used, the same effect can be obtained even if the number of pieces is set to six.

Further, although the memory use request signal groups are grouped into one group of four request signals, the same effect can be obtained even if the number of the request signals is other than that of the group.

[Effects of the Invention] As described above, the present invention includes a circuit for dividing a group of memory use request signals from a plurality of CPUs into memory use request signals for each group, and a circuit for dividing a group of memory use request signals from a plurality of CPUs into memory use request signals for each group. a circuit that generates a use approval signal;
It is equipped with a circuit that generates a memory use approval signal for each CPU using the memory use approval signal for each group, divides the memory use request signal group into several groups, and tests the presence or absence of the memory use request signal as a group. This has the effect that when the same CPU generates a memory use request signal again, the waiting time that occurs for testing another memory use request signal can be reduced.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram for dividing memory use request signals into groups according to an embodiment of the present invention.
b) is a configuration diagram of a memory use approval signal generation circuit for each group showing an embodiment of the present invention; FIG. 1(c) is a configuration diagram of a memory use approval signal generation circuit for each CPU showing an embodiment of the present invention, and FIG. 2 is a multi-C
A block diagram of the PU system, FIG. 3 is a block diagram of a conventional multi-board memory controller. In the figure, (5,-+) to (5,-,)...each CP
Memory use request signal from U, (5+) to (54)...
・Group-specific memory use request signal, (6,-1) to (6
, -4)...Memory use approval signal for each CPU as a multi-board memory controller, (7)...Oscillation circuit. <16), <20)...Gate circuit, (17), (
21) Basic timing generation circuit, (18)...
Latch circuit, (19), (23)...OR circuit, (2
2)...This is an output circuit for each CPU's memory use approval signal. Note that the same reference numerals in each figure indicate the same or corresponding parts. Challenge 1 Figure (Q)! 1 mouth (b) yA1■ (C)

Claims (1)

[Claims] In a multi-CPU system that shares memory, there is a circuit for dividing a group of memory use request signals from multiple CPUs into memory use request signals for each group, and a memory use approval signal for the memory use request signal for each group. A multi-port memory controller comprising: a circuit for generating a memory use approval signal for each CPU; and a circuit for generating a memory use approval signal for each CPU using a memory use approval signal for each group.