JPS6327899B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic tuning tuner device, and in particular to an automatic tuning frequency control signal called AFT.
This method is characterized by a method in which a fine adjustment voltage based on a signal is superimposed on a tuning voltage.

Recent electronic tuning tuners for television receivers employ a method in which the capacitance is varied by applying a terminal voltage (tuning voltage) to a variable capacitance diode, and the tuning frequency (channel) is selected. . As means for generating the tuning voltage, there is a method of obtaining the tuning voltage by converting a digital signal into an analog signal.
This is obtained by passing a pulse waveform with a constant period T through a low-pass filter, and when changing the voltage value output from this, the pulse duty of the pulse waveform with a constant period T is varied. ing.

Even in the case of an electronically tuned tuner device using the pulse width modulation PWM method as described above, its output tuning voltage V _T is not always optimal for the receiving channel. Therefore, the previous tuning voltage V _T
It is conceivable to maintain an optimal reception state by arbitrarily superimposing a fine adjustment voltage V _T ' on the signal. In order to obtain the fine adjustment voltage V _T ′, it is possible to use a pulse width modulation circuit and superimpose the fine adjustment pulse obtained from this pulse width modulation circuit on the channel selection pulse described above. It will be done. That is, the first pulse width modulation circuit for channel selection and the second pulse width modulation circuit for fine adjustment are used, and the configuration is such that the output pulses of both can be synthesized. The second pulse width modulation circuit for fine adjustment is configured to vary its output pulse duty using, for example, an AFT signal.

However, when using such a method, when determining whether to further increase or decrease the amount of superposition after one step of superposition operation by the second pulse width modulation circuit, the result of the previous superposition operation is sufficiently stable. You need to wait until then and then make a decision. In this way, a certain amount of time is required for each step, so when the AFT operation range is wide or when the number of steps is increased to improve resolution, the time required for AFT operation becomes longer. In order to solve this problem, the range of change in the AFT superimposition amount is changed in several steps, and the range of change is changed largely at first, and then the range of change is gradually reduced to gradually approach the center frequency. It is possible to shorten and average the time. However, when this is done, the operation gradually approaches the center frequency while causing damped oscillations, so the amplitude at the beginning is large and the tuning frequency fluctuates widely several times.As a result, the demodulated output is also affected by this, for example on TVs. Jiyoung: On the screen, the color tone etc. will fluctuate.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an electronic tuning channel device that can shorten the time required for AFT operation and eliminate large oscillatory changes in the amount of superimposition.

Embodiments of the present invention will be described below with reference to the drawings.

First, an example of the entire electronic tuning tuner will be described with reference to FIG. In FIG. 1, the first pulse width modulator is the second pulse width modulator.
The first pulse width modulation section includes a first counter circuit 1, an RS type first flip-flop circuit 2,
It is composed of a first comparator 3, a memory circuit 4, and the like. The second pulse width modulation section is composed of a second counter circuit 5, a second RS type flip-flop circuit 6, a second comparator 7, a presettable up-down counter circuit 8, etc. .

A clock pulse Ck is input to the first and second counter circuits 1 and 5. Also clock pulse
Ck is frequency-divided through a frequency divider 12 and is also input to the presettable up-down counter circuit 8. Next, 13 is a channel input section, and when a channel is specified here, the binary conversion circuit 1
Data at an address corresponding to the designated channel of the memory circuit 4 is read out via the memory circuit 4. Furthermore, by operating the channel input section 13, the up-down counter circuit 8 is reset via the switching signal generation circuit 15, and then starts operation.

The outputs of the flip-flop circuits 2 and 6 are then applied to first and second input terminals of a matrix circuit 16, and the output of this matrix circuit 16 is derived via a low-pass filter 17 as a tuning voltage. A pulse width modulation output for channel selection is obtained from the first pulse width modulation section, and a pulse width modulation output for fine adjustment during channel selection is obtained from the second pulse width modulation section.

The pulse width modulation output for fine adjustment is varied by the AFT signal, and when fine adjustment is required, data is preset to the presettable up-down counter circuit 8, for example.

Next, the circuit for creating the above data is constructed as shown in FIG. That is, the AFT superposition amount control signal is generated by a combination circuit of a timer and a superposition amount control means, and this circuit has a
AFT signal and clock are input. Furthermore, this circuit is specifically constructed as shown in FIG. In FIG. 3, 34 is a superimposition register circuit, 31 is an addition/subtraction circuit, 26 is a data switching circuit,
25 is a binary counter circuit, 35 is a shift register, 38 and 40 are exclusive OR circuits, 27 and 28 are OR circuits, and 23, 30, and 39 are AND circuits.

Reference numeral 21 denotes a start pulse input terminal, which is connected to one input terminal of the flip-flop circuit 22, a reset terminal of the binary counter circuit 25, and a second input terminal of the OR circuit 28. The output terminal of the flip-flop circuit 22 is connected to the second input terminal of the AND circuit 23, the data switching control terminal of the data switching circuit 26, and the second input terminal of the AND circuit 39.

The output terminal of the AND circuit 23 is connected to the clock input terminal of the binary counter circuit 25. The clock pulse Ck is input to the third input terminal 24 of this AND circuit 23, and the clock pulse Ck is input to the first input terminal.
The output of the OR circuit 27 is input. A binary counter circuit 25 is connected to the input terminal of this OR circuit 27.
Each bit output terminal of is connected. When the start pulse is input, the output of the binary counter circuit 25 is all "1", and the clock pulse Ck
Start time counting.

The shift register circuit 35 is connected via a terminal 36.
A waveform-shaped version of the AFT signal (high level or low level) is supplied, and this is transferred as transfer data using a clock pulse Ck. For example, two stages of appropriate transfer bits of this shift register circuit 35 are connected to an exclusive OR circuit 38.
is connected to the first and second input terminals of the. The output terminal of this exclusive OR circuit 38 is connected to the AND circuit 3
It is connected to the first input terminal of 9. This AND circuit 3
A calculation pulse is obtained from 9, and its output terminal is connected to the first input terminal of the OR circuit 28. A fine adjustment clock pulse input terminal 29 is provided at the third input terminal of the OR circuit 28. The output terminal of this OR circuit 28 is connected to the first input terminal of an AND circuit 30. A clock pulse input terminal 41 is provided at the second input terminal of the AND circuit 30. The output terminal of the AND circuit 30 is connected to the arithmetic processing control terminal of the addition/subtraction circuit 31 and also to the data movement control terminal of the register circuit 34. The addition/subtraction circuit 31 is provided with calculation mode switching terminals 32 and 33. When the tuning frequency is lower than the broadcast frequency,
The AFT signal is added, and at this time the calculation mode becomes addition mode, and as a result of the calculation, the tuning frequency is controlled toward the higher side. Further, an AFT signal is applied to the switching end 33 when the tuned frequency is higher than the broadcast frequency,
At this time, the calculation mode becomes subtraction mode, and as a result of the calculation, the tuning frequency is controlled to be lower. switching end 32,
The above-mentioned operation is obtained by supplying an AFT signal having an S-shaped characteristic and a reverse phase to 32. Appropriate transfer bits on the downstream side of the shift register circuit 35 are connected to an exclusive OR circuit 40, and the output terminal of this circuit is connected to the reset terminal of the flip-flop circuit 22.

The present invention is constructed as described above, and is particularly characterized in that the AFT operation is controlled by the circuit shown in FIG. The operation of the circuit shown in FIG. 3 will be explained with reference to the signal waveforms shown in FIG. To simplify the explanation, it is assumed that the number of steps of the superimposed pulse is seven.

When the start pulse (FIG. 4b) is input, the flip-flop circuit 22 is set, and
Counter circuit 25 is reset. The output of the flip-flop circuit 22 is output from the AND circuits 23 and 39.
conduction is possible. Furthermore, the output of the flip-flop circuit 22 switches the data switching circuit 26,
The output of the counter circuit 25 is applied to the addition/subtraction circuit 31. Furthermore, the start pulse is applied to the AND circuit 30 through the OR circuit 28, where it is logically connected to the clock pulse and P1 of FIG.
This pulse is applied to the arithmetic processing control terminal of the addition/subtraction circuit 31 and the data movement control terminal of the register circuit 34. It is assumed that the addition/subtraction circuit 31 is currently in the subtraction mode due to the AFT signal. This addition/subtraction circuit 31 receives data A from the register circuit 34 and the counter circuit 25 at the rising edge of pulse P1.
Data B is subtracted from , and the calculation result AB is written into the register 34 at the falling edge of pulse P1. At this time, since the output data ₁ to ₃ of the counter circuit 25 are all "1", the value A-7 is written into the register circuit 34.

This completes the first stage of processing,
Assuming that the superimposed value for fine adjustment given by data A up to the end of the register circuit 34 was at point A in Figure 4, data A-7 was given by this operation. Therefore, the superimposed value is A-
Gradually move to level 7. During this time, the counter circuit 25 counts the clock pulses.

However, when the tuning frequency crosses the broadcast frequency during the change (sweep) of the superimposed value, the addition/subtraction circuit 31 switches to the addition mode, and
The AFT signal (Figure 4C) is transferred to the shift register circuit 3.
5 Exclusive OR circuit 38, AND circuit 3
9 to generate a calculation pulse α (FIG. 4d). As a result, the calculation pulse α is applied to the addition/subtraction circuit 31 according to the logic with the clock pulses in the OR circuit 28 and the AND circuit 30. (Pulse P2 in Fig. 4h) At this time, the counter circuit 25 counts four clock pulses, and ₃ to ₁ becomes "01", and this value is input to the addition/subtraction circuit 31 as data B. . That is, in the example shown in FIG. 4, the counter circuit 25 is reset and the value (A-7) is set in the register circuit 34, and as the superimposed voltage gradually decreases as shown in FIG. The AFT signal is inverted (passes through a good tuning point), but the time up to this point is replaced by four clocks. The output data of the count circuit 25 obtained as a result is used as superimposition amount correction data. Furthermore, the relationship with the entire system will be explained. The time from the moment when the fine adjustment voltage is superimposed until the tuning voltage stabilizes (this is determined by the time constant of the low-pass filter 17 in FIG. 1) and the time required for the counter circuit 25 to make a full count (in this example, the clock is The number of clocks Ck from the moment the superimposed voltage is generated until the AFT signal is inverted can be determined by the tuning frequency and the broadcast frequency when the superimposition is 0. It can be used as correction data corresponding to the deviation.

If the difference between the tuning frequency and the broadcast frequency is large,
It takes time for the AFT signal to reverse polarity,
The number of clocks to be counted increases, and counter circuit 2
Since the inverted output data of 5 becomes small, the value stored in the fine adjustment register circuit 34 becomes large based on the calculation result. This results in a large superimposed voltage. Conversely, when the deviation between the tuning frequency and the broadcast frequency is small, the time until the polarity of the AFT signal is reversed is short, the count value of the counter circuit 25 is small, and the inverted output data of the counter circuit 25 is large. Therefore, the output of the counter circuit 25 and the register circuit 34
The calculation result of the data is small in value, and this is stored in the register circuit 34 again, so the superimposed voltage becomes a small voltage. In this way, superimposed data for fine tuning corresponding to the difference between the tuning frequency and the broadcast frequency when the amount of superimposition is 0 is obtained in the first fine tuning operation. Also, since the previous calculation result A-7 is written in the register circuit 34, in this calculation, {(A-7)+
3} is performed, and the data (A-4) is newly written to the register circuit 34.

Next, the output β of the exclusive OR circuit 40
(Fig. 4e), the flip-flop circuit 22
is reset. (FIG. 4f) As a result, the gates of AND circuits 23 and 39 are closed. As a result, the operation of the counter circuit 25 is stopped. Furthermore, the data switching circuit 26 is switched to the basic small data "001" on the data input terminal 26A side, and this data is preset.

This completes the second stage of processing, and data A-4 is set in the register circuit 34, and the superimposed value is changed to that level.

Next, for the addition/subtraction circuit 31, the fine adjustment clock pulse Cp (Fig. 4g) and the clock pulse
A calculation pulse is input based on a logical product with Ck (FIG. 4a). At this time, data that changes bit by bit is also input to the data input terminal of the data switching circuit 26. Therefore, the data in the register circuit 34 is slowly varied one step at a time. When the tuned frequency and the broadcast frequency match, a stop signal closes the gate of the AND circuit 30, for example. The above operation is illustrated in a broach chart as shown in Fig. 5. Step _SP1 is the start time, and when the AFT signal reaches a certain level, the detection circuit operates and generates a start pulse. Next, the process moves to step _SP2 , where the fine adjustment voltage based on the calculation result changes transiently, resulting in a superimposition operation.
In other words, the data is changed significantly and the transient operation of the tuner is used to count the time until the AFT signal reverses. (Steps SP ₃ , SP ₄ ) Through this operation, the sweep speed to the tuning point depends on the transient response characteristics of the tuner. When the AFT signal is inverted, the data is replaced and the amount of superimposition is corrected in order to move on to fine adjustment. (Step SP ₅ ) Fine adjustment is then performed by increasing or decreasing the amount of superimposition one step at a time until a tuning point is reached where the AFT signal disappears. (Steps SP ₆ , SP ₇ ) The data stored in the shift register circuit may be used as data to determine the current frequency ratio and determine the amount of superimposition, but depending on the tuner system, this data may be used as the basic data. It is also possible to read it out as a superimposed voltage and pass it through a digital-to-analog converter.

As described above, according to the present invention, the data for correction is first greatly varied, and this data is used to effectively utilize the waiting time until the device shifts to operation, and the waiting time until the AFT signal is inverted. Based on this relationship, the data to be added or subtracted in the next step is stored in a register circuit, and the amount of superimposition is changed for each step, which takes the time required for the AFT operation. It is possible to provide an electronically tuned tuner device that is shortened and minimizes the vibration of the superimposed operation, taking advantage of the fact that a small deviation near the tuning point has little effect on the demodulated output.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of an electronically tuned tuner device according to the present invention, FIG. 2 is a diagram showing the basic components of the invention, and FIG. 3 is a concrete illustration of FIG. 2. FIG. 4 a to i, which are explanatory diagrams showing the main parts of the present invention, are operational waveform diagrams in FIG. 3, and FIG. 5.
This figure is a diagram showing an operation flowchart of the circuit of FIG. 3. 22...Flip-flop circuit, 23, 30, 3
9... AND circuit, 25... Counter circuit, 26... Data switching circuit, 27, 28... OR circuit, 31... Addition/subtraction circuit, 34... Register circuit, 35... Shift register circuit.

Claims (1)

[Scope of Claims] 1. An electronic tuning tuner having means for generating a fine adjustment voltage for fine adjustment according to an automatic tuning frequency control (AFT) signal, and adding or subtracting and superimposing this on the tuning voltage, A register circuit stores data for determining the amount of superimposition of the fine adjustment voltage, and the initial data of the register circuit and the fine adjustment voltage corresponding to the amount of superimposition of the fine adjustment voltage of zero are determined by a start pulse from the AFT signal detection section. addition/subtraction circuit means for calculating the sum or difference with data corresponding to the maximum amount of superimposition of the fine adjustment voltage and storing the result in the register circuit; counter circuit means that generates data to input to the addition/subtraction circuit through a data switching circuit and starts counting clock pulses; Said
means for causing the addition/subtraction circuit to calculate the difference or sum between the data currently stored in the register circuit and the data counted by the clock by the counter circuit in response to the polarity of the AFT signal being switched; stopping the operation of the counter circuit after the operation of the means, and presetting data corresponding to the minimum amount of superimposition in the data switching circuit;
For fine adjustment, this preset value is input to the adder/subtractor circuit using a low-speed clock to perform a sum or difference calculation, and when the tuning point is reached using the resulting tuning voltage, the low-speed clock is stopped and fine-tuned. An electronic tuning tuner characterized by comprising means for stopping adjustment.