JPS63276944A - Data transfer equipment - Google Patents

Abstract

PURPOSE:To quicken the information transfer by allowing a transmission section to write information of a prescribed byte number to be transferred into a storage, transmission information by a prescribed method in applying a CPU transfer start trigger to a transmission control means, allowing a reception section to write the information into a storage and reading it at a CPU when a prescribed number of bytes for writing are finished. CONSTITUTION:A transmission section once writes all transfer information into a storage 30, and in applying a transfer start trigger of a CPU to a transmission control means 32, the information is transferred according to a prescribed hand-shake method. The transferred byte number and the byte number written in the storage 30 are compared by a circuit 31 and the transfer is finished when they are coincident. By the control of a reception control means 42, a reception section writes information into a storage 40 by a prescribed hand-shake method and a counter 41 counts the byte number. The reception control means 42 informs the end of transfer to the CPU at the end of write. The CPU reads the information of the corresponding byte number to the count 41 from the storage 40. By such a constitution, the information transfer speed depends on the processing speed of the reception section and high speed information transfer is attained.

Description

[Detailed Description of the Invention] [Summary] In a data transfer device, the transmitting unit writes a predetermined number of bytes of data to be transferred into the transmitting storage means, and then the CPU
When a transfer start trigger from is applied to the transmission control means,
The data is transferred to the receiving section using a handshake method determined by the control of the transmission control means.

The reception section receives this data using a handshake method under the control of the reception control means and writes it into the reception storage means, and when the writing of a predetermined number of bytes of data is completed, the CPU
This is intended to speed up data transfer by having the data read out from the side.

[Industrial application field]

The present invention relates to an improvement in a data transfer device 9, for example, a data transfer device that transfers parallel data using a handshake method.

FIG. 3 is a time chart of the hide shake method to which the present application can be applied, and FIG. 3 (a) is a time chart of the transmitter;
FIG. 3 (bl shows a time chart of the receiving section. The numbers in the figure indicate the order of procedures, (S) indicates transmission, and (R) indicates reception.

This method will be explained below with reference to the figure.

1) Time chart of the transmitter (see Figure 3 (al)) First, as shown in
When it receives ``, the level of ``data being sent'' is set to H, and the first word of data is transferred almost simultaneously, and after a period of time 1, the level of ``L'' indicates that the transferred data is valid. “Send the data strobe to the receiver (see ■ to ■).

Next, in response to the reception of “Receive OK” at level 11, “
The level of the data strobe is changed from L to H and sent to the receiving section. Therefore, the receiving section changes the level of "receive OK" from H to L to indicate that transmission is possible, and therefore transfers the next word of data from the transmitting section (see ① to ①).

After repeating this and sending out the last word of data from the transmitting section, "change the data strobe level from H to L and send it to the receiving section, and after receiving the 11 level "receive OK" from the receiving section, ""Sendingdata" level to L
to H and sends it to the receiving unit (see ■~@). Then, when "receive OK" becomes L, the transmitting section sets the level of the data strobe to 1 (from then on) and transmits the data, thereby completing the data transfer.

This state corresponds to the state A in FIG. 3(a).

(2) Time chart of the receiving section (see Fig. 3 (bl)) In the receiving section, as shown by ◯ to 0, almost the opposite operation to that of the above-mentioned transmitting section is performed.

Here, when data is transferred using the handshake method as described above, it is necessary that the transfer speed be high.

[Prior Art] Fig. 4 shows a block diagram of a conventional example, with the block diagram above the dotted line showing the transmitting section, and the section below the dotted line showing the receiving section.

Hereinafter, the operation of FIG. 4 will be explained assuming that since a program corresponding to the time chart of the above handshake method is written in the memory (not shown), the CPU 1 executes the above time chart in accordance with the program. .

First, in the transmitting section, when "receive OK" is received from the other party, an inverter (hereinafter abbreviated as INV), a 6,7° D-type flip-flop (hereinafter abbreviated as D-FF),
CP as IRQ (interrupt request) via INV3
Added to U 1.

Therefore, the CPU sends the address (B) and data (Do) to the buffer gate 14 via the address decoder 2 and the data bus.
-FF9. Through INV 4, an L-level message "Data Sending" is sent to the other party.

8 is a buffer gate 14. No specifies D-FF 9.

Then, the data of the first word of the data to be transferred, which had been transferred to the internal register (not shown) of the CPU, is transferred to address 8 and the read/write clock (hereinafter referred to as R).
/W-CK) is used to transfer the data in parallel to the other party via the buffer gate 13, but after time t1 from the start of data transfer, the CPU transfers the address (B) and data (p,) to the buffer gate. 14, so the buffer gate 14. D-FF IQ.

This data passing through INV 5 causes an L level "data strobe" to be sent to the other party.

After that, the H level "receive OK" was IN.

7. Input to the CPU via D-FFII and INV3, and send address (B) and data (0+) from CPU 1.
sends out to the buffer gate 14, so D-FF 10
．． The If level “
data strobe” is sent to the other party.

Therefore, since the other side manually sends an L level "receive OK", the parallel data of the next word is transferred to the buffer gate 1.
3 to the other party.

By repeating this process, data of a predetermined byte length is sent out.

Next, in the receiving section, the address (C) and data (
mouth. ) is sent to the buffer gate 15, so D-F
F24. With this data passing through INV 23, L
A level “receive OK” is sent to the other party. In response, the other party's L-level "Data Sending" is treated as an interrupt request. 19. D-FF 26.
lNV2O is input to the CPU via the AND gate 16.

The CPU receives address 8 via address decoder 2,
Since R/W-CK is sent to buffer number 2 via INV8, the first word of transferred parallel data is read into the CPU via buffer gate 12.

Thereafter, in the same way as the transmitter, reception of an L level "data strobe", transmission of an H level "receive OK", transmission of an H level "receive OK", and reception of an H level "data strobe" are performed using INVs 17 to 23. D-FF 24-2
7. AND gate 16. The buffer gate 15 is used to complete the reception of the first word of data.

[Problem that the invention seeks to solve]

That is, when transferring data using a predetermined handshake method, the CPU must directly drive the buffer gates and D-PF, and is highly dependent on CPU processing.

Therefore, the input/output speed of parallel data is determined by the clock speed of the CPU and the processing ability of the program, and there is a problem in that high-speed data transfer is difficult.

[Means for solving problems]

The above problems are solved by the data transfer device shown in FIG.

Reference numeral 30 denotes a transmission storage means for writing and reading a predetermined number of bytes of data to be transferred by the CPU, and 31 a count value corresponding to the number of bytes of the data written in the transmission storage means and the bytes of the data read and transferred. 32 is a comparison means that sends a transfer end signal to the transmission control means when the count value corresponding to the number matches, and 32 is a comparison means that sends a transfer end signal to the transmission control means when the count value corresponding to the number of data matches. The transmission control means controls the operation of the transmission unit so that the transfer is performed.

Further, 40 is a reception storage means for writing and reading the transferred data, 41 is a reception data counting means for counting the number of bytes of the data written in the reception storage means, and 42 is a reception storage means when the data is in a reception ready state. , controls the operation of the receiving section so that the transfer data is received using a predetermined handshake method, and sends a transfer end signal to the C when the predetermined number of bytes of data has been written to the reception storage means.
This is reception control means for sending data to the PU.

[Effect]

In the present invention, when the CPU transfers a predetermined number of bytes of data to the other party, the transmitting section once writes all the data to be transferred into the storage means 30, and then a transfer start trigger from the CPU is sent to the transmission control means 30. added to.

Therefore, the data is transferred to the receiving section of the other party according to the handshake method determined by the control of the transmission control means, separated from the CPU control. If the comparison means 31 detects that the number of bytes and the number of transferred bytes match, the process ends.

On the other hand, in the reception section, if the reception is possible, the reception control means 4
The transfer data is written into the reception storage means 40 using the handshake method determined by the control of No. 2, and the number of bytes of the written data is counted by the reception data counting means.

Then, when all the data has been written, the reception control means notifies the CPU of the end of the transfer, so the CPU reads the count value of the reception data counting means and counts the number of bytes of data corresponding to the count value. Read from the reception storage means.

That is, when transferring data, the CPU sends a trigger to start the transfer to the transmission control means, and then the data is sent to the receiving section according to the handshake method determined by the control of the transmission control means, so that the data transfer rate is low. depends on the processing speed of the receiving section and enables high-speed data transfer.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the invention.

Also, transmission RAM 301. Buffer gate 302 is a component of transmission storage means 30, input counter 311. Transmission counter 312. Selector 313. Comparator 314 is a component of comparison means 31, transmission controller 321. Data transmission request transmitter 322. Data strobe transmitter 323. The receive OK receiver 324 is a component of the transmission control means 32, the reception RAM 401 and the buffer 302 (common) are components of the reception storage means, and the reception counter 411. Selector 412
are the constituent parts of the reception data counting means 41, and the reception controller 421. Data strobe receiver 422. Receive OK
Transmitter 423. The data transmitter 424 is a component of the reception control means 42 .

Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the transmission controller 321 and the reception controller 421 have a function (for example, a logic circuit The operation will be explained with reference to FIG.

- First, the CPU (not shown) must write the number of bytes of data to be transferred into the transmission RAM 301, so from here it adds -CK to the transmission controller 321 and input counter 311. Therefore, the selector 313 selects the cPυ address side in response to a selector switching signal from the transmission controller, and --CK is added to the transmission RAM.

Therefore, data is written into the area corresponding to the address added to the transmission RAM 301 via the selector, and in response to this, the input counter counts W-CK. Then, when a predetermined number of bytes of data are written, writing stops, and the input counter becomes the corresponding count value. The transmission controller 321 returns the selector 313 to the transmission counter side.

On the other hand, if "receive OK" is applied from the other party to the transmission controller 321 via the receive OK receiver 324, and an IRQ is sent from there to the CI'U, then the transmission RA
Since writing to M has been completed, the address and data are applied from the CPU as a transfer start trigger to the data transmission request transmitter 322 via the transmission controller 321, and from this point on, the L level "data transmission" is sent. Sent out.

After that, R-CK is sent from the transmission controller 321 to the transmission RAM 3.
01, the L level “receive OK” is detected on the transmission counter 3.
21, the transmission counter counts this, and the address corresponding to the count value is sent to the transmission RAM via the selector 313. The first word of data is then read out and sent out through buffer gate 302.

1 hour after sending the data. After the data strobe is at L level, the data strobe transmitter 323
In response, the other party sends an H-level 6 receive OK” to the transmission controller 321 via the receive OK receiver 324.

Therefore, under this control, an H level "data strobe" is sent from the data strobe transmitter, and an "L""receiveθK" from the other party is again applied to the transmission controller via the receive OK receiver 324, from which the data strobe is transmitted. counter 31
2, the count value increases and the comparator 31
4, and this value is added to the transmission RAM via the selector 313 as a value corresponding to the address,
The next word of data is read and transferred to the other party.

This is repeated, and when the count value of the transmission counter matches the count value of the input counter, it means that the predetermined number of bytes, that is, the last word, has been transferred, and the device enters a standby state.

On the other hand, in the receiving section above the dotted line in FIG. 2, the receive OK transmitter 423 is controlled by the CPU (address and data).
A "receive OK" signal of L level is sent to the other party, and the reception counter counts this.

Next, an L-level “data sending” signal is applied from the other party to the reception controller 421 via the data sending receiver 424, and at about the same time, the first word of data that has passed through the buffer gate 302 is transferred to the reception RAM 401. is written to the address corresponding to the count value of the reception counter. Note that the selector 412 is switched to the reception counter side by the reception controller.

And time 1. After the data strobe receiver 422 receives an L-level data strobe, it sends an H-level "receive OK" to the other party, and when it receives an H-level data strobe, it sends an L-level "receive OK" again. " is sent to the other party, and the next word of data is received, but the reception counter 411 counts the falling edge of "Receive OK" at the L level.

When all the data is transferred by repeating this, the reception controller 421 sends the IRQ to the CPU, so the CPU
reads the count value of the reception counter, and reads all transfer data in addition to the reception RAH via the selector up to the address corresponding to the value.

That is, data is transferred using a handshake method by the transmission control section and the reception control section in response to a transfer start trigger from the CPU, so that high-speed data transfer is possible.

〔Effect of the invention〕

As described above in detail, the present invention has the effect of enabling high-speed data transfer.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, and Fig. 3 is a tie of the handshake interface. Figure 4 shows a block diagram of a conventional example. In the figure, 30 is a transmission storage means, 31 is a comparison means, 32 is a transmission control means, 40 is a reception storage means, 41 is a reception data counting means, and 42 is a reception control means. /! of the present invention! ! T village along map Y f b

Claims (1)

[Claims] When transmitting data using the handshake method, the transmitter
A transmission storage means (30) in which the PU (33) writes and reads a predetermined number of bytes of data to be transferred, a count value corresponding to the number of bytes of the data written in the transmission storage means, and the data read and transferred. a comparison means (31) that sends a transfer end signal to the transmission control means when the count value corresponding to the number of bytes matches; the transmission control means (32) for controlling the operation of the transmission section so that the data is transferred; reception storage means (40) for writing and reading out the data transferred to the reception section; and the reception storage a received data counting means (41) for counting the number of bytes of the data written in the means; and a receiving section configured to operate the receiving section so that the transfer data is received using a predetermined handshake method when the data is ready for reception. 1. A data transfer device comprising: reception control means (42) for controlling the CPU and sending a transfer end signal to the CPU when the predetermined number of bytes of data have been written to the reception storage means.