JPS63276935A - High speed bus arbitration circuit - Google Patents

Abstract

PURPOSE:To attain bus acquisition by providing a constant current source to each unit, allowing a unit issuing a bus request to supply it to a bus line, and allowing each unit to detect a voltage drop across a resistor provided to the line thereby judging whether the request is addressed only to itself or to plural stations. CONSTITUTION:When each unit does not issue any request, a switch 3 is turned OFF, no current flows to a bus line 5 and no voltage drop exists across a resistor 6 and the voltage of the line 5 is zero. When a unit desires to acquire a bus, a request signal is outputted from a bus requester 2 to the switch 3 after zero voltage is confirmed by a level comparator, an output current from a constant current source 1 is fed to the line 5 to cause a voltage of e.g., 2.5V across the resistor 6. Then the pulse comparator 4 compares the voltage and when the voltage is 2.5V, it is recognized that the acquisition request comes from the station only and the voltage is restored to zero after the real cycle. If a request exists earlier, since the voltage reaches>=2.5V, retrial is actuated after being in the standby state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control circuit when a plurality of units, such as a computer, acquire a bus alternately and perform data transfer operations.

(Summary of the Invention) The present invention enables high-speed arbitrage by flowing a constant current through the bus line and detecting the voltage level when each unit acquires the bus.

(Prior Art) Conventionally, as shown in FIG. 3, a bus acquirer circuit is provided separately from a plurality of bus requesters requesting bus acquisition, and the bus acquisition request signal output from the bus requester is a bus request signal. Go to Bus Abita through the line,
The one that receives the pass accredited signal in response is
I was able to get a bus.

(Problems to be Solved by the Invention) However, in the conventional 7 and tracing circuits, a separate bus abiter is always required, and at least two bus lines are used. Furthermore, the processing time for avitreation was 50 to 100 nS, which was disadvantageous in terms of speed.

Therefore, in order to solve these conventional drawbacks, the present invention aims to eliminate the need for a separate Avita, use only one bus line, and further reduce the processing time to around 1 ounce.

(Means for Solving the Problems) In order to solve the above problems, the present invention has a constant current source for each unit, and the unit issuing a bus request sends it to the bus line, The system detects the voltage drop in the resistor attached to the line for each unit and determines whether the request is for just one person or multiple users and then acquires the bus.

(Function) By the means described above, the current bus usage status and the status of other NoriQuesta at the time of outputting the bus request can be detected with a single bus line, and high-speed avitracing is possible. .

(Example) Examples of the present invention will be described below based on the drawings. In FIG. 1, when none of the units is issuing a request, the switch 3 is OFF, and no current flows through the bus line 5. Therefore, there is no voltage drop across the resistor 6, and the voltage on the bus line 5 is OV. Now, if one unit attempts to capture the bus, the level comparator 4 confirms that the bus line voltage is oV, and the bus requester 2 transfers the request signal to the switch 3.
Output to. Switch 3 receives the signal and switches on constant current source 1.
The output current of is sent to the bus line 5. The bus line 5 is connected to the n-end by a resistor 6. For example, when the current value is 10m8 and the resistance value is 2500, a voltage of 2.5V is applied to the bus line.

Next, in the unit, when the voltage becomes stable, the voltage of the bus line is compared by a level comparator 4. If the result is 2.5■, the user knows that he or she is the only one making the bus acquisition request, and goes directly to the next actual cycle.

At the end of the cycle, the request signal is stopped, the switch 3 is turned off, and the voltage of the bus line 5 is returned to OV.

If multiple units issue bus acquisition requests at the same time, the current flowing from each unit is added →−
It becomes 5V or more. When each 1 nit detects this voltage by the level comparator 4, it once stops the request signal and issues a request again after a delay of a certain period of time. If this delay time is changed for each unit, 'CL13 <, then a time difference will occur in the second bus acquisition request, so the one with the shortest delay time will acquire 1q. This makes it possible to prioritize each unit.

(Effects of the Invention) As explained above, according to the present invention, only a few circuits are provided for each unit, there is no need for an independent bus abiter, only one bus line is required, and high speed This has the effect of making it possible to perform bus abitrage techniques.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the abitrage in a unit according to the present invention, FIG. 2 is a block diagram of a case where a plurality of units according to the present invention are connected, and FIG. 3 is a block diagram of a conventional abitrage. 1... Constant current source 2... Bus requester 3... Switch 4... Level comparator 5... Bus line 6... Resistor

Claims (1)

[Claims] In each unit having multiple bus acquisition functions, the above-mentioned
a constant current source that outputs a current for notifying each unit of bus acquisition; a bus requester that generates a bus acquisition request signal; and a switch that causes the output of the constant current source to flow to the bus line in accordance with the request signal of the bus requester. and a level comparator that detects the voltage of the bus line and determines whether there is one or more bus acquisition requests.