JPS63276643A - キャッシュ・メモリ制御方式 - Google Patents

キャッシュ・メモリ制御方式

Info

Publication number
JPS63276643A
JPS63276643A JP62110868A JP11086887A JPS63276643A JP S63276643 A JPS63276643 A JP S63276643A JP 62110868 A JP62110868 A JP 62110868A JP 11086887 A JP11086887 A JP 11086887A JP S63276643 A JPS63276643 A JP S63276643A
Authority
JP
Japan
Prior art keywords
request
cache
signal
operand
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62110868A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0456345B2 (cs
Inventor
Kazue Yamaguchi
和枝 山口
Hideki Osone
大曽根　秀樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62110868A priority Critical patent/JPS63276643A/ja
Publication of JPS63276643A publication Critical patent/JPS63276643A/ja
Publication of JPH0456345B2 publication Critical patent/JPH0456345B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP62110868A 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式 Granted JPS63276643A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62110868A JPS63276643A (ja) 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62110868A JPS63276643A (ja) 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS63276643A true JPS63276643A (ja) 1988-11-14
JPH0456345B2 JPH0456345B2 (cs) 1992-09-08

Family

ID=14546723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62110868A Granted JPS63276643A (ja) 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS63276643A (cs)

Also Published As

Publication number Publication date
JPH0456345B2 (cs) 1992-09-08

Similar Documents

Publication Publication Date Title
CA1287924C (en) Bus interface circuit for digital data processor
JPH10232826A5 (cs)
US4831581A (en) Central processor unit for digital data processing system including cache management mechanism
WO2015138312A1 (en) Method and apparatus for transfer of wide command and data between a processor and coprocessor
US5091845A (en) System for controlling the storage of information in a cache memory
US5119484A (en) Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction
US5226170A (en) Interface between processor and special instruction processor in digital data processing system
JPS60124754A (ja) バッファ記憶制御装置
WO1997004392A1 (en) Shared cache memory device
JPS63276643A (ja) キャッシュ・メモリ制御方式
US5276892A (en) Destination control logic for arithmetic and logic unit for digital data processor
JPH0516061B2 (cs)
JPH04250542A (ja) コンピューターメモリシステム
JPH0461384B2 (cs)
JPH0552539B2 (cs)
JPH06149669A (ja) キャッシュデータ転送方式およびキャッシュデータ転送装置
CA1305557C (en) Control signal generation circuit for arithmetic and logic unit for digital processor
JP2538993B2 (ja) オペランドストアのキャッシュメモリヘのストア制御方式
EP0418220B1 (en) Destination control logic for arithmetic and logic unit for digital data processor
JPH02259945A (ja) ストア処理方式
JPH0690681B2 (ja) キャッシュメモリ制御方式
JPS61118855A (ja) バツフアメモリ制御方式
JPH057740B2 (cs)
JPS60123944A (ja) 情報処理装置におけるバツフアメモリ制御方式
JPH10247182A (ja) マルチプロセッサシステム