JPS63275962A - Peak detecting circuit - Google Patents

Abstract

PURPOSE:To improve detecting accuracy, by detecting the presence or absence of the output of a comparator, which is one-step higher than each comparator based on the comparison of a plurality of level reference signals and a detected peak signal. CONSTITUTION:A signal S1 as a detected peak signal, which is inputted from an input terminal 1, undergoes full-wave rectification in a full-wave rectifier circuit 21. In the detection of the peak position, the presence or absence of the output of a comparator, which is one-step higher than each of comparators 23-1-23-n is detected in the comparators 23-1-23-n in the vicinity of the peak position based on the result of the comparison with the signal S1 and a plurality of level reference signals L1-Ln by using inverter circuits 25-1-25-n and AND circuits 26-1-26-n. Even if noises are superimposed on the signal S1 and thereby the signal level is decreased, the effects are not exerted thereupon, and the detecting accuracy can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a peak detection circuit for detecting the peak position of an analog signal, such as a sine wave or a distorted wave, whose level changes sequentially at an arbitrary period. It is something.

[Prior Art] Fig. 3 is a circuit diagram showing a conventional peak detection circuit shown in, for example, "Design of ROP Amplifier Circuit" published by CQ Publishing Co., Ltd., pages 192 to 197. In the figure, 1 is an input terminal; 2 is a differentiating circuit that differentiates the input signal S from the input terminal l; 3 is a zero level comparator that performs a comparison based on the zero level of the signal S differentiated by the differentiating circuit 2; and 4 is a differentiating circuit from this zero level comparator 3. A rising/falling detection pulse generation circuit detects the rising edge and falling edge of the output signal S, and outputs a pulse at the time of detection, and 5 is an output for taking out the output signal S4 from this rising/falling detection pulse generation circuit 4. It is a terminal.

Next, the operation of the conventional device will be explained with reference to FIG.

FIG. 4 shows waveforms at various parts of the conventional device shown in FIG. In this figure 4, 6 is the input terminal 1
The normal waveform of the input signal S4 input to the differentiator circuit 2 from
7 is a waveform in which noise is superimposed on the normal waveform input signal S, 8 is a waveform obtained by differentiating the input signal S of normal waveform 6 with the differentiating circuit 2, and 9 is a waveform 7 with a feeder.
This waveform is obtained as a result of differentiating the input signal S0 in the differentiating circuit 2. When the input signal S (waveforms 6 and 7) whose peak is to be detected is input to the differentiating circuit 2, it is differentiated and becomes 9.
Signals S2 of waveforms 8 and 9 with a 0° phase advance are obtained, and the peak of the input signal S1 corresponds to the zero point of the differentiated signal S2.

The signal S2 obtained by being differentiated by the differentiating circuit 2 is compared with the zero level in the zero level comparator 3, and the signal S3 from the zero level comparator 3 is as shown in FIG. is also large, “0”
”, and if it is small, it becomes “1”.

Then, the rising/falling detection pulse generation circuit 4 receives the output signal S3 from the comparator 3, and receives the output signal S3.
The rising and falling points of the signal are detected, and as shown in FIG. 4, a detection pulse is outputted as an output signal S4 at the detected points. Therefore, the output time point of this output signal S4 corresponds to the zero level of the signal s2, that is, the input signal S4 corresponds to the zero level of the signal s2.
Since this also corresponds to the peak position of the input signal S, the peak position of the input signal S can be detected from the signal S4 from the rising/falling detection pulse generation circuit 4.

Here, consider a case where the input signal S1 is in a state as shown by waveform 7 due to superimposition of noise. At this time, a noise portion as shown by waveform 9 also appears in the output signal S2 from the differentiating circuit 2, and this noise portion crosses the zero level many times. Therefore, as shown in FIG. 4, the output signals S3. A part corresponding to the above-mentioned noise part (waveform 9) also appears in s4, and in particular, the output signal S, which is used as a peak position detection signal, generates a pulse at a position completely different from the normal peak position. This can lead to incorrect peak position detection.

Further, as a characteristic characteristic of the zero level comparator 3, a shift in the zero level and a delay in the rise response of the output signal S may occur. For example, as shown in FIG. 4, when the zero level reference in the zero level comparator 3 shifts to the position indicated by the chain line O, the output signal S3 of the zero level comparator 3 shifts to the normal output as shown by the chain line. compare, it
The width of the 177 output changes significantly, and as a result, the output signal S4 of the rising/falling detection pulse generation circuit 4 also changes as shown by the chain line, resulting in a large detection error.

The influence of this zero level shift on detection accuracy is likely to change depending on the waveform of the input signal S and its signal level, and if the waveform rises and falls slowly,
Detection of the zero level at is likely to include errors, which has a large effect on peak detection.

[Problems to be Solved by the Invention] Since the conventional peak detection circuit is configured as described above, noise superimposed on the input signal S1, a decrease in the signal level, a shift in the zero level of the zero level comparator 3, etc. has a large effect on peak detection accuracy, and there have been problems such as the inability to perform accurate peak detection.

This invention was made to solve the above-mentioned problems, and it is possible to detect a peak position without being affected by noise superimposed on the peak detected signal (input signal) or a drop in signal level. The purpose of this invention is to obtain a peak detection circuit with high detection accuracy.

[Means for Solving the Problems] The peak detection circuit according to the present invention includes a reference level generation circuit that outputs reference signals of different levels, and a peak detection signal and each reference signal from the reference level generation circuit. a plurality of comparators that compare the outputs of these comparators, a plurality of rise detection delay pulse generation circuits that detect the rise of each output of these comparators and output a delayed pulse signal after the required time has elapsed from this rise, and these rise detection delay pulse generation circuits. A plurality of AND circuits that output an AND output of the delayed pulse signal from the circuit and the output of the above-mentioned comparator one stage above each stage for each stage, and an OR circuit that outputs the OR output of each output of these AND circuits. It is constructed in advance.

[Function] In the peak detection circuit according to the present invention, the peak detected signal is compared with the reference signal at each level in each comparator, and the comparator at the level near the peak position determines whether there is an output from the comparator one level higher. The peak is detected. In other words, each comparator detects the point in time when the peak detected signal reaches each level, and after a predetermined time has elapsed from the detection point, a delayed pulse signal is output from the rising edge detection delay pulse generation circuit, and this delayed pulse signal By using an AND circuit to obtain the AND output of the output of the comparator one stage higher than that, it is determined whether the peak detected signal has reached a level one stage higher than each level, and the final Then, the OR circuit causes the peak detected signal to become 1 at the level that has reached near the peak.
Only the delayed pulse signal when it is determined that the level above the step has not been reached is extracted as a peak detection signal.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. 1st
In the figure, 21 is a full-wave rectifier circuit that full-wave rectifies the input signal S, which is a peak detected signal input from input terminal 1, and 22 is a plurality of different level reference signals L□~ set at arbitrary stages. As shown in FIG. 2(b), this is the lowest level of the level output from the standard level generating circuit 22, and the level The reference signals L2 to Ln are sequentially 1
The level output is stepped up (Ln is the highest level).

Further, 23-1 to 23-n are respective reference signals L□ to Ln from the reference level generation circuit 22 and the gold wave rectifier circuit 21.
A comparator for comparing the signal S2□ from 24-1
-24-n are comparators 23-1 to 23-, respectively.
Rising detection delay pulse generation circuits, 25-2 to 25-, detecting the rising edge of output signals C□ to Cn of output signals C□ to Cn and outputting delayed pulse signals D1 to Dn after a required time elapses from this rising edge;
n are inverting circuits 26-1 to 26-1 to invert the levels of the output signals C2 to Cn of the comparators 23-2 to 23-n, respectively;
26-n is an AND circuit, which outputs the delayed pulse signals R-Dn of the rising edge detection pulse generation circuits 24-1 to 24-n and each stage obtained through the inverting circuits 25-2 to 25-n. Comparators 23-2 to 2 above each one step
3-n and the signals I2-In, that is, when the signals match, the signals A1-A are output.

Further, 27 is an OR circuit, and AND circuits 26-1 to 26
-n output signals A to An are output by the logical sum, that is, when any of the output signals A8 to An is generated, the signal S is output.
2'l is output. A latch circuit 28 receives the output signal Sat of the OR circuit 27 and outputs a signal Sza to stop the operation of the rising edge detection delay pulse generation circuits 24-1 to 24-n.

In FIG. 1, numerals 3 and 4 are a zero level comparator and a rising/falling detection pulse generating circuit, respectively, which have the same functions as the conventional device, and these devices are as follows:
As will be described later, it is provided to detect the zero level of the input signal S and reset the latch circuit 28.

Next, the operation of the apparatus of this embodiment will be explained in Figs. 2(a) and (
This is explained by b). Note that Fig. 2(b) is similar to Fig. 2(a).
) shows the output waveforms of each part of the device when detecting the peak position at the nb section of the graph.

First, the basic operation when no noise is superimposed on the input signal S will be explained.

When the input signal S, which is the peak detected signal, is input from the input terminal 1, it is full-wave rectified by the aftereffect rectifier circuit 21, and
A signal S2□ as shown in FIG. 2(a) is obtained, and this signal Szt is input to each of the comparators 23-1 to 23-n. And each comparator 23-1 to 23-n
, the signal S21 is compared with each level of the base signal Ln from the reference level generation circuit 22, and the signals C to Cn from each of the comparators 23-1 to 23-n are calculated as shown in FIG. ), when the signal S21 is larger than each reference level, it becomes 1", and when it is smaller, II O
It becomes +1.

Therefore, in the case of the input signal S2□ shown in FIGS. 2(a) and (b), the output signal 01 of the comparators 23-1 to 23-4
ll I Tl output is generated for ~C4, and the output signals of the comparators 23-5 to 23-n at higher levels remain "0)I.In addition, in FIG. 2('b), the output signal c Illustrations of x p c s to an are omitted.

Output signals 01 to C4 of comparators 23-1 to 23-4
are the rising edge detection delay pulse generation circuits 24-1 to 24-1, respectively.
24-4, and the output of each rising detection delay pulse generation circuit 24-1 to 24-4 detects the rising time of the signals C0 to C4, and a predetermined time t (for example, when the signal S2□ After the elapse of the time required for the level to change from the level to the level one level higher, the delayed pulse signals D to D4 are input to the AND circuit 26-1, respectively, as shown in FIG.
~Output to 26-4.

At this time, each of the AND circuits 26-1 to 26-4 receives an inverted signal ?
2 to 4 are input. For example, comparator 23-4
The level "I I+" portion of the output signal C4 is inputted into the level II O11 signal (■) by the inverting circuit 25-4 to the AND circuit 26-3, and the AND circuit 26-3 outputs the signal as the delayed pulse signal D3. By taking the AND output, the output signal A3 of the AND circuit 26-3 remains at the level II OI+.In other words, it is determined that the input signal S has reached the level of the reference signal L4.Similarly,
To the output signals of AND circuits 26-1 and 26-2 〇, A
2 remains at level II 07+.

On the other hand, since the output signal C4 of the comparator 23-4 always remains at the level "0", the signal from the inverting circuit 25-2 is always at the level 11111, so the output signal A4 of the AND circuit 26-4 is , the level becomes "'1" at the same time when the delayed pulse signal D4 becomes the level "1". That is, it is determined that the input signal S1 has reached the level of the reference signal L4 but has not reached the level of the reference signal L5. Accordingly, the output signal S 27 of the OR circuit 27
also becomes level it 111, and this output signal 527 (
In other words, the delayed pulse signal D4) is output from the output terminal 5 as a peak position detection pulse.

At the same time, the detection pulse of the output signal S2□ is also input to the latch circuit 28, and as shown in the bottom row of FIG. 2(b), each rising detection delay pulse generation circuit 24-1 to
The signal S211 output from the latch circuit 28 as an operation command signal to 24-n changes from level 11111 to 1'0''', and each rise detection delay pulse generation circuit 24-1 to 24-n Even if you input C-C, it will not work.

Therefore, in this embodiment, as shown in FIG. 2(b), since the noise N is superimposed near the peak of the input signal S (or signal 521), the comparator 23-4 is Even if the comparator 23-4 malfunctions [see section N in Figure 2(b)], when the comparator 23-4 outputs the delayed pulse signal D4 after a predetermined period of time has elapsed since it first outputs the signal C4, the input signal S level is one step higher (reference signal LS)
If the
The output signal A4 of -4 is output simultaneously with the output of the delayed pulse signal RI, and each rising edge detection delayed pulse generation circuit 24-1
~24-n stops, and the output (two pulses after the N1 part) due to the malfunction of the comparator 23-4 is caused by the rising edge detection delay, as shown by the chain line in the N2 part of FIG. 2(b). The output signal of the pulse generating circuit 24-4 is inhibited and is no longer outputted, so that the peak detection accuracy will not be degraded due to malfunction due to noise.

Further, in the device of this embodiment, a plurality of level reference signals L0
Since the peak position is detected based on the comparison result between ~Ln and the input signal S, the detection accuracy is no longer affected by fluctuations in the atmosphere level or reduction in the signal level as in the prior art.

Note that the signal S2s as an operation command signal output from the latch circuit 28 is generated at the time when the next zero level (zero cross point) of the input signal S is detected by the zero level comparator 3 and the rising/falling detection pulse generation circuit 4. Then, the latch circuit 28 is reset and changes from "0" to "1".
Each of the rising edge detection delay pulse generation circuits 24-1 to 24-n becomes operational again, and the peak position detection operation for the next input waveform is restarted.

In this way, according to this embodiment, when detecting the peak position, the comparator 2 at the level near the peak position
3'-1 to 23-n, each comparator 23-1
The presence or absence of the output of the comparator one stage higher than ~23-n is determined by the inverting circuits 25-1 to 25-n and the AND By detecting with the circuits 26-1 to 26-n, even if noise is superimposed on the input signal S or the signal level has decreased, it will not be affected by it.
Detection accuracy can be greatly improved.

In the above embodiment, the input signal S is input to the full-wave rectifier circuit 2.
1, the polarity is unified to either positive or negative, and then peak detection is performed. The signal may be set in a range from positive to negative, and in this case as well, the same effect as in the above embodiment can be achieved.

Furthermore, in the above embodiments, the input signal S has a sine wave shape or a distorted wave shape, but the device of the present invention can also be applied to a sawtooth wave shape, a triangular wave shape, etc., and the same effects as in the above embodiments can be obtained. play.

[Effects of the Invention] As described above, according to the present invention, when detecting a peak position, a plurality of level reference signals are used to determine whether or not there is a comparator output one step higher than each comparator at a level near the peak position. By detecting the peak based on the comparison result between the peak detected signal and the peak detected signal, the peak can be detected, so even if noise is superimposed on the peak detected signal or the signal level has decreased,
This has the effect of providing a peak detection circuit that is free from this influence and can significantly improve detection accuracy.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a peak detection circuit according to an embodiment of the present invention, FIGS. 2(a) and 2(b) are timing charts for explaining the operation of the apparatus of the above embodiment, and FIG. 3 4 is a configuration diagram showing a conventional peak detection circuit, and FIG. 4 is a timing chart for explaining the operation of the conventional device h1. In the figure, 22-reference level generation circuit, 23-1 to 2
3-n-comparator, 24-1 to 24-n--rising detection delay pulse generation circuit, 26-1 to 26-n-
AND circuit, 27-OR circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A reference level generating circuit that outputs reference signals of different levels, multiple comparators that compare each reference signal from the same reference level generating circuit with the peak detected signal, and detecting the rise of each output from these comparators. A plurality of rising edge detection delay pulse generation circuits that output delayed pulse signals after a required time elapses from the rise of the rising edge, and the delayed pulse signals from these rising edge detection delay pulse generation circuits and the above-mentioned comparators one stage above each for each stage. 1. A peak detection circuit comprising: a plurality of AND circuits that output an AND output with outputs; and an OR circuit that outputs a logical sum of the outputs of these AND circuits.