JPS63275967A - Semiconductor measuring apparatus - Google Patents
Semiconductor measuring apparatusInfo
- Publication number
- JPS63275967A JPS63275967A JP62111595A JP11159587A JPS63275967A JP S63275967 A JPS63275967 A JP S63275967A JP 62111595 A JP62111595 A JP 62111595A JP 11159587 A JP11159587 A JP 11159587A JP S63275967 A JPS63275967 A JP S63275967A
- Authority
- JP
- Japan
- Prior art keywords
- output
- comparator
- input
- signal
- pulse train
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000005259 measurement Methods 0.000 claims abstract description 17
- 230000003321 amplification Effects 0.000 claims abstract description 13
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 13
- 230000002238 attenuated effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路の特性を測定する半導体測定
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor measuring device for measuring the characteristics of a semiconductor integrated circuit.
第４図は従来の半導体測定装置を示す構成図である。図
において、１は差動増幅器２．コンパレータ３及びパル
ス化回路４を直列に接続してなる被測定半導体集積回路
、８は被測定半導体集積回路１より出力されるパルス列
の非対称性を測定するためのカウンタ、６は入力信号源
、５は上記差動増幅器２の増幅率を決める外付抵抗であ
る。また、第５図は従来の半導体測定装置の各部の信号
波形を示す図、第６図はオフセット電圧と非対称性との
関係を示す図である。FIG. 4 is a configuration diagram showing a conventional semiconductor measuring device. In the figure, 1 is a differential amplifier 2. A semiconductor integrated circuit under test is formed by connecting a comparator 3 and a pulsing circuit 4 in series; 8 is a counter for measuring the asymmetry of the pulse train output from the semiconductor integrated circuit under test 1; 6 is an input signal source; is an external resistor that determines the amplification factor of the differential amplifier 2. Further, FIG. 5 is a diagram showing signal waveforms at various parts of a conventional semiconductor measuring device, and FIG. 6 is a diagram showing the relationship between offset voltage and asymmetry.
次に動作について説明する。Next, the operation will be explained.
まず、出力パルス列の非対称性を測定する場合、被測定
半導体集積回路１の差動入力差動出力タイプの差動増幅
器２の入力に一定振幅、一定周波数の正弦波信号■ｉを
入力信号源６により入力する。First, when measuring the asymmetry of the output pulse train, a sine wave signal with a constant amplitude and a constant frequency ■i is input to the input signal source 6 of the differential input differential output type differential amplifier 2 of the semiconductor integrated circuit under test 1. Input by.
この信号Ｖｌ＋ｓは、上記差動増幅器２により増幅され
る。このときの上記差動増幅器２の増幅率は、これに接
続された外付抵抗５により決められている。そして増幅
された信号■１はコンパレータ３に入り、交流レベルの
ゼロクロス点でコンパレータ３の出力レベルが反転する
。このコンパレータ３の出力信号■８の立上り、立下り
エツジでパルス化回路４からパルス列■。が出力される
。この出力パルス列■。の立下りエツジでトリガをかけ
、第５図に示すようにカウンタ８により立↑リエソジの
時間間隔１．．１．を測定する。パルス列の非対称特性
ｐｓは時間間隔１．．１．を用いて次式から求められる
。This signal Vl+s is amplified by the differential amplifier 2. The amplification factor of the differential amplifier 2 at this time is determined by the external resistor 5 connected thereto. The amplified signal (1) then enters the comparator 3, and the output level of the comparator 3 is inverted at the zero-crossing point of the AC level. At the rising and falling edges of the output signal 8 of the comparator 3, a pulse train 2 is generated from the pulse generator 4. is output. This output pulse train■. A trigger is applied at the falling edge of , and as shown in FIG. 5, the counter 8 determines the time interval 1. ．． 1. Measure. The asymmetric characteristic ps of the pulse train is determined by the time interval 1. ．． 1. It can be obtained from the following equation using
ところでこのパルス列の非対称性は差動増幅器２の出力
オフセット電圧及びコンパレータ３の入力オフセント電
圧により生じる。Incidentally, the asymmetry of this pulse train is caused by the output offset voltage of the differential amplifier 2 and the input offset voltage of the comparator 3.
そこでパルス列の非対称性ｐｓと上記差動増幅器２の出
力オフセット電圧及びコンパレータ３の入力オフセント
電圧によるオフセント電圧Ｖ。ｆｆとの関係を求める。Therefore, the offset voltage V is determined by the asymmetry ps of the pulse train, the output offset voltage of the differential amplifier 2, and the input offset voltage of the comparator 3. Find the relationship with ff.
１．．１！は第６図よりＬ＋−ｔｏ ２Δｔ
ｔｔ＝ｔ０＋２Δｔ ・・・（２）と表
わされ、第（１１，（２１式より
であり、また差動増幅器の入力電圧をＶｉｒｉ、増幅率
をＧとすると、
π ＧＶい
となり、第＋３１． （５）式により
となる。1. ．． 1! From FIG. 6, it is expressed as L+-to 2Δt tt=t0+2Δt (2), which is from equations (11 and (21), and if the input voltage of the differential amplifier is Viri and the amplification factor is G, , π GV, and +31. According to equation (5).
従来の半導体測定装置は以上のように構成されているの
で、出力パルス列を連続的に高分解能で時間測定しなけ
ればならず高価なカウンタが必要で、また、外来ノイズ
により、測定誤差が発生するなどの問題点があった。Conventional semiconductor measurement equipment is configured as described above, so the output pulse train must be time-measured continuously with high resolution, requiring an expensive counter, and measurement errors may occur due to external noise. There were problems such as:
この発明は上記のような問題点を解消するためになされ
たもので、外来ノイズの悪影響を低減でき、測定精度が
高くしかも安価な半導体測定装置を得ることを目的とす
る。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor measuring device that can reduce the adverse effects of external noise, has high measurement accuracy, and is inexpensive.
この発明に係る半導体測定装置は、被測定半導体集積回
路にその増幅率を１以下とした状態で一定の周波数の入
力正弦波信号を入力する信号入力手段を設け、さらに該
入力信号の振幅を変化させていったとき上記被測定回路
の出力がパルス無出力状態となったことを検出するパル
ス検出手段を設けたものである。A semiconductor measuring device according to the present invention is provided with a signal input means for inputting an input sine wave signal of a constant frequency to a semiconductor integrated circuit under test with an amplification factor of 1 or less, and further changes the amplitude of the input signal. A pulse detecting means is provided for detecting that the output of the circuit under test becomes a pulseless state when the output voltage is increased.
この発明において、被測定半導体回路への測定用入力信
号の振幅を変化させていったとき該回路の出力がパルス
無出力状態となったことを検出するようにしたから、高
価なカウンタを用いることなく、被測定回路のパルス列
の非対称性をパルス無出力状態検出時の入力信号の振幅
から求めることができ、しかも測定時被測定回路の増幅
率を１以下としているため、外来ノイズによる測定誤差
を低減できる。In this invention, when the amplitude of the measurement input signal to the semiconductor circuit under test is changed, it is detected that the output of the circuit becomes a pulseless state, so an expensive counter is not required. The asymmetry of the pulse train of the circuit under test can be determined from the amplitude of the input signal when the pulse no-output state is detected.Moreover, since the amplification factor of the circuit under test is set to 1 or less during measurement, measurement errors due to external noise are eliminated. Can be reduced.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による半導体測定装置の回路
構成を示し、図において、ｌは誤差増幅器２．コンパレ
ータ３及びパルス化回路４を直列に接続してなる被測定
半導体集積回路、７は被測定半導体集積回路１より出力
されるパルス列の有無を検出するための測定用コンパレ
ータ、６は入力信号源、５は上記差動増幅器２の増幅率
を決める外付抵抗である。FIG. 1 shows a circuit configuration of a semiconductor measuring device according to an embodiment of the present invention, in which l denotes an error amplifier 2. a semiconductor integrated circuit under test formed by connecting a comparator 3 and a pulsing circuit 4 in series; 7 a measurement comparator for detecting the presence or absence of a pulse train output from the semiconductor integrated circuit 1 under test; 6 an input signal source; 5 is an external resistor that determines the amplification factor of the differential amplifier 2.
次にこの半導体測定装置の動作について説明する。Next, the operation of this semiconductor measuring device will be explained.
まず、出力パルス列の非対称性を測定する場合、被測定
半導体集積回路１の差動入力差動出力タイプの差動増幅
器２に接続されている外付抵抗５により増幅率を１以下
に設定し、上記差動増幅器２の入力に一定周波数の正弦
波を入力信号源６により入力する。この信号は上記差動
増幅器２により減衰され、これと同時に、外来ノイズも
同様に滅衰される。この減衰された信号■いが第２図ｔ
ａｌに示すように上記差動増幅器２の出力オフセント電
圧、もしくはコンパレータ３の入力オフセット電圧より
大きな場合、信号Ｖえはコンパレータ３に入り、交流レ
ベルのゼロクロス点からオフセット電圧■。ｆｆ分だけ
大きな点でコンパレータ３の出力レベルが反転する。こ
のコンパレータ３の出力信号■３の立上り及び立下りエ
ツジで、パルス化回路４によりパルス列■。が出力され
る。First, when measuring the asymmetry of the output pulse train, the amplification factor is set to 1 or less using the external resistor 5 connected to the differential input differential output type differential amplifier 2 of the semiconductor integrated circuit under test 1. A sine wave of a constant frequency is inputted to the input of the differential amplifier 2 by an input signal source 6. This signal is attenuated by the differential amplifier 2, and at the same time, external noise is also attenuated. This attenuated signal is shown in Figure 2.
As shown in al, if it is larger than the output offset voltage of the differential amplifier 2 or the input offset voltage of the comparator 3, the signal V enters the comparator 3, and the offset voltage 2 is generated from the zero cross point of the AC level. The output level of the comparator 3 is inverted at a point larger by ff. At the rising and falling edges of the output signal (3) of the comparator 3, the pulse generator 4 generates a pulse train (2). is output.
また、上記減衰された信号■、が第２図（′ｂ）に示す
ように上記差動増幅器２の出力オフセ・ノド電圧もしく
はコンパレータ３の入力オフセット電圧より小さな場合
、コンパレータ３は動作せず出力レベルは反転せず、こ
のためパルス化回路４も動作せずパルス列は出力されな
い。ここでパルス化回路４の出力パルス列の有無はパル
ス検出用の測定用コンパレータ７により検出される。従
って、入力信号源６の振幅を変化させていったとき、パ
ルス化回路４の出力がパルス無出力状態となったことを
測定用コンパレータ７により検出することより、オフセ
ット電圧■。ｆｆが求められる。In addition, if the attenuated signal (2) is smaller than the output offset voltage of the differential amplifier 2 or the input offset voltage of the comparator 3, as shown in FIG. 2('b), the comparator 3 does not operate and outputs The level is not inverted, so the pulsing circuit 4 also does not operate and no pulse train is output. Here, the presence or absence of the output pulse train of the pulse generation circuit 4 is detected by a measurement comparator 7 for pulse detection. Therefore, when the amplitude of the input signal source 6 is changed, the measuring comparator 7 detects that the output of the pulsing circuit 4 is in a non-pulse output state, so that the offset voltage . ff is calculated.
すなわち測定用コンパレータ７の出力レベルが反転した
時の入力信号源６の振幅をＶｉｒ＋０とするとオフセッ
ト電圧Ｖ０７．はこの回路の増幅率をＧ。That is, if the amplitude of the input signal source 6 when the output level of the measurement comparator 7 is inverted is Vir+0, then the offset voltage V07. is the amplification factor of this circuit.
とじて、
■。Ｈ＝Ｇ６ Ｖｉ、、。 ・・・（８
）と表わされ、従って、パルス列の非対称性ＰＳは上記
第（６）式より
となる。Close, ■. H=G6 Vi,. ...(8
), and therefore, the asymmetry PS of the pulse train is expressed by the above equation (6).
従って、測定用コンパレータ７の出力レベルが反転する
時の入力信号源の振幅を測定することによりパルス列の
非対称性を求めることができる。Therefore, the asymmetry of the pulse train can be determined by measuring the amplitude of the input signal source when the output level of the measurement comparator 7 is inverted.
このように本実施例では、被測定半導体集積回路１への
入力信号の振幅を変化させていったときその出力がパル
ス無出力状態となったことを測定用コンパレータで検出
するようにしなので、高価なカウンタを用いることなく
、パルス列の非対称性をパルス無出力状態検出時の入力
信号の振幅から求めることができ、しかも測定時、被測
定回路１の増幅率を１以下としているため外来ノイズに
よる悪影響を低減して測定精度を向上できる。As described above, in this embodiment, when the amplitude of the input signal to the semiconductor integrated circuit under test 1 is changed, the measurement comparator detects when the output becomes a no-pulse state. The asymmetry of the pulse train can be determined from the amplitude of the input signal when the pulse no-output state is detected without using a counter, and since the amplification factor of the circuit under test 1 is set to 1 or less during measurement, there is no adverse effect due to external noise. It is possible to improve measurement accuracy by reducing
なお、上記実施例では被測定用半導体集積回路１として
その入力初段には差動増幅器を有するものを示したが、
この差動増幅器は第３図に示すように外付抵抗５及び外
付容量１０が接続された微分器９でもよく、この場合も
上記実施例と同様の効果を奏する。In the above embodiment, the semiconductor integrated circuit under test 1 has a differential amplifier at its first input stage.
This differential amplifier may be a differentiator 9 to which an external resistor 5 and an external capacitor 10 are connected as shown in FIG. 3, and in this case as well, the same effects as in the above embodiment can be achieved.
以上のように、この発明によれば、被測定半導体集積回
路への入力信号の振幅を該回路の増幅率を１以下とした
状態で変化させていったとき、該回路の出力がパルス無
出力状態となったことを検出するようにしたので、高価
なカウンタを用いることなく、パルス列の非対称性をパ
ルス無出力状態検出時の入力信号の振幅から求めること
ができ、もって外来ノイズの影響を受けにクク、安価で
かつ測定精度の高い半導体測定装置を得ることができる
。As described above, according to the present invention, when the amplitude of the input signal to the semiconductor integrated circuit under test is changed while the amplification factor of the circuit is set to 1 or less, the output of the circuit becomes pulseless. Since the state is detected, the asymmetry of the pulse train can be determined from the amplitude of the input signal when the pulse no-output state is detected, without using an expensive counter, which reduces the influence of external noise. Therefore, it is possible to obtain a semiconductor measuring device that is inexpensive and has high measurement accuracy.
第１図はこの発明の一実施例による半導体測定装置を示
す構成図、第２図はこの発明の一実施例による半導体測
定装置の各部の信号波形を示す図、第３図はこの発明の
他の実施例による半導体測定装置を示す構成図、第４図
は従来の半導体測定装置を示す構成図、第５図は従来の
半導体測定装置の各部の信号波形を示す図、第６図はオ
フセ−／ ）電圧と非対称性との関係を示す図である１
・・・被測定半導体集積回路、２・・・差動増幅器、３
・・・コンパレータ、４・・・パルス化回路、５・・・
’Ａ付低抵抗６・・・入力信号源、７・・・測定用コン
パレータ、９・・・微分器。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a block diagram showing a semiconductor measuring device according to an embodiment of the present invention, FIG. 2 is a diagram showing signal waveforms of various parts of the semiconductor measuring device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a semiconductor measuring device according to an embodiment of the present invention. FIG. 4 is a block diagram showing a conventional semiconductor measuring device, FIG. 5 is a diagram showing signal waveforms of each part of the conventional semiconductor measuring device, and FIG. 6 is a block diagram showing a conventional semiconductor measuring device. / ) is a diagram showing the relationship between voltage and asymmetry 1
...Semiconductor integrated circuit under test, 2...Differential amplifier, 3
...Comparator, 4...Pulsing circuit, 5...
'Low resistance with A 6...Input signal source, 7...Measurement comparator, 9...Differentiator. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
直列に接続してなる被測定半導体集積回路の出力パルス
列の非対称性を測定するための半導体測定装置において
、 上記差動増幅器にその増幅率を１以下とした状態で一定
周波数の入力信号を入力する信号入力手段と、 上記入力信号の振幅を変化させていったときコンパレー
タ出力が反転し、これにより上記パルス化回路の出力が
パルス無出力状態となったことを検出するパルス検出手
段とを備えたことを特徴とする半導体測定装置。(1) In a semiconductor measurement device for measuring the asymmetry of the output pulse train of a semiconductor integrated circuit under test, which is formed by connecting a differential amplifier, a comparator, and a pulse generator circuit in series, the amplification factor of the differential amplifier is a signal input means for inputting an input signal of a constant frequency in a state of 1 or less; and when the amplitude of the input signal is changed, the comparator output is inverted, so that the output of the pulsing circuit is in a non-pulse output state. What is claimed is: 1. A semiconductor measuring device comprising: a pulse detecting means for detecting that .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111595A JPS63275967A (en) | 1987-05-07 | 1987-05-07 | Semiconductor measuring apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111595A JPS63275967A (en) | 1987-05-07 | 1987-05-07 | Semiconductor measuring apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63275967A true JPS63275967A (en) | 1988-11-14 |
Family
ID=14565343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111595A Pending JPS63275967A (en) | 1987-05-07 | 1987-05-07 | Semiconductor measuring apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63275967A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149885A (en) * | 1987-10-30 | 1989-06-12 | Gaz De France | Application of mixture of chlorofluorated ether fluid and solvent to absorbing engine |
-
1987
- 1987-05-07 JP JP62111595A patent/JPS63275967A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149885A (en) * | 1987-10-30 | 1989-06-12 | Gaz De France | Application of mixture of chlorofluorated ether fluid and solvent to absorbing engine |
| JPH0786196B2 (en) * | 1987-10-30 | 1995-09-20 | ガーズ・ド・フランス | Heat absorbing medium composition consisting of chlorofluorinated ether fluid and solvent and method for producing heat and low temperature |
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